tx39.c revision 1.29       1  1.29       uch /*	$NetBSD: tx39.c,v 1.29 2002/01/05 04:47:30 uch Exp $ */
      2   1.1       uch 
      3  1.17       uch /*-
      4  1.20       uch  * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
      5  1.20       uch  * All rights reserved.
      6  1.20       uch  *
      7  1.20       uch  * This code is derived from software contributed to The NetBSD Foundation
      8  1.20       uch  * by UCHIYAMA Yasushi.
      9   1.1       uch  *
     10   1.1       uch  * Redistribution and use in source and binary forms, with or without
     11   1.1       uch  * modification, are permitted provided that the following conditions
     12   1.1       uch  * are met:
     13   1.1       uch  * 1. Redistributions of source code must retain the above copyright
     14   1.1       uch  *    notice, this list of conditions and the following disclaimer.
     15  1.16       uch  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.16       uch  *    notice, this list of conditions and the following disclaimer in the
     17  1.16       uch  *    documentation and/or other materials provided with the distribution.
     18  1.20       uch  * 3. All advertising materials mentioning features or use of this software
     19  1.20       uch  *    must display the following acknowledgement:
     20  1.20       uch  *        This product includes software developed by the NetBSD
     21  1.20       uch  *        Foundation, Inc. and its contributors.
     22  1.20       uch  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  1.20       uch  *    contributors may be used to endorse or promote products derived
     24  1.20       uch  *    from this software without specific prior written permission.
     25   1.1       uch  *
     26  1.20       uch  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  1.20       uch  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  1.20       uch  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  1.20       uch  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  1.20       uch  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  1.20       uch  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  1.20       uch  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  1.20       uch  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  1.20       uch  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  1.20       uch  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  1.20       uch  * POSSIBILITY OF SUCH DAMAGE.
     37   1.1       uch  */
     38   1.1       uch 
     39  1.27       uch #include "opt_vr41xx.h"
     40  1.27       uch #include "opt_tx39xx.h"
     41   1.1       uch #include "opt_tx39_debug.h"
     42   1.5       uch #include "m38813c.h"
     43   1.6       uch #include "tc5165buf.h"
     44   1.1       uch 
     45   1.1       uch #include <sys/param.h>
     46   1.1       uch #include <sys/systm.h>
     47   1.1       uch 
     48  1.28       uch #include <mips/cache.h>
     49  1.28       uch 
     50   1.1       uch #include <machine/locore.h>   /* cpu_id */
     51   1.1       uch #include <machine/bootinfo.h> /* bootinfo */
     52   1.1       uch #include <machine/sysconf.h>  /* platform */
     53   1.1       uch 
     54   1.6       uch #include <machine/platid.h>
     55   1.6       uch #include <machine/platid_mask.h>
     56   1.6       uch 
     57   1.1       uch #include <machine/bus.h>
     58   1.1       uch 
     59  1.26       uch #include <hpcmips/hpcmips/machdep.h> /* cpu_name, mem_cluster */
     60   1.1       uch 
     61   1.1       uch #include <hpcmips/tx/tx39biureg.h>
     62   1.1       uch #include <hpcmips/tx/tx39reg.h>
     63   1.1       uch #include <hpcmips/tx/tx39var.h>
     64   1.1       uch #ifdef TX391X
     65   1.1       uch #include <hpcmips/tx/tx3912videovar.h>
     66   1.1       uch #endif
     67   1.1       uch 
     68   1.1       uch #include <sys/termios.h>
     69   1.1       uch #include <sys/ttydefaults.h>
     70   1.1       uch #include <hpcmips/tx/tx39uartvar.h>
     71   1.1       uch #ifndef CONSPEED
     72   1.1       uch #define CONSPEED TTYDEF_SPEED
     73   1.1       uch #endif
     74   1.1       uch 
     75   1.5       uch /* console keyboard */
     76   1.5       uch #if NM38813C > 0
     77   1.5       uch #include <hpcmips/dev/m38813cvar.h>
     78   1.1       uch #endif
     79   1.6       uch #if NTC5165BUF > 0
     80   1.6       uch #include <hpcmips/dev/tc5165bufvar.h>
     81   1.6       uch #endif
     82   1.1       uch 
     83   1.1       uch struct tx_chipset_tag tx_chipset;
     84   1.1       uch 
     85   1.1       uch #ifdef TX39_DEBUG
     86   1.1       uch u_int32_t tx39debugflag;
     87   1.1       uch #endif
     88   1.1       uch 
     89  1.20       uch void	tx_init(void);
     90  1.27       uch #if defined(VR41XX) && defined(TX39XX)
     91  1.27       uch #define	TX_INTR	tx_intr
     92  1.27       uch #else
     93  1.27       uch #define	TX_INTR	cpu_intr	/* locore_mips3 directly call this */
     94  1.27       uch #endif
     95  1.27       uch 
     96  1.27       uch extern void TX_INTR(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
     97  1.27       uch 
     98  1.26       uch void	tx39clock_cpuspeed(int *, int *);
     99   1.1       uch 
    100   1.1       uch /* TX39-specific initialization vector */
    101  1.20       uch void	tx_cons_init(void);
    102  1.26       uch void    tx_fb_init(caddr_t *);
    103  1.20       uch void    tx_mem_init(paddr_t);
    104  1.20       uch void	tx_find_dram(paddr_t, paddr_t);
    105  1.20       uch void	tx_reboot(int, char *);
    106   1.1       uch 
    107   1.1       uch void
    108   1.1       uch tx_init()
    109   1.1       uch {
    110   1.1       uch 	tx_chipset_tag_t tc;
    111   1.1       uch 	int model, rev;
    112   1.8       uch 	int cpuclock;
    113   1.1       uch 
    114   1.1       uch 	tc = tx_conf_get_tag();
    115   1.1       uch 	/*
    116   1.1       uch 	 * Platform Specific Function Hooks
    117   1.1       uch 	 */
    118  1.27       uch 	platform.cpu_intr	= TX_INTR;
    119  1.25       uch 	platform.cpu_idle	= NULL; /* not implemented yet */
    120  1.25       uch 	platform.cons_init	= tx_cons_init;
    121  1.25       uch 	platform.fb_init	= tx_fb_init;
    122  1.25       uch 	platform.mem_init	= tx_mem_init;
    123  1.25       uch 	platform.reboot		= tx_reboot;
    124  1.27       uch 
    125   1.1       uch 
    126  1.19       cgd 	model = MIPS_PRID_REV(cpu_id);
    127   1.1       uch 
    128   1.1       uch 	switch (model) {
    129   1.1       uch 	default:
    130  1.23       uch 		/* Unknown TOSHIBA TX39-series */
    131  1.19       cgd 		sprintf(cpu_name, "Unknown TOSHIBA TX39-series %x", model);
    132   1.1       uch 		break;
    133   1.1       uch 	case TMPR3912:
    134   1.8       uch 		tx39clock_cpuspeed(&cpuclock, &cpuspeed);
    135   1.8       uch 
    136  1.13      sato 		sprintf(cpu_name, "TOSHIBA TMPR3912 %d.%02d MHz",
    137  1.23       uch 		    cpuclock / 1000000, (cpuclock % 1000000) / 10000);
    138  1.20       uch 		tc->tc_chipset = __TX391X;
    139   1.1       uch 		break;
    140   1.1       uch 	case TMPR3922:
    141   1.8       uch 		tx39clock_cpuspeed(&cpuclock, &cpuspeed);
    142   1.1       uch 		rev = tx_conf_read(tc, TX3922_REVISION_REG);
    143   1.8       uch 
    144  1.13      sato 		sprintf(cpu_name, "TOSHIBA TMPR3922 rev. %x.%x "
    145  1.23       uch 		    "%d.%02d MHz", (rev >> 4) & 0xf, rev & 0xf,
    146  1.23       uch 		    cpuclock / 1000000, (cpuclock % 1000000) / 10000);
    147  1.20       uch 		tc->tc_chipset = __TX392X;
    148   1.1       uch 		break;
    149   1.1       uch 	}
    150   1.1       uch }
    151   1.1       uch 
    152   1.1       uch void
    153  1.26       uch tx_fb_init(caddr_t *kernend)
    154   1.1       uch {
    155   1.1       uch #ifdef TX391X
    156  1.16       uch 	paddr_t fb_end;
    157   1.1       uch 
    158  1.16       uch 	fb_end = MIPS_KSEG0_TO_PHYS(mem_clusters[0].start +
    159  1.23       uch 	    mem_clusters[0].size - 1);
    160  1.16       uch 	tx3912video_init(MIPS_KSEG0_TO_PHYS(*kernend), &fb_end);
    161  1.16       uch 
    162   1.1       uch 	/* Skip V-RAM area */
    163  1.16       uch 	*kernend = (caddr_t)MIPS_PHYS_TO_KSEG0(fb_end);
    164   1.1       uch #endif /* TX391X */
    165   1.1       uch #ifdef TX392X
    166   1.1       uch 	/*
    167   1.1       uch 	 *  Plum V-RAM isn't accessible until pmap_bootstrap,
    168   1.7       uch 	 * at this time, frame buffer device is disabled.
    169   1.1       uch 	 */
    170   1.1       uch 	bootinfo->fb_addr = 0;
    171   1.1       uch #endif /* TX392X */
    172   1.1       uch }
    173   1.1       uch 
    174  1.14      shin void
    175  1.26       uch tx_mem_init(paddr_t kernend)
    176   1.1       uch {
    177  1.26       uch 
    178  1.14      shin 	mem_clusters[0].start = 0;
    179  1.14      shin 	mem_clusters[0].size = kernend;
    180  1.14      shin 	mem_cluster_cnt = 1;
    181  1.14      shin 	/* search DRAM bank 0 */
    182  1.14      shin 	tx_find_dram(kernend, 0x02000000);
    183   1.1       uch 
    184  1.14      shin 	/* search DRAM bank 1 */
    185  1.14      shin 	tx_find_dram(0x02000000, 0x04000000);
    186   1.2  takemura }
    187   1.2  takemura 
    188   1.2  takemura void
    189  1.26       uch tx_find_dram(paddr_t start, paddr_t end)
    190   1.2  takemura {
    191  1.14      shin 	caddr_t page, startaddr, endaddr;
    192  1.28       uch 	u_int32_t magic0, magic1;
    193  1.28       uch #define MAGIC0		(*(__volatile u_int32_t *)(page + 0))
    194  1.28       uch #define MAGIC1		(*(__volatile u_int32_t *)(page + 4))
    195  1.14      shin 
    196  1.28       uch 	startaddr = (void *)MIPS_PHYS_TO_KSEG1(start);
    197  1.28       uch 	endaddr = (void *)MIPS_PHYS_TO_KSEG1(end);
    198   1.1       uch 
    199   1.1       uch 	page = startaddr;
    200  1.14      shin 	if (badaddr(page, 4))
    201  1.14      shin 		return;
    202  1.14      shin 
    203  1.28       uch 	do {
    204  1.28       uch 		magic0 = random();
    205  1.28       uch 		magic1 = random();
    206  1.28       uch 	} while (MAGIC0 == magic0 || MAGIC0 == magic1);
    207  1.28       uch 
    208  1.28       uch 	MAGIC0 = magic0;
    209  1.28       uch 	MAGIC1 = magic1;
    210  1.14      shin 	wbflush();
    211  1.14      shin 
    212  1.28       uch 	if (MAGIC0 != magic0 || MAGIC1 != magic1)
    213  1.14      shin 		return;
    214  1.14      shin 
    215  1.14      shin 	for (page += NBPG; page < endaddr; page += NBPG) {
    216  1.14      shin 		if (badaddr(page, 4))
    217  1.14      shin 			return;
    218  1.28       uch 		if (MAGIC0 == magic0 &&
    219  1.28       uch 		    MAGIC1 == magic1) {
    220  1.17       uch 			goto memend_found;
    221   1.1       uch 		}
    222   1.1       uch 	}
    223  1.14      shin 
    224  1.17       uch 	/* check for 32MByte memory */
    225  1.17       uch 	page -= NBPG;
    226  1.28       uch 	MAGIC0 = magic0;
    227  1.28       uch 	MAGIC1 = magic1;
    228  1.17       uch 	wbflush();
    229  1.28       uch 	if (MAGIC0 != magic0 || MAGIC1 != magic1)
    230  1.17       uch 		return; /* no memory in this bank */
    231  1.17       uch 
    232  1.17       uch  memend_found:
    233  1.17       uch 	mem_clusters[mem_cluster_cnt].start = start;
    234  1.17       uch 	mem_clusters[mem_cluster_cnt].size = page - startaddr;
    235  1.29       uch 
    236  1.29       uch 	/* skip kernel area */
    237  1.29       uch 	if (mem_cluster_cnt == 1)
    238  1.29       uch 		mem_clusters[mem_cluster_cnt].size -= start;
    239  1.29       uch 
    240  1.17       uch 	mem_cluster_cnt++;
    241  1.28       uch #undef MAGIC0
    242  1.28       uch #undef MAGIC1
    243  1.14      shin }
    244  1.14      shin 
    245  1.14      shin void
    246  1.26       uch tx_reboot(int howto, char *bootstr)
    247  1.14      shin {
    248  1.26       uch 
    249  1.14      shin 	goto *(u_int32_t *)MIPS_RESET_EXC_VEC;
    250   1.1       uch }
    251   1.1       uch 
    252   1.1       uch void
    253   1.1       uch tx_cons_init()
    254   1.1       uch {
    255   1.1       uch 	int slot;
    256  1.20       uch #define CONSPLATIDMATCH(p)						\
    257   1.6       uch 	platid_match(&platid, &platid_mask_MACH_##p)
    258   1.1       uch 
    259   1.1       uch #ifdef SERIALCONSSLOT
    260   1.1       uch 	slot = SERIALCONSSLOT;
    261   1.1       uch #else
    262   1.1       uch 	slot = TX39_UARTA;
    263   1.1       uch #endif
    264   1.1       uch 	if (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) {
    265  1.23       uch 		if(txcom_cnattach(slot, CONSPEED,
    266  1.23       uch 		    (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8)) {
    267   1.1       uch 			panic("tx_cons_init: can't attach serial console.");
    268   1.1       uch 		}
    269   1.5       uch 	} else {
    270   1.6       uch #if NM38813C > 0
    271   1.6       uch 		if(CONSPLATIDMATCH(VICTOR_INTERLINK) &&
    272  1.23       uch 		    m38813c_cnattach(TX39_SYSADDR_CARD1)) {
    273  1.10       uch 			goto panic;
    274   1.6       uch 		}
    275   1.6       uch #endif
    276   1.6       uch #if NTC5165BUF > 0
    277  1.10       uch 		if(CONSPLATIDMATCH(COMPAQ_C) &&
    278  1.23       uch 		    tc5165buf_cnattach(TX39_SYSADDR_CS3)) {
    279  1.10       uch 			goto panic;
    280  1.10       uch 		}
    281  1.10       uch 
    282   1.6       uch 		if(CONSPLATIDMATCH(SHARP_TELIOS) &&
    283  1.23       uch 		    tc5165buf_cnattach(TX39_SYSADDR_CS1)) {
    284  1.10       uch 			goto panic;
    285  1.10       uch 		}
    286  1.10       uch 
    287  1.10       uch 		if(CONSPLATIDMATCH(SHARP_MOBILON) &&
    288  1.23       uch 		    tc5165buf_cnattach(TX39_SYSADDR_MCS0)) {
    289  1.10       uch 			goto panic;
    290   1.5       uch 		}
    291   1.5       uch #endif
    292   1.1       uch 	}
    293  1.10       uch 
    294  1.10       uch 	return;
    295  1.10       uch  panic:
    296  1.10       uch 	panic("tx_cons_init: can't init console");
    297  1.10       uch 	/* NOTREACHED */
    298   1.1       uch }
    299   1.1       uch 
    300   1.1       uch void
    301  1.26       uch tx_conf_register_intr(tx_chipset_tag_t t, void *intrt)
    302   1.1       uch {
    303  1.26       uch 
    304  1.20       uch 	KASSERT(t == &tx_chipset);
    305   1.1       uch 	tx_chipset.tc_intrt = intrt;
    306   1.1       uch }
    307   1.1       uch 
    308   1.9       uch void
    309  1.26       uch tx_conf_register_power(tx_chipset_tag_t t, void *powert)
    310   1.9       uch {
    311  1.26       uch 
    312  1.20       uch 	KASSERT(t == &tx_chipset);
    313   1.9       uch 	tx_chipset.tc_powert = powert;
    314   1.9       uch }
    315   1.9       uch 
    316   1.9       uch void
    317  1.26       uch tx_conf_register_clock(tx_chipset_tag_t t, void *clockt)
    318   1.9       uch {
    319  1.26       uch 
    320  1.20       uch 	KASSERT(t == &tx_chipset);
    321   1.9       uch 	tx_chipset.tc_clockt = clockt;
    322  1.11       uch }
    323  1.11       uch 
    324  1.11       uch void
    325  1.26       uch tx_conf_register_sound(tx_chipset_tag_t t, void *soundt)
    326  1.11       uch {
    327  1.26       uch 
    328  1.20       uch 	KASSERT(t == &tx_chipset);
    329  1.11       uch 	tx_chipset.tc_soundt = soundt;
    330  1.18       uch }
    331  1.18       uch 
    332  1.18       uch void
    333  1.26       uch tx_conf_register_video(tx_chipset_tag_t t, void *videot)
    334  1.18       uch {
    335  1.26       uch 
    336  1.20       uch 	KASSERT(t == &tx_chipset);
    337  1.18       uch 	tx_chipset.tc_videot = videot;
    338   1.9       uch }
    339   1.1       uch 
    340   1.1       uch int
    341  1.26       uch __is_set_print(u_int32_t reg, int mask, char *name)
    342   1.1       uch {
    343   1.9       uch 	const char onoff[2] = "_x";
    344   1.9       uch 	int ret = reg & mask ? 1 : 0;
    345   1.9       uch 
    346   1.9       uch 	printf("%s[%c] ", name, onoff[ret]);
    347   1.9       uch 
    348  1.23       uch 	return (ret);
    349   1.1       uch }
    350