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tx39.c revision 1.12 
      1 /*	$NetBSD: tx39.c,v 1.12 2000/01/16 21:47:00 uch Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1999, 2000, by UCHIYAMA Yasushi
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. The name of the developer may NOT be used to endorse or promote products
     13  *    derived from this software without specific prior written permission.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     25  * SUCH DAMAGE.
     26  *
     27  */
     28 
     29 #include "opt_tx39_debug.h"
     30 #include "m38813c.h"
     31 #include "tc5165buf.h"
     32 
     33 #include <sys/param.h>
     34 #include <sys/systm.h>
     35 #include <sys/device.h>
     36 
     37 #include <machine/locore.h>   /* cpu_id */
     38 #include <machine/bootinfo.h> /* bootinfo */
     39 #include <machine/sysconf.h>  /* platform */
     40 
     41 #include <machine/platid.h>
     42 #include <machine/platid_mask.h>
     43 
     44 #include <machine/bus.h>
     45 #include <machine/intr.h>
     46 
     47 #include <hpcmips/hpcmips/machdep.h> /* cpu_model */
     48 
     49 #include <hpcmips/tx/tx39biureg.h>
     50 #include <hpcmips/tx/tx39reg.h>
     51 #include <hpcmips/tx/tx39var.h>
     52 #ifdef TX391X
     53 #include <hpcmips/tx/tx3912videovar.h>
     54 #endif
     55 
     56 #include <sys/termios.h>
     57 #include <sys/ttydefaults.h>
     58 #include <hpcmips/tx/tx39uartvar.h>
     59 #ifndef CONSPEED
     60 #define CONSPEED TTYDEF_SPEED
     61 #endif
     62 
     63 /* console keyboard */
     64 #if NM38813C > 0
     65 #include <hpcmips/dev/m38813cvar.h>
     66 #endif
     67 #if NTC5165BUF > 0
     68 #include <hpcmips/dev/tc5165bufvar.h>
     69 #endif
     70 
     71 extern unsigned nullclkread __P((void));
     72 extern unsigned (*clkread) __P((void));
     73 
     74 struct tx_chipset_tag tx_chipset;
     75 
     76 #ifdef TX39_DEBUG
     77 u_int32_t tx39debugflag;
     78 #endif
     79 
     80 void	tx_init __P((void));
     81 int	tx39icu_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t));
     82 int	tx39_find_dram __P((u_int32_t, u_int32_t));
     83 void	tx39clock_cpuspeed __P((int*, int*));
     84 
     85 /* TX39-specific initialization vector */
     86 void	tx_os_init __P((void));
     87 void	tx_bus_reset __P((void));
     88 void	tx_cons_init __P((void));
     89 void	tx_device_register __P((struct device *, void *));
     90 void    tx_fb_init __P((caddr_t*));
     91 int     tx_mem_init __P((caddr_t));
     92 void	tx_reboot __P((int howto, char *bootstr));
     93 int	tx_intr __P((u_int32_t mask, u_int32_t pc, u_int32_t statusReg,
     94 		     u_int32_t causeReg));
     95 
     96 void
     97 tx_init()
     98 {
     99 	tx_chipset_tag_t tc;
    100 	int model, rev;
    101 	int cpuclock;
    102 
    103 	tc = tx_conf_get_tag();
    104 	/*
    105 	 * Platform Specific Function Hooks
    106 	 */
    107 	platform.os_init = tx_os_init;
    108 	platform.bus_reset = tx_bus_reset;
    109 	platform.cons_init = tx_cons_init;
    110 	platform.device_register = tx_device_register;
    111 	platform.fb_init = tx_fb_init;
    112 	platform.mem_init = tx_mem_init;
    113 	platform.reboot = tx_reboot;
    114 
    115 	model = (cpu_id.cpu.cp_majrev << 4)| cpu_id.cpu.cp_minrev;
    116 
    117 	switch (model) {
    118 	default:
    119 		 /* Unknown TOSHIBA TX39-series */
    120 		sprintf(cpu_model, "Unknown TOSHIBA TX39-series %x.%x",
    121 			cpu_id.cpu.cp_majrev, cpu_id.cpu.cp_minrev);
    122 		break;
    123 	case TMPR3912:
    124 		tx39clock_cpuspeed(&cpuclock, &cpuspeed);
    125 
    126 		sprintf(cpu_model, "TOSHIBA TMPR3912 %d.%02d MHz",
    127 			cpuclock / 1000000, (cpuclock % 1000000) / 10000);
    128 		break;
    129 	case TMPR3922:
    130 		tx39clock_cpuspeed(&cpuclock, &cpuspeed);
    131 		rev = tx_conf_read(tc, TX3922_REVISION_REG);
    132 
    133 		sprintf(cpu_model, "TOSHIBA TMPR3922 rev. %x.%x "
    134 			"%d.%02d MHz", (rev >> 4) & 0xf, rev & 0xf,
    135 			cpuclock / 1000000, (cpuclock % 1000000) / 10000);
    136 		break;
    137 	}
    138 }
    139 
    140 void
    141 tx_os_init()
    142 {
    143 	/*
    144 	 * Set up interrupt handling and I/O addresses.
    145 	 */
    146 	mips_hardware_intr = tx39icu_intr;
    147 
    148 	splvec.splbio = MIPS_SPL_2_4;
    149 	splvec.splnet = MIPS_SPL_2_4;
    150 	splvec.spltty = MIPS_SPL_2_4;
    151 	splvec.splimp = MIPS_SPL_2_4;
    152 	splvec.splclock = MIPS_SPL_2_4;
    153 	splvec.splstatclock = MIPS_SPL_2_4;
    154 
    155 	/* no high resolution timer circuit; possibly never called */
    156 	clkread = nullclkread;
    157 }
    158 
    159 void
    160 tx_fb_init(kernend)
    161 	caddr_t *kernend;
    162 {
    163 #ifdef TX391X
    164 	tx_chipset_tag_t tc;
    165 	u_int32_t fb_start, fb_addr, fb_size, fb_line_bytes;
    166 
    167 	/* Initialize to access TX39 configuration register */
    168 	tc = tx_conf_get_tag();
    169 
    170 	fb_start = MIPS_KSEG0_TO_PHYS(*kernend);
    171 	tx3912video_init(tc, fb_start, bootinfo->fb_width,
    172 			bootinfo->fb_height, &fb_addr, &fb_size,
    173 			&fb_line_bytes);
    174 
    175 	/* Setup bootinfo */
    176 	bootinfo->fb_line_bytes = fb_line_bytes;
    177 	bootinfo->fb_addr = (unsigned char*)MIPS_PHYS_TO_KSEG1(fb_addr);
    178 
    179 	/* Skip V-RAM area */
    180 	*kernend += fb_size;
    181 #endif /* TX391X */
    182 #ifdef TX392X
    183 	/*
    184 	 *  Plum V-RAM isn't accessible until pmap_bootstrap,
    185 	 * at this time, frame buffer device is disabled.
    186 	 */
    187 	bootinfo->fb_addr = 0;
    188 #endif /* TX392X */
    189 }
    190 
    191 int
    192 tx_mem_init(kernend)
    193 	caddr_t kernend; /* kseg0 */
    194 {
    195 	u_int32_t startaddr, endaddr;
    196 	int npage, xpage, kpage;
    197 
    198 	startaddr = MIPS_PHYS_TO_KSEG1(
    199 		(btoc((u_int32_t)kernend - MIPS_KSEG0_START)) << PGSHIFT);
    200 	endaddr = MIPS_PHYS_TO_KSEG1(TX39_SYSADDR_DRAMBANK0CS1 +
    201 				     TX39_SYSADDR_DRAMBANK_LEN);
    202 	kpage = btoc(MIPS_KSEG1_TO_PHYS(startaddr));
    203 
    204 	/* D-RAM bank0 */
    205 	npage = tx39_find_dram(startaddr, endaddr);
    206 
    207 	printf("DRAM bank0: %d pages (%dMByte) reserved %d pages\n",
    208 	       npage + 1, ((npage  + 1) * NBPG) / 0x100000, kpage + 1);
    209 	npage -= kpage; /* exclude kernel area */
    210 
    211 	/* Clear DRAM area */
    212 	memset((void*)startaddr, 0, npage * NBPG);
    213 
    214 	/* D-RAM bank1 XXX find only. not usable yet */
    215 	startaddr = MIPS_PHYS_TO_KSEG1(TX39_SYSADDR_DRAMBANK1CS1);
    216 	endaddr = MIPS_PHYS_TO_KSEG1(TX39_SYSADDR_DRAMBANK1CS1 +
    217 				     TX39_SYSADDR_DRAMBANK_LEN);
    218 	xpage = tx39_find_dram(startaddr, endaddr);
    219 	printf("DRAM bank1: %d pages (%dMByte) ...but not usable yet\n",
    220 	       xpage + 1, ((xpage + 1) * NBPG) / 0x100000);
    221 
    222 	/*
    223 	 *  Clear currently unused D-RAM area
    224 	 *  (For reboot Windows CE clearly)
    225 	 */
    226 	memset((void*)startaddr, 0, npage * NBPG);
    227 	memset((void*)(KERNBASE + 0x400), 0,
    228 	       KERNTEXTOFF - KERNBASE - 0x800);
    229 
    230 	return npage; /* Return bank0's memory only */
    231 }
    232 
    233 void
    234 tx_reboot(howto, bootstr)
    235 	int howto;
    236 	char *bootstr;
    237 {
    238 	goto *(u_int32_t *)MIPS_RESET_EXC_VEC;
    239 }
    240 
    241 int
    242 tx39_find_dram(startaddr, endaddr)
    243 	u_int32_t startaddr; /* kseg1 */
    244 	u_int32_t endaddr;    /* kseg1 */
    245 {
    246 #define DRAM_MAGIC0 0xac1dcafe
    247 #define DRAM_MAGIC1 0x19700220
    248 	u_int32_t page;
    249 	int npage;
    250 
    251 	page = startaddr;
    252 	((volatile int *)page)[0] = DRAM_MAGIC0;
    253 	((volatile int *)page)[4] = DRAM_MAGIC1;
    254 	page += NBPG;
    255 	for (npage = 0; page < endaddr; page += NBPG, npage++) {
    256 		if ((((volatile int *)page)[0] == DRAM_MAGIC0 &&
    257 		     ((volatile int *)page)[4] == DRAM_MAGIC1)) {
    258 			return npage;
    259 		}
    260 	}
    261 	/* no memory in this bank */
    262 	return 0;
    263 }
    264 
    265 void
    266 tx_bus_reset()
    267 {
    268 	/* hpcmips port don't use */
    269 }
    270 
    271 void
    272 tx_cons_init()
    273 {
    274 	int slot;
    275 #define CONSPLATIDMATCH(p) \
    276 	platid_match(&platid, &platid_mask_MACH_##p)
    277 
    278 #ifdef SERIALCONSSLOT
    279 	slot = SERIALCONSSLOT;
    280 #else
    281 	slot = TX39_UARTA;
    282 #endif
    283 	if (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) {
    284 		if(txcom_cnattach(slot, CONSPEED,
    285 				  (TTYDEF_CFLAG & ~(CSIZE | PARENB)) |
    286 				  CS8)) {
    287 			panic("tx_cons_init: can't attach serial console.");
    288 		}
    289 	} else {
    290 #if NM38813C > 0
    291 		if(CONSPLATIDMATCH(VICTOR_INTERLINK) &&
    292 		   m38813c_cnattach(TX39_SYSADDR_CARD1)) {
    293 			goto panic;
    294 		}
    295 #endif
    296 #if NTC5165BUF > 0
    297 		if(CONSPLATIDMATCH(COMPAQ_C) &&
    298 		   tc5165buf_cnattach(TX39_SYSADDR_CS3)) {
    299 			goto panic;
    300 		}
    301 
    302 		if(CONSPLATIDMATCH(SHARP_TELIOS) &&
    303 		   tc5165buf_cnattach(TX39_SYSADDR_CS1)) {
    304 			goto panic;
    305 		}
    306 
    307 		if(CONSPLATIDMATCH(SHARP_MOBILON) &&
    308 		   tc5165buf_cnattach(TX39_SYSADDR_MCS0)) {
    309 			goto panic;
    310 		}
    311 #endif
    312 	}
    313 
    314 	return;
    315  panic:
    316 	panic("tx_cons_init: can't init console");
    317 	/* NOTREACHED */
    318 }
    319 
    320 void
    321 tx_device_register(dev, aux)
    322 	struct device *dev;
    323 	void *aux;
    324 {
    325 	/* hpcmips port don't use */
    326 }
    327 
    328 void
    329 tx_conf_register_intr(t, intrt)
    330 	tx_chipset_tag_t t;
    331 	void *intrt;
    332 {
    333 	if (tx_chipset.tc_intrt) {
    334 		panic("duplicate intrt");
    335 	}
    336 
    337 	if (t != &tx_chipset) {
    338 		panic("bogus tx_chipset_tag");
    339 	}
    340 
    341 	tx_chipset.tc_intrt = intrt;
    342 }
    343 
    344 void
    345 tx_conf_register_power(t, powert)
    346 	tx_chipset_tag_t t;
    347 	void *powert;
    348 {
    349 	if (tx_chipset.tc_powert) {
    350 		panic("duplicate powert");
    351 	}
    352 
    353 	if (t != &tx_chipset) {
    354 		panic("bogus tx_chipset_tag");
    355 	}
    356 
    357 	tx_chipset.tc_powert = powert;
    358 }
    359 
    360 void
    361 tx_conf_register_clock(t, clockt)
    362 	tx_chipset_tag_t t;
    363 	void *clockt;
    364 {
    365 	if (tx_chipset.tc_clockt) {
    366 		panic("duplicate clockt");
    367 	}
    368 
    369 	if (t != &tx_chipset) {
    370 		panic("bogus tx_chipset_tag");
    371 	}
    372 
    373 	tx_chipset.tc_clockt = clockt;
    374 }
    375 
    376 void
    377 tx_conf_register_sound(t, soundt)
    378 	tx_chipset_tag_t t;
    379 	void *soundt;
    380 {
    381 	if (t != &tx_chipset) {
    382 		panic("bogus tx_chipset_tag");
    383 	}
    384 
    385 	tx_chipset.tc_soundt = soundt;
    386 }
    387 
    388 void
    389 tx_conf_register_ioman(t, iomant)
    390 	tx_chipset_tag_t t;
    391 	void *iomant;
    392 {
    393 	if (tx_chipset.tc_iomant) {
    394 		panic("duplicate iomant");
    395 	}
    396 
    397 	if (t != &tx_chipset) {
    398 		panic("bogus tx_chipset_tag");
    399 	}
    400 
    401 	tx_chipset.tc_iomant = iomant;
    402 }
    403 
    404 #ifdef TX39_PREFER_FUNCTION
    405 tx_chipset_tag_t
    406 tx_conf_get_tag()
    407 {
    408 	return (tx_chipset_tag_t)&tx_chipset;
    409 }
    410 
    411 txreg_t
    412 tx_conf_read(t, reg)
    413 	tx_chipset_tag_t t;
    414 	int reg;
    415 {
    416 	return *((volatile txreg_t*)(TX39_SYSADDR_CONFIG_REG_KSEG1 + reg));
    417 }
    418 
    419 void
    420 tx_conf_write(t, reg, val)
    421 	tx_chipset_tag_t t;
    422 	int reg;
    423 	txreg_t val;
    424 {
    425 	*((volatile txreg_t*)(TX39_SYSADDR_CONFIG_REG_KSEG1 + reg)) = val;
    426 }
    427 #endif /* TX39_PREFER_FUNCTION */
    428 
    429 int
    430 __is_set_print(reg, mask, name)
    431 	u_int32_t reg;
    432 	int mask;
    433 	char *name;
    434 {
    435 	const char onoff[2] = "_x";
    436 	int ret = reg & mask ? 1 : 0;
    437 
    438 	printf("%s[%c] ", name, onoff[ret]);
    439 
    440 	return ret;
    441 }
    442