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tx39.c revision 1.14 
      1 /*	$NetBSD: tx39.c,v 1.14 2000/02/21 13:46:04 shin Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1999, 2000, by UCHIYAMA Yasushi
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. The name of the developer may NOT be used to endorse or promote products
     13  *    derived from this software without specific prior written permission.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     25  * SUCH DAMAGE.
     26  *
     27  */
     28 
     29 #include "opt_tx39_debug.h"
     30 #include "m38813c.h"
     31 #include "tc5165buf.h"
     32 
     33 #include <sys/param.h>
     34 #include <sys/systm.h>
     35 #include <sys/device.h>
     36 #include <sys/kcore.h>
     37 
     38 #include <machine/locore.h>   /* cpu_id */
     39 #include <machine/bootinfo.h> /* bootinfo */
     40 #include <machine/sysconf.h>  /* platform */
     41 
     42 #include <machine/platid.h>
     43 #include <machine/platid_mask.h>
     44 
     45 #include <machine/bus.h>
     46 #include <machine/intr.h>
     47 
     48 #include <hpcmips/hpcmips/machdep.h> /* cpu_name */
     49 
     50 #include <hpcmips/tx/tx39biureg.h>
     51 #include <hpcmips/tx/tx39reg.h>
     52 #include <hpcmips/tx/tx39var.h>
     53 #ifdef TX391X
     54 #include <hpcmips/tx/tx3912videovar.h>
     55 #endif
     56 
     57 #include <sys/termios.h>
     58 #include <sys/ttydefaults.h>
     59 #include <hpcmips/tx/tx39uartvar.h>
     60 #ifndef CONSPEED
     61 #define CONSPEED TTYDEF_SPEED
     62 #endif
     63 
     64 /* console keyboard */
     65 #if NM38813C > 0
     66 #include <hpcmips/dev/m38813cvar.h>
     67 #endif
     68 #if NTC5165BUF > 0
     69 #include <hpcmips/dev/tc5165bufvar.h>
     70 #endif
     71 
     72 extern unsigned nullclkread __P((void));
     73 extern unsigned (*clkread) __P((void));
     74 
     75 struct tx_chipset_tag tx_chipset;
     76 
     77 #ifdef TX39_DEBUG
     78 u_int32_t tx39debugflag;
     79 #endif
     80 
     81 void	tx_init __P((void));
     82 int	tx39icu_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t));
     83 void	tx39clock_cpuspeed __P((int*, int*));
     84 
     85 /* TX39-specific initialization vector */
     86 void	tx_os_init __P((void));
     87 void	tx_bus_reset __P((void));
     88 void	tx_cons_init __P((void));
     89 void	tx_device_register __P((struct device *, void *));
     90 void    tx_fb_init __P((caddr_t*));
     91 void    tx_mem_init __P((paddr_t));
     92 void	tx_find_dram __P((paddr_t, paddr_t));
     93 void	tx_reboot __P((int howto, char *bootstr));
     94 int	tx_intr __P((u_int32_t mask, u_int32_t pc, u_int32_t statusReg,
     95 		     u_int32_t causeReg));
     96 
     97 extern phys_ram_seg_t mem_clusters[];
     98 extern int mem_cluster_cnt;
     99 
    100 void
    101 tx_init()
    102 {
    103 	tx_chipset_tag_t tc;
    104 	int model, rev;
    105 	int cpuclock;
    106 
    107 	tc = tx_conf_get_tag();
    108 	/*
    109 	 * Platform Specific Function Hooks
    110 	 */
    111 	platform.os_init = tx_os_init;
    112 	platform.bus_reset = tx_bus_reset;
    113 	platform.cons_init = tx_cons_init;
    114 	platform.device_register = tx_device_register;
    115 	platform.fb_init = tx_fb_init;
    116 	platform.mem_init = tx_mem_init;
    117 	platform.reboot = tx_reboot;
    118 
    119 	model = (cpu_id.cpu.cp_majrev << 4)| cpu_id.cpu.cp_minrev;
    120 
    121 	switch (model) {
    122 	default:
    123 		 /* Unknown TOSHIBA TX39-series */
    124 		sprintf(cpu_name, "Unknown TOSHIBA TX39-series %x.%x",
    125 			cpu_id.cpu.cp_majrev, cpu_id.cpu.cp_minrev);
    126 		break;
    127 	case TMPR3912:
    128 		tx39clock_cpuspeed(&cpuclock, &cpuspeed);
    129 
    130 		sprintf(cpu_name, "TOSHIBA TMPR3912 %d.%02d MHz",
    131 			cpuclock / 1000000, (cpuclock % 1000000) / 10000);
    132 		break;
    133 	case TMPR3922:
    134 		tx39clock_cpuspeed(&cpuclock, &cpuspeed);
    135 		rev = tx_conf_read(tc, TX3922_REVISION_REG);
    136 
    137 		sprintf(cpu_name, "TOSHIBA TMPR3922 rev. %x.%x "
    138 			"%d.%02d MHz", (rev >> 4) & 0xf, rev & 0xf,
    139 			cpuclock / 1000000, (cpuclock % 1000000) / 10000);
    140 		break;
    141 	}
    142 }
    143 
    144 void
    145 tx_os_init()
    146 {
    147 	/*
    148 	 * Set up interrupt handling and I/O addresses.
    149 	 */
    150 	mips_hardware_intr = tx39icu_intr;
    151 
    152 	splvec.splbio = MIPS_SPL_2_4;
    153 	splvec.splnet = MIPS_SPL_2_4;
    154 	splvec.spltty = MIPS_SPL_2_4;
    155 	splvec.splimp = MIPS_SPL_2_4;
    156 	splvec.splclock = MIPS_SPL_2_4;
    157 	splvec.splstatclock = MIPS_SPL_2_4;
    158 
    159 	/* no high resolution timer circuit; possibly never called */
    160 	clkread = nullclkread;
    161 }
    162 
    163 void
    164 tx_fb_init(kernend)
    165 	caddr_t *kernend;
    166 {
    167 #ifdef TX391X
    168 	tx_chipset_tag_t tc;
    169 	u_int32_t fb_start, fb_addr, fb_size, fb_line_bytes;
    170 
    171 	/* Initialize to access TX39 configuration register */
    172 	tc = tx_conf_get_tag();
    173 
    174 	fb_start = MIPS_KSEG0_TO_PHYS(*kernend);
    175 	tx3912video_init(tc, fb_start, bootinfo->fb_width,
    176 			bootinfo->fb_height, &fb_addr, &fb_size,
    177 			&fb_line_bytes);
    178 
    179 	/* Setup bootinfo */
    180 	bootinfo->fb_line_bytes = fb_line_bytes;
    181 	bootinfo->fb_addr = (unsigned char*)MIPS_PHYS_TO_KSEG1(fb_addr);
    182 
    183 	/* Skip V-RAM area */
    184 	*kernend += fb_size;
    185 #endif /* TX391X */
    186 #ifdef TX392X
    187 	/*
    188 	 *  Plum V-RAM isn't accessible until pmap_bootstrap,
    189 	 * at this time, frame buffer device is disabled.
    190 	 */
    191 	bootinfo->fb_addr = 0;
    192 #endif /* TX392X */
    193 }
    194 
    195 void
    196 tx_mem_init(kernend)
    197 	paddr_t kernend;
    198 {
    199 	mem_clusters[0].start = 0;
    200 	mem_clusters[0].size = kernend;
    201 	mem_cluster_cnt = 1;
    202 	/* search DRAM bank 0 */
    203 	tx_find_dram(kernend, 0x02000000);
    204 
    205 	/* search DRAM bank 1 */
    206 	tx_find_dram(0x02000000, 0x04000000);
    207 	/*
    208 	 *  Clear currently unused D-RAM area
    209 	 *  (For reboot Windows CE clearly)
    210 	 */
    211 	memset((void *)(KERNBASE + 0x400), 0, KERNTEXTOFF -
    212 	       (KERNBASE + 0x800));
    213 }
    214 
    215 void
    216 tx_find_dram(start, end)
    217 	paddr_t start, end;
    218 {
    219 	caddr_t page, startaddr, endaddr;
    220 
    221 	startaddr = (void*)MIPS_PHYS_TO_KSEG1(start);
    222 	endaddr = (void*)MIPS_PHYS_TO_KSEG1(end);
    223 
    224 #define DRAM_MAGIC0 0xac1dcafe
    225 #define DRAM_MAGIC1 0x19700220
    226 
    227 	page = startaddr;
    228 	if (badaddr(page, 4))
    229 		return;
    230 
    231 	*(volatile int *)(page+0) = DRAM_MAGIC0;
    232 	*(volatile int *)(page+4) = DRAM_MAGIC1;
    233 	wbflush();
    234 
    235 	if (*(volatile int *)(page+0) != DRAM_MAGIC0 ||
    236 	    *(volatile int *)(page+4) != DRAM_MAGIC1)
    237 		return;
    238 
    239 	for (page += NBPG; page < endaddr; page += NBPG) {
    240 		if (badaddr(page, 4))
    241 			return;
    242 
    243 		if (*(volatile int *)(page+0) == DRAM_MAGIC0 &&
    244 		    *(volatile int *)(page+4) == DRAM_MAGIC1) {
    245 			mem_clusters[mem_cluster_cnt].start = start;
    246 			mem_clusters[mem_cluster_cnt].size =
    247 				page - startaddr;
    248 			/* skip kernel area */
    249 			if (mem_cluster_cnt == 1)
    250 				mem_clusters[mem_cluster_cnt].size -= start;
    251 
    252 			mem_cluster_cnt++;
    253 
    254 			return;
    255 		}
    256 	}
    257 
    258 	/* no memory in this bank */
    259 	return;
    260 }
    261 
    262 void
    263 tx_reboot(howto, bootstr)
    264 	int howto;
    265 	char *bootstr;
    266 {
    267 	goto *(u_int32_t *)MIPS_RESET_EXC_VEC;
    268 }
    269 
    270 void
    271 tx_bus_reset()
    272 {
    273 	/* hpcmips port don't use */
    274 }
    275 
    276 void
    277 tx_cons_init()
    278 {
    279 	int slot;
    280 #define CONSPLATIDMATCH(p) \
    281 	platid_match(&platid, &platid_mask_MACH_##p)
    282 
    283 #ifdef SERIALCONSSLOT
    284 	slot = SERIALCONSSLOT;
    285 #else
    286 	slot = TX39_UARTA;
    287 #endif
    288 	if (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) {
    289 		if(txcom_cnattach(slot, CONSPEED,
    290 				  (TTYDEF_CFLAG & ~(CSIZE | PARENB)) |
    291 				  CS8)) {
    292 			panic("tx_cons_init: can't attach serial console.");
    293 		}
    294 	} else {
    295 #if NM38813C > 0
    296 		if(CONSPLATIDMATCH(VICTOR_INTERLINK) &&
    297 		   m38813c_cnattach(TX39_SYSADDR_CARD1)) {
    298 			goto panic;
    299 		}
    300 #endif
    301 #if NTC5165BUF > 0
    302 		if(CONSPLATIDMATCH(COMPAQ_C) &&
    303 		   tc5165buf_cnattach(TX39_SYSADDR_CS3)) {
    304 			goto panic;
    305 		}
    306 
    307 		if(CONSPLATIDMATCH(SHARP_TELIOS) &&
    308 		   tc5165buf_cnattach(TX39_SYSADDR_CS1)) {
    309 			goto panic;
    310 		}
    311 
    312 		if(CONSPLATIDMATCH(SHARP_MOBILON) &&
    313 		   tc5165buf_cnattach(TX39_SYSADDR_MCS0)) {
    314 			goto panic;
    315 		}
    316 #endif
    317 	}
    318 
    319 	return;
    320  panic:
    321 	panic("tx_cons_init: can't init console");
    322 	/* NOTREACHED */
    323 }
    324 
    325 void
    326 tx_device_register(dev, aux)
    327 	struct device *dev;
    328 	void *aux;
    329 {
    330 	/* hpcmips port don't use */
    331 }
    332 
    333 void
    334 tx_conf_register_intr(t, intrt)
    335 	tx_chipset_tag_t t;
    336 	void *intrt;
    337 {
    338 	if (tx_chipset.tc_intrt) {
    339 		panic("duplicate intrt");
    340 	}
    341 
    342 	if (t != &tx_chipset) {
    343 		panic("bogus tx_chipset_tag");
    344 	}
    345 
    346 	tx_chipset.tc_intrt = intrt;
    347 }
    348 
    349 void
    350 tx_conf_register_power(t, powert)
    351 	tx_chipset_tag_t t;
    352 	void *powert;
    353 {
    354 	if (tx_chipset.tc_powert) {
    355 		panic("duplicate powert");
    356 	}
    357 
    358 	if (t != &tx_chipset) {
    359 		panic("bogus tx_chipset_tag");
    360 	}
    361 
    362 	tx_chipset.tc_powert = powert;
    363 }
    364 
    365 void
    366 tx_conf_register_clock(t, clockt)
    367 	tx_chipset_tag_t t;
    368 	void *clockt;
    369 {
    370 	if (tx_chipset.tc_clockt) {
    371 		panic("duplicate clockt");
    372 	}
    373 
    374 	if (t != &tx_chipset) {
    375 		panic("bogus tx_chipset_tag");
    376 	}
    377 
    378 	tx_chipset.tc_clockt = clockt;
    379 }
    380 
    381 void
    382 tx_conf_register_sound(t, soundt)
    383 	tx_chipset_tag_t t;
    384 	void *soundt;
    385 {
    386 	if (t != &tx_chipset) {
    387 		panic("bogus tx_chipset_tag");
    388 	}
    389 
    390 	tx_chipset.tc_soundt = soundt;
    391 }
    392 
    393 void
    394 tx_conf_register_ioman(t, iomant)
    395 	tx_chipset_tag_t t;
    396 	void *iomant;
    397 {
    398 	if (tx_chipset.tc_iomant) {
    399 		panic("duplicate iomant");
    400 	}
    401 
    402 	if (t != &tx_chipset) {
    403 		panic("bogus tx_chipset_tag");
    404 	}
    405 
    406 	tx_chipset.tc_iomant = iomant;
    407 }
    408 
    409 #ifdef TX39_PREFER_FUNCTION
    410 tx_chipset_tag_t
    411 tx_conf_get_tag()
    412 {
    413 	return (tx_chipset_tag_t)&tx_chipset;
    414 }
    415 
    416 txreg_t
    417 tx_conf_read(t, reg)
    418 	tx_chipset_tag_t t;
    419 	int reg;
    420 {
    421 	return *((volatile txreg_t*)(TX39_SYSADDR_CONFIG_REG_KSEG1 + reg));
    422 }
    423 
    424 void
    425 tx_conf_write(t, reg, val)
    426 	tx_chipset_tag_t t;
    427 	int reg;
    428 	txreg_t val;
    429 {
    430 	*((volatile txreg_t*)(TX39_SYSADDR_CONFIG_REG_KSEG1 + reg)) = val;
    431 }
    432 #endif /* TX39_PREFER_FUNCTION */
    433 
    434 int
    435 __is_set_print(reg, mask, name)
    436 	u_int32_t reg;
    437 	int mask;
    438 	char *name;
    439 {
    440 	const char onoff[2] = "_x";
    441 	int ret = reg & mask ? 1 : 0;
    442 
    443 	printf("%s[%c] ", name, onoff[ret]);
    444 
    445 	return ret;
    446 }
    447