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tx39.c revision 1.16 
      1 /*	$NetBSD: tx39.c,v 1.16 2000/04/24 13:02:14 uch Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1999, 2000 UCHIYAMA Yasushi
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     26  *
     27  */
     28 
     29 #include "opt_tx39_debug.h"
     30 #include "m38813c.h"
     31 #include "tc5165buf.h"
     32 
     33 #include <sys/param.h>
     34 #include <sys/systm.h>
     35 #include <sys/device.h>
     36 #include <sys/kcore.h>
     37 
     38 #include <machine/locore.h>   /* cpu_id */
     39 #include <machine/bootinfo.h> /* bootinfo */
     40 #include <machine/sysconf.h>  /* platform */
     41 
     42 #include <machine/platid.h>
     43 #include <machine/platid_mask.h>
     44 
     45 #include <machine/bus.h>
     46 #include <machine/intr.h>
     47 
     48 #include <hpcmips/hpcmips/machdep.h> /* cpu_name */
     49 
     50 #include <hpcmips/tx/tx39biureg.h>
     51 #include <hpcmips/tx/tx39reg.h>
     52 #include <hpcmips/tx/tx39var.h>
     53 #ifdef TX391X
     54 #include <hpcmips/tx/tx3912videovar.h>
     55 #endif
     56 
     57 #include <sys/termios.h>
     58 #include <sys/ttydefaults.h>
     59 #include <hpcmips/tx/tx39uartvar.h>
     60 #ifndef CONSPEED
     61 #define CONSPEED TTYDEF_SPEED
     62 #endif
     63 
     64 /* console keyboard */
     65 #if NM38813C > 0
     66 #include <hpcmips/dev/m38813cvar.h>
     67 #endif
     68 #if NTC5165BUF > 0
     69 #include <hpcmips/dev/tc5165bufvar.h>
     70 #endif
     71 
     72 extern unsigned nullclkread __P((void));
     73 extern unsigned (*clkread) __P((void));
     74 
     75 struct tx_chipset_tag tx_chipset;
     76 
     77 #ifdef TX39_DEBUG
     78 u_int32_t tx39debugflag;
     79 #endif
     80 
     81 void	tx_init __P((void));
     82 int	tx39icu_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t));
     83 void	tx39clock_cpuspeed __P((int*, int*));
     84 
     85 /* TX39-specific initialization vector */
     86 void	tx_os_init __P((void));
     87 void	tx_bus_reset __P((void));
     88 void	tx_cons_init __P((void));
     89 void	tx_device_register __P((struct device *, void *));
     90 void    tx_fb_init __P((caddr_t*));
     91 void    tx_mem_init __P((paddr_t));
     92 void	tx_find_dram __P((paddr_t, paddr_t));
     93 void	tx_reboot __P((int howto, char *bootstr));
     94 int	tx_intr __P((u_int32_t mask, u_int32_t pc, u_int32_t statusReg,
     95 		     u_int32_t causeReg));
     96 
     97 extern phys_ram_seg_t mem_clusters[];
     98 extern int mem_cluster_cnt;
     99 
    100 void
    101 tx_init()
    102 {
    103 	tx_chipset_tag_t tc;
    104 	int model, rev;
    105 	int cpuclock;
    106 
    107 	tc = tx_conf_get_tag();
    108 	/*
    109 	 * Platform Specific Function Hooks
    110 	 */
    111 	platform.os_init = tx_os_init;
    112 	platform.bus_reset = tx_bus_reset;
    113 	platform.cons_init = tx_cons_init;
    114 	platform.device_register = tx_device_register;
    115 	platform.fb_init = tx_fb_init;
    116 	platform.mem_init = tx_mem_init;
    117 	platform.reboot = tx_reboot;
    118 	platform.iointr = tx39icu_intr;
    119 
    120 	model = (cpu_id.cpu.cp_majrev << 4)| cpu_id.cpu.cp_minrev;
    121 
    122 	switch (model) {
    123 	default:
    124 		 /* Unknown TOSHIBA TX39-series */
    125 		sprintf(cpu_name, "Unknown TOSHIBA TX39-series %x.%x",
    126 			cpu_id.cpu.cp_majrev, cpu_id.cpu.cp_minrev);
    127 		break;
    128 	case TMPR3912:
    129 		tx39clock_cpuspeed(&cpuclock, &cpuspeed);
    130 
    131 		sprintf(cpu_name, "TOSHIBA TMPR3912 %d.%02d MHz",
    132 			cpuclock / 1000000, (cpuclock % 1000000) / 10000);
    133 		break;
    134 	case TMPR3922:
    135 		tx39clock_cpuspeed(&cpuclock, &cpuspeed);
    136 		rev = tx_conf_read(tc, TX3922_REVISION_REG);
    137 
    138 		sprintf(cpu_name, "TOSHIBA TMPR3922 rev. %x.%x "
    139 			"%d.%02d MHz", (rev >> 4) & 0xf, rev & 0xf,
    140 			cpuclock / 1000000, (cpuclock % 1000000) / 10000);
    141 		break;
    142 	}
    143 }
    144 
    145 void
    146 tx_os_init()
    147 {
    148 	/*
    149 	 * Set up interrupt handling and I/O addresses.
    150 	 */
    151 
    152 	splvec.splbio = MIPS_SPL_2_4;
    153 	splvec.splnet = MIPS_SPL_2_4;
    154 	splvec.spltty = MIPS_SPL_2_4;
    155 	splvec.splimp = MIPS_SPL_2_4;
    156 	splvec.splclock = MIPS_SPL_2_4;
    157 	splvec.splstatclock = MIPS_SPL_2_4;
    158 
    159 	/* no high resolution timer circuit; possibly never called */
    160 	clkread = nullclkread;
    161 }
    162 
    163 void
    164 tx_fb_init(kernend)
    165 	caddr_t *kernend;
    166 {
    167 #ifdef TX391X
    168 	paddr_t fb_end;
    169 
    170 	fb_end = MIPS_KSEG0_TO_PHYS(mem_clusters[0].start +
    171 				    mem_clusters[0].size - 1);
    172 	tx3912video_init(MIPS_KSEG0_TO_PHYS(*kernend), &fb_end);
    173 
    174 	/* Skip V-RAM area */
    175 	*kernend = (caddr_t)MIPS_PHYS_TO_KSEG0(fb_end);
    176 #endif /* TX391X */
    177 #ifdef TX392X
    178 	/*
    179 	 *  Plum V-RAM isn't accessible until pmap_bootstrap,
    180 	 * at this time, frame buffer device is disabled.
    181 	 */
    182 	bootinfo->fb_addr = 0;
    183 #endif /* TX392X */
    184 }
    185 
    186 void
    187 tx_mem_init(kernend)
    188 	paddr_t kernend;
    189 {
    190 	mem_clusters[0].start = 0;
    191 	mem_clusters[0].size = kernend;
    192 	mem_cluster_cnt = 1;
    193 	/* search DRAM bank 0 */
    194 	tx_find_dram(kernend, 0x02000000);
    195 
    196 	/* search DRAM bank 1 */
    197 	tx_find_dram(0x02000000, 0x04000000);
    198 	/*
    199 	 *  Clear currently unused D-RAM area
    200 	 *  (For reboot Windows CE clearly)
    201 	 */
    202 	memset((void *)(KERNBASE + 0x400), 0, KERNTEXTOFF -
    203 	       (KERNBASE + 0x800));
    204 }
    205 
    206 void
    207 tx_find_dram(start, end)
    208 	paddr_t start, end;
    209 {
    210 	caddr_t page, startaddr, endaddr;
    211 
    212 	startaddr = (void*)MIPS_PHYS_TO_KSEG1(start);
    213 	endaddr = (void*)MIPS_PHYS_TO_KSEG1(end);
    214 
    215 #define DRAM_MAGIC0 0xac1dcafe
    216 #define DRAM_MAGIC1 0x19700220
    217 
    218 	page = startaddr;
    219 	if (badaddr(page, 4))
    220 		return;
    221 
    222 	*(volatile int *)(page+0) = DRAM_MAGIC0;
    223 	*(volatile int *)(page+4) = DRAM_MAGIC1;
    224 	wbflush();
    225 
    226 	if (*(volatile int *)(page+0) != DRAM_MAGIC0 ||
    227 	    *(volatile int *)(page+4) != DRAM_MAGIC1)
    228 		return;
    229 
    230 	for (page += NBPG; page < endaddr; page += NBPG) {
    231 		if (badaddr(page, 4))
    232 			return;
    233 
    234 		if (*(volatile int *)(page+0) == DRAM_MAGIC0 &&
    235 		    *(volatile int *)(page+4) == DRAM_MAGIC1) {
    236 			mem_clusters[mem_cluster_cnt].start = start;
    237 			mem_clusters[mem_cluster_cnt].size =
    238 				page - startaddr;
    239 			/* skip kernel area */
    240 			if (mem_cluster_cnt == 1)
    241 				mem_clusters[mem_cluster_cnt].size -= start;
    242 
    243 			mem_cluster_cnt++;
    244 
    245 			return;
    246 		}
    247 	}
    248 
    249 	/* no memory in this bank */
    250 	return;
    251 }
    252 
    253 void
    254 tx_reboot(howto, bootstr)
    255 	int howto;
    256 	char *bootstr;
    257 {
    258 	goto *(u_int32_t *)MIPS_RESET_EXC_VEC;
    259 }
    260 
    261 void
    262 tx_bus_reset()
    263 {
    264 	/* hpcmips port don't use */
    265 }
    266 
    267 void
    268 tx_cons_init()
    269 {
    270 	int slot;
    271 #define CONSPLATIDMATCH(p) \
    272 	platid_match(&platid, &platid_mask_MACH_##p)
    273 
    274 #ifdef SERIALCONSSLOT
    275 	slot = SERIALCONSSLOT;
    276 #else
    277 	slot = TX39_UARTA;
    278 #endif
    279 	if (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) {
    280 		if(txcom_cnattach(slot, CONSPEED,
    281 				  (TTYDEF_CFLAG & ~(CSIZE | PARENB)) |
    282 				  CS8)) {
    283 			panic("tx_cons_init: can't attach serial console.");
    284 		}
    285 	} else {
    286 #if NM38813C > 0
    287 		if(CONSPLATIDMATCH(VICTOR_INTERLINK) &&
    288 		   m38813c_cnattach(TX39_SYSADDR_CARD1)) {
    289 			goto panic;
    290 		}
    291 #endif
    292 #if NTC5165BUF > 0
    293 		if(CONSPLATIDMATCH(COMPAQ_C) &&
    294 		   tc5165buf_cnattach(TX39_SYSADDR_CS3)) {
    295 			goto panic;
    296 		}
    297 
    298 		if(CONSPLATIDMATCH(SHARP_TELIOS) &&
    299 		   tc5165buf_cnattach(TX39_SYSADDR_CS1)) {
    300 			goto panic;
    301 		}
    302 
    303 		if(CONSPLATIDMATCH(SHARP_MOBILON) &&
    304 		   tc5165buf_cnattach(TX39_SYSADDR_MCS0)) {
    305 			goto panic;
    306 		}
    307 #endif
    308 	}
    309 
    310 	return;
    311  panic:
    312 	panic("tx_cons_init: can't init console");
    313 	/* NOTREACHED */
    314 }
    315 
    316 void
    317 tx_device_register(dev, aux)
    318 	struct device *dev;
    319 	void *aux;
    320 {
    321 	/* hpcmips port don't use */
    322 }
    323 
    324 void
    325 tx_conf_register_intr(t, intrt)
    326 	tx_chipset_tag_t t;
    327 	void *intrt;
    328 {
    329 	if (tx_chipset.tc_intrt) {
    330 		panic("duplicate intrt");
    331 	}
    332 
    333 	if (t != &tx_chipset) {
    334 		panic("bogus tx_chipset_tag");
    335 	}
    336 
    337 	tx_chipset.tc_intrt = intrt;
    338 }
    339 
    340 void
    341 tx_conf_register_power(t, powert)
    342 	tx_chipset_tag_t t;
    343 	void *powert;
    344 {
    345 	if (tx_chipset.tc_powert) {
    346 		panic("duplicate powert");
    347 	}
    348 
    349 	if (t != &tx_chipset) {
    350 		panic("bogus tx_chipset_tag");
    351 	}
    352 
    353 	tx_chipset.tc_powert = powert;
    354 }
    355 
    356 void
    357 tx_conf_register_clock(t, clockt)
    358 	tx_chipset_tag_t t;
    359 	void *clockt;
    360 {
    361 	if (tx_chipset.tc_clockt) {
    362 		panic("duplicate clockt");
    363 	}
    364 
    365 	if (t != &tx_chipset) {
    366 		panic("bogus tx_chipset_tag");
    367 	}
    368 
    369 	tx_chipset.tc_clockt = clockt;
    370 }
    371 
    372 void
    373 tx_conf_register_sound(t, soundt)
    374 	tx_chipset_tag_t t;
    375 	void *soundt;
    376 {
    377 	if (t != &tx_chipset) {
    378 		panic("bogus tx_chipset_tag");
    379 	}
    380 
    381 	tx_chipset.tc_soundt = soundt;
    382 }
    383 
    384 void
    385 tx_conf_register_ioman(t, iomant)
    386 	tx_chipset_tag_t t;
    387 	void *iomant;
    388 {
    389 	if (tx_chipset.tc_iomant) {
    390 		panic("duplicate iomant");
    391 	}
    392 
    393 	if (t != &tx_chipset) {
    394 		panic("bogus tx_chipset_tag");
    395 	}
    396 
    397 	tx_chipset.tc_iomant = iomant;
    398 }
    399 
    400 #ifdef TX39_PREFER_FUNCTION
    401 tx_chipset_tag_t
    402 tx_conf_get_tag()
    403 {
    404 	return (tx_chipset_tag_t)&tx_chipset;
    405 }
    406 
    407 txreg_t
    408 tx_conf_read(t, reg)
    409 	tx_chipset_tag_t t;
    410 	int reg;
    411 {
    412 	return *((volatile txreg_t*)(TX39_SYSADDR_CONFIG_REG_KSEG1 + reg));
    413 }
    414 
    415 void
    416 tx_conf_write(t, reg, val)
    417 	tx_chipset_tag_t t;
    418 	int reg;
    419 	txreg_t val;
    420 {
    421 	*((volatile txreg_t*)(TX39_SYSADDR_CONFIG_REG_KSEG1 + reg)) = val;
    422 }
    423 #endif /* TX39_PREFER_FUNCTION */
    424 
    425 int
    426 __is_set_print(reg, mask, name)
    427 	u_int32_t reg;
    428 	int mask;
    429 	char *name;
    430 {
    431 	const char onoff[2] = "_x";
    432 	int ret = reg & mask ? 1 : 0;
    433 
    434 	printf("%s[%c] ", name, onoff[ret]);
    435 
    436 	return ret;
    437 }
    438