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tx39.c revision 1.2 
      1 /*	$NetBSD: tx39.c,v 1.2 1999/11/28 04:29:38 takemura Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1999, by UCHIYAMA Yasushi
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. The name of the developer may NOT be used to endorse or promote products
     13  *    derived from this software without specific prior written permission.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     25  * SUCH DAMAGE.
     26  *
     27  */
     28 
     29 #include "opt_tx39_debug.h"
     30 #include "fb.h"
     31 #include "cckbd.h"
     32 
     33 #include <sys/param.h>
     34 #include <sys/systm.h>
     35 #include <sys/device.h>
     36 
     37 #include <machine/locore.h>   /* cpu_id */
     38 #include <machine/bootinfo.h> /* bootinfo */
     39 #include <machine/sysconf.h>  /* platform */
     40 
     41 #include <machine/bus.h>
     42 #include <machine/intr.h>
     43 
     44 #include <hpcmips/hpcmips/machdep.h> /* cpu_model */
     45 #include <hpcmips/dev/biconsvar.h>
     46 #include <hpcmips/dev/bicons.h>
     47 
     48 #include <hpcmips/tx/tx39biureg.h>
     49 #include <hpcmips/tx/tx39reg.h>
     50 #include <hpcmips/tx/tx39var.h>
     51 #ifdef TX391X
     52 #include <hpcmips/tx/tx3912videovar.h>
     53 #endif
     54 
     55 #include <sys/termios.h>
     56 #include <sys/ttydefaults.h>
     57 #include <hpcmips/tx/tx39uartvar.h>
     58 #ifndef CONSPEED
     59 #define CONSPEED TTYDEF_SPEED
     60 #endif
     61 
     62 #if NFB > 0
     63 #include <dev/rcons/raster.h>
     64 #include <dev/wscons/wsdisplayvar.h>
     65 #include <arch/hpcmips/dev/fbvar.h>
     66 #endif
     67 
     68 #if NCCKBD > 0
     69 #include <hpcmips/dev/cckbdvar.h>
     70 #endif
     71 
     72 extern unsigned nullclkread __P((void));
     73 extern unsigned (*clkread) __P((void));
     74 
     75 struct tx_chipset_tag tx_chipset;
     76 
     77 #ifdef TX39_DEBUG
     78 u_int32_t tx39debugflag;
     79 #endif
     80 
     81 void	tx_init __P((void));
     82 int	tx39icu_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t));
     83 int	tx39_find_dram __P((u_int32_t, u_int32_t));
     84 
     85 /* TX39-specific initialization vector */
     86 void	tx_os_init __P((void));
     87 void	tx_bus_reset __P((void));
     88 void	tx_cons_init __P((void));
     89 void	tx_device_register __P((struct device *, void *));
     90 void    tx_fb_init __P((caddr_t*));
     91 int     tx_mem_init __P((caddr_t));
     92 void	tx_reboot __P((int howto, char *bootstr));
     93 int	tx_intr __P((u_int32_t mask, u_int32_t pc, u_int32_t statusReg, u_int32_t causeReg));
     94 
     95 void
     96 tx_init()
     97 {
     98 	tx_chipset_tag_t tc;
     99 	int model, rev;
    100 
    101 	tc = tx_conf_get_tag();
    102 	/*
    103 	 * Platform Specific Function Hooks
    104 	 */
    105 	platform.os_init = tx_os_init;
    106 	platform.bus_reset = tx_bus_reset;
    107 	platform.cons_init = tx_cons_init;
    108 	platform.device_register = tx_device_register;
    109 	platform.fb_init = tx_fb_init;
    110 	platform.mem_init = tx_mem_init;
    111 	platform.reboot = tx_reboot;
    112 
    113 	model = (cpu_id.cpu.cp_majrev << 4)| cpu_id.cpu.cp_minrev;
    114 
    115 	switch (model) {
    116 	default:
    117 		 /* Unknown TOSHIBA TX39-series */
    118 		sprintf(cpu_model, "Unknown TOSHIBA TX39-series %x.%x",
    119 			cpu_id.cpu.cp_majrev, cpu_id.cpu.cp_minrev);
    120 		break;
    121 	case TMPR3912:
    122 		sprintf(cpu_model, "TOSHIBA TMPR3912");
    123 		cpuspeed = 50; /* XXX Should calibrate XXX */
    124 		break;
    125 	case TMPR3922:
    126 		rev = tx_conf_read(tc, TX3922_REVISION_REG);
    127 		sprintf(cpu_model, "TOSHIBA TMPR3922 rev. %x.%x",
    128 			(rev >> 4) & 0xf, rev & 0xf);
    129 		cpuspeed = 100; /* XXX Should calibrate XXX */
    130 		break;
    131 	}
    132 }
    133 
    134 void
    135 tx_os_init()
    136 {
    137 	/*
    138 	 * Set up interrupt handling and I/O addresses.
    139 	 */
    140 	mips_hardware_intr = tx39icu_intr;
    141 
    142 	splvec.splbio = MIPS_SPL_2_4;
    143 	splvec.splnet = MIPS_SPL_2_4;
    144 	splvec.spltty = MIPS_SPL_2_4;
    145 	splvec.splimp = MIPS_SPL_2_4;
    146 	splvec.splclock = MIPS_SPL_2_4;
    147 	splvec.splstatclock = MIPS_SPL_2_4;
    148 
    149 	/* no high resolution timer circuit; possibly never called */
    150 	clkread = nullclkread;
    151 }
    152 
    153 void
    154 tx_fb_init(kernend)
    155 	caddr_t *kernend;
    156 {
    157 #ifdef TX391X
    158 	tx_chipset_tag_t tc;
    159 	u_int32_t fb_start, fb_addr, fb_size, fb_line_bytes;
    160 
    161 	/* Initialize to access TX39 configuration register */
    162 	tc = tx_conf_get_tag();
    163 
    164 	fb_start = MIPS_KSEG0_TO_PHYS(*kernend);
    165 	tx3912video_init(tc, fb_start, bootinfo->fb_width,
    166 			bootinfo->fb_height, &fb_addr, &fb_size,
    167 			&fb_line_bytes);
    168 
    169 	/* Set bootinfo for bicons */
    170 	bootinfo->fb_line_bytes = fb_line_bytes;
    171 	bootinfo->fb_addr = (unsigned char*)MIPS_PHYS_TO_KSEG1(fb_addr);
    172 
    173 	/* Skip V-RAM area */
    174 	*kernend += fb_size;
    175 #endif /* TX391X */
    176 #ifdef TX392X
    177 	/*
    178 	 *  Plum V-RAM isn't accessible until pmap_bootstrap,
    179 	 * at this time, bicons is disabled.
    180 	 */
    181 	bootinfo->fb_addr = 0;
    182 #endif /* TX392X */
    183 }
    184 
    185 int
    186 tx_mem_init(kernend)
    187 	caddr_t kernend; /* kseg0 */
    188 {
    189 	u_int32_t startaddr, endaddr;
    190 	int npage, xpage, kpage;
    191 
    192 	startaddr = MIPS_PHYS_TO_KSEG1(
    193 		(btoc((u_int32_t)kernend - MIPS_KSEG0_START)) << PGSHIFT);
    194 	endaddr = MIPS_PHYS_TO_KSEG1(TX39_SYSADDR_DRAMBANK0CS1 +
    195 				     TX39_SYSADDR_DRAMBANK_LEN);
    196 	kpage = btoc(MIPS_KSEG1_TO_PHYS(startaddr));
    197 	/* D-RAM bank0 */
    198 	npage = tx39_find_dram(startaddr, endaddr);
    199 
    200 	printf("DRAM bank0: %d pages (%dMByte) reserved %d pages\n", npage + 1,
    201 	       ((npage  + 1) * NBPG) / 0x100000, kpage + 1);
    202 	npage -= kpage; /* exclude kernel area */
    203 	/* Clear DRAM area */
    204 	memset((void*)startaddr, 0, npage * NBPG);
    205 
    206 	/* D-RAM bank1 XXX find only. not usable yet */
    207 	startaddr = MIPS_PHYS_TO_KSEG1(TX39_SYSADDR_DRAMBANK1CS1);
    208 	endaddr = MIPS_PHYS_TO_KSEG1(TX39_SYSADDR_DRAMBANK1CS1 +
    209 				     TX39_SYSADDR_DRAMBANK_LEN);
    210 	xpage = tx39_find_dram(startaddr, endaddr);
    211 	printf("DRAM bank1: %d pages (%dMByte) ...but not usable yet\n",
    212 	       xpage + 1, ((xpage + 1) * NBPG) / 0x100000);
    213 
    214 	/* Clear currently unused D-RAM area (For reboot Windows CE clearly)*/
    215 	memset((void*)startaddr, 0, npage * NBPG);
    216 	memset((void*)(KERNBASE + 0x400), 0, KERNTEXTOFF - KERNBASE - 0x800);
    217 
    218 	return npage; /* Return bank0's memory only */
    219 }
    220 
    221 void
    222 tx_reboot(howto, bootstr)
    223 	int howto;
    224 	char *bootstr;
    225 {
    226 	goto *(u_int32_t *)MIPS_RESET_EXC_VEC;
    227 }
    228 
    229 int
    230 tx39_find_dram(startaddr, endaddr)
    231 	u_int32_t startaddr; /* kseg1 */
    232 	u_int32_t endaddr;    /* kseg1 */
    233 {
    234 #define DRAM_MAGIC0 0xac1dcafe
    235 #define DRAM_MAGIC1 0x19700220
    236 	u_int32_t page;
    237 	int npage;
    238 
    239 	page = startaddr;
    240 	((volatile int *)page)[0] = DRAM_MAGIC0;
    241 	((volatile int *)page)[4] = DRAM_MAGIC1;
    242 	page += NBPG;
    243 	for (npage = 0; page < endaddr; page += NBPG, npage++) {
    244 		if ((((volatile int *)page)[0] == DRAM_MAGIC0 &&
    245 		     ((volatile int *)page)[4] == DRAM_MAGIC1)) {
    246 			return npage;
    247 		}
    248 	}
    249 	/* no memory in this bank */
    250 	return 0;
    251 }
    252 
    253 void
    254 tx_bus_reset()
    255 {
    256 	/* hpcmips port don't use */
    257 }
    258 
    259 void
    260 tx_cons_init()
    261 {
    262 	int slot;
    263 
    264 #ifdef SERIALCONSSLOT
    265 	slot = SERIALCONSSLOT;
    266 #else
    267 	slot = TX39_UARTA;
    268 #endif
    269 	if (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) {
    270 		if(txcom_cnattach(slot, CONSPEED,
    271 				  (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8)) {
    272 			panic("tx_cons_init: can't attach serial console.");
    273 		}
    274 	}
    275 #if NFB > 0
    276 	if(fb_cnattach(0, 0, 0, 0)) {
    277 		panic("tx_cons_init: can't init fb console");
    278 	}
    279 #endif
    280 #if NCCKBD > 0
    281 	if(cckbd_cnattach(0, 0)) {
    282 		panic("tx_cons_init: can't init cckbd as console");
    283 	}
    284 #endif
    285 
    286 }
    287 
    288 void
    289 tx_device_register(dev, aux)
    290 	struct device *dev;
    291 	void *aux;
    292 {
    293 	/* hpcmips port don't use */
    294 }
    295 
    296 void
    297 tx_conf_register_intr(t, intrt)
    298 	tx_chipset_tag_t t;
    299 	void *intrt;
    300 {
    301 	if (tx_chipset.tc_intrt) {
    302 		panic("duplicate intrt");
    303 	}
    304 
    305 	if (t != &tx_chipset) {
    306 		panic("bogus tx_chipset_tag");
    307 	}
    308 
    309 	tx_chipset.tc_intrt = intrt;
    310 }
    311 
    312 #ifdef TX39_PREFER_FUNCTION
    313 tx_chipset_tag_t
    314 tx_conf_get_tag()
    315 {
    316 	return (tx_chipset_tag_t)&tx_chipset;
    317 }
    318 
    319 txreg_t
    320 tx_conf_read(t, reg)
    321 	tx_chipset_tag_t t;
    322 	int reg;
    323 {
    324 	return *((txreg_t*)(TX39_SYSADDR_CONFIG_REG_KSEG1 + reg));
    325 }
    326 
    327 void
    328 tx_conf_write(t, reg, val)
    329 	tx_chipset_tag_t t;
    330 	int reg;
    331 	txreg_t val;
    332 {
    333 	*((txreg_t*)(TX39_SYSADDR_CONFIG_REG_KSEG1 + reg)) = val;
    334 }
    335 #endif /* TX39_PREFER_FUNCTION */
    336 
    337 int
    338 __is_set_print(reg, mask, name)
    339 	u_int32_t reg;
    340 	int mask;
    341 	char *name;
    342 {
    343 	if (reg & mask) {
    344 		printf("%s ", name);
    345 		return 1;
    346 	}
    347 	return 0;
    348 }
    349