tx39.c revision 1.28 1 /* $NetBSD: tx39.c,v 1.28 2002/01/02 13:08:05 uch Exp $ */
2
3 /*-
4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by UCHIYAMA Yasushi.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #include "opt_vr41xx.h"
40 #include "opt_tx39xx.h"
41 #include "opt_tx39_debug.h"
42 #include "m38813c.h"
43 #include "tc5165buf.h"
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47
48 #include <mips/cache.h>
49
50 #include <machine/locore.h> /* cpu_id */
51 #include <machine/bootinfo.h> /* bootinfo */
52 #include <machine/sysconf.h> /* platform */
53
54 #include <machine/platid.h>
55 #include <machine/platid_mask.h>
56
57 #include <machine/bus.h>
58
59 #include <hpcmips/hpcmips/machdep.h> /* cpu_name, mem_cluster */
60
61 #include <hpcmips/tx/tx39biureg.h>
62 #include <hpcmips/tx/tx39reg.h>
63 #include <hpcmips/tx/tx39var.h>
64 #ifdef TX391X
65 #include <hpcmips/tx/tx3912videovar.h>
66 #endif
67
68 #include <sys/termios.h>
69 #include <sys/ttydefaults.h>
70 #include <hpcmips/tx/tx39uartvar.h>
71 #ifndef CONSPEED
72 #define CONSPEED TTYDEF_SPEED
73 #endif
74
75 /* console keyboard */
76 #if NM38813C > 0
77 #include <hpcmips/dev/m38813cvar.h>
78 #endif
79 #if NTC5165BUF > 0
80 #include <hpcmips/dev/tc5165bufvar.h>
81 #endif
82
83 struct tx_chipset_tag tx_chipset;
84
85 #ifdef TX39_DEBUG
86 u_int32_t tx39debugflag;
87 #endif
88
89 void tx_init(void);
90 #if defined(VR41XX) && defined(TX39XX)
91 #define TX_INTR tx_intr
92 #else
93 #define TX_INTR cpu_intr /* locore_mips3 directly call this */
94 #endif
95
96 extern void TX_INTR(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
97
98 void tx39clock_cpuspeed(int *, int *);
99
100 /* TX39-specific initialization vector */
101 void tx_cons_init(void);
102 void tx_fb_init(caddr_t *);
103 void tx_mem_init(paddr_t);
104 void tx_find_dram(paddr_t, paddr_t);
105 void tx_reboot(int, char *);
106
107 void
108 tx_init()
109 {
110 tx_chipset_tag_t tc;
111 int model, rev;
112 int cpuclock;
113
114 tc = tx_conf_get_tag();
115 /*
116 * Platform Specific Function Hooks
117 */
118 platform.cpu_intr = TX_INTR;
119 platform.cpu_idle = NULL; /* not implemented yet */
120 platform.cons_init = tx_cons_init;
121 platform.fb_init = tx_fb_init;
122 platform.mem_init = tx_mem_init;
123 platform.reboot = tx_reboot;
124
125
126 model = MIPS_PRID_REV(cpu_id);
127
128 switch (model) {
129 default:
130 /* Unknown TOSHIBA TX39-series */
131 sprintf(cpu_name, "Unknown TOSHIBA TX39-series %x", model);
132 break;
133 case TMPR3912:
134 tx39clock_cpuspeed(&cpuclock, &cpuspeed);
135
136 sprintf(cpu_name, "TOSHIBA TMPR3912 %d.%02d MHz",
137 cpuclock / 1000000, (cpuclock % 1000000) / 10000);
138 tc->tc_chipset = __TX391X;
139 break;
140 case TMPR3922:
141 tx39clock_cpuspeed(&cpuclock, &cpuspeed);
142 rev = tx_conf_read(tc, TX3922_REVISION_REG);
143
144 sprintf(cpu_name, "TOSHIBA TMPR3922 rev. %x.%x "
145 "%d.%02d MHz", (rev >> 4) & 0xf, rev & 0xf,
146 cpuclock / 1000000, (cpuclock % 1000000) / 10000);
147 tc->tc_chipset = __TX392X;
148 break;
149 }
150 }
151
152 void
153 tx_fb_init(caddr_t *kernend)
154 {
155 #ifdef TX391X
156 paddr_t fb_end;
157
158 fb_end = MIPS_KSEG0_TO_PHYS(mem_clusters[0].start +
159 mem_clusters[0].size - 1);
160 tx3912video_init(MIPS_KSEG0_TO_PHYS(*kernend), &fb_end);
161
162 /* Skip V-RAM area */
163 *kernend = (caddr_t)MIPS_PHYS_TO_KSEG0(fb_end);
164 #endif /* TX391X */
165 #ifdef TX392X
166 /*
167 * Plum V-RAM isn't accessible until pmap_bootstrap,
168 * at this time, frame buffer device is disabled.
169 */
170 bootinfo->fb_addr = 0;
171 #endif /* TX392X */
172 }
173
174 void
175 tx_mem_init(paddr_t kernend)
176 {
177
178 mem_clusters[0].start = 0;
179 mem_clusters[0].size = kernend;
180 mem_cluster_cnt = 1;
181 /* search DRAM bank 0 */
182 tx_find_dram(kernend, 0x02000000);
183
184 /* search DRAM bank 1 */
185 tx_find_dram(0x02000000, 0x04000000);
186 }
187
188 void
189 tx_find_dram(paddr_t start, paddr_t end)
190 {
191 caddr_t page, startaddr, endaddr;
192 u_int32_t magic0, magic1;
193 #define MAGIC0 (*(__volatile u_int32_t *)(page + 0))
194 #define MAGIC1 (*(__volatile u_int32_t *)(page + 4))
195
196 startaddr = (void *)MIPS_PHYS_TO_KSEG1(start);
197 endaddr = (void *)MIPS_PHYS_TO_KSEG1(end);
198
199 page = startaddr;
200 if (badaddr(page, 4))
201 return;
202
203 do {
204 magic0 = random();
205 magic1 = random();
206 } while (MAGIC0 == magic0 || MAGIC0 == magic1);
207
208 MAGIC0 = magic0;
209 MAGIC1 = magic1;
210 wbflush();
211
212 if (MAGIC0 != magic0 || MAGIC1 != magic1)
213 return;
214
215 for (page += NBPG; page < endaddr; page += NBPG) {
216 if (badaddr(page, 4))
217 return;
218 if (MAGIC0 == magic0 &&
219 MAGIC1 == magic1) {
220 goto memend_found;
221 }
222 }
223
224 /* check for 32MByte memory */
225 page -= NBPG;
226 MAGIC0 = magic0;
227 MAGIC1 = magic1;
228 wbflush();
229 if (MAGIC0 != magic0 || MAGIC1 != magic1)
230 return; /* no memory in this bank */
231
232 memend_found:
233 mem_clusters[mem_cluster_cnt].start = start;
234 mem_clusters[mem_cluster_cnt].size = page - startaddr;
235 mem_cluster_cnt++;
236 #undef MAGIC0
237 #undef MAGIC1
238 }
239
240 void
241 tx_reboot(int howto, char *bootstr)
242 {
243
244 goto *(u_int32_t *)MIPS_RESET_EXC_VEC;
245 }
246
247 void
248 tx_cons_init()
249 {
250 int slot;
251 #define CONSPLATIDMATCH(p) \
252 platid_match(&platid, &platid_mask_MACH_##p)
253
254 #ifdef SERIALCONSSLOT
255 slot = SERIALCONSSLOT;
256 #else
257 slot = TX39_UARTA;
258 #endif
259 if (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) {
260 if(txcom_cnattach(slot, CONSPEED,
261 (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8)) {
262 panic("tx_cons_init: can't attach serial console.");
263 }
264 } else {
265 #if NM38813C > 0
266 if(CONSPLATIDMATCH(VICTOR_INTERLINK) &&
267 m38813c_cnattach(TX39_SYSADDR_CARD1)) {
268 goto panic;
269 }
270 #endif
271 #if NTC5165BUF > 0
272 if(CONSPLATIDMATCH(COMPAQ_C) &&
273 tc5165buf_cnattach(TX39_SYSADDR_CS3)) {
274 goto panic;
275 }
276
277 if(CONSPLATIDMATCH(SHARP_TELIOS) &&
278 tc5165buf_cnattach(TX39_SYSADDR_CS1)) {
279 goto panic;
280 }
281
282 if(CONSPLATIDMATCH(SHARP_MOBILON) &&
283 tc5165buf_cnattach(TX39_SYSADDR_MCS0)) {
284 goto panic;
285 }
286 #endif
287 }
288
289 return;
290 panic:
291 panic("tx_cons_init: can't init console");
292 /* NOTREACHED */
293 }
294
295 void
296 tx_conf_register_intr(tx_chipset_tag_t t, void *intrt)
297 {
298
299 KASSERT(t == &tx_chipset);
300 tx_chipset.tc_intrt = intrt;
301 }
302
303 void
304 tx_conf_register_power(tx_chipset_tag_t t, void *powert)
305 {
306
307 KASSERT(t == &tx_chipset);
308 tx_chipset.tc_powert = powert;
309 }
310
311 void
312 tx_conf_register_clock(tx_chipset_tag_t t, void *clockt)
313 {
314
315 KASSERT(t == &tx_chipset);
316 tx_chipset.tc_clockt = clockt;
317 }
318
319 void
320 tx_conf_register_sound(tx_chipset_tag_t t, void *soundt)
321 {
322
323 KASSERT(t == &tx_chipset);
324 tx_chipset.tc_soundt = soundt;
325 }
326
327 void
328 tx_conf_register_video(tx_chipset_tag_t t, void *videot)
329 {
330
331 KASSERT(t == &tx_chipset);
332 tx_chipset.tc_videot = videot;
333 }
334
335 int
336 __is_set_print(u_int32_t reg, int mask, char *name)
337 {
338 const char onoff[2] = "_x";
339 int ret = reg & mask ? 1 : 0;
340
341 printf("%s[%c] ", name, onoff[ret]);
342
343 return (ret);
344 }
345