tx39.c revision 1.8
1 /* $NetBSD: tx39.c,v 1.8 1999/12/22 15:35:35 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #include "opt_tx39_debug.h" 30 #include "m38813c.h" 31 #include "p7416buf.h" 32 #include "tc5165buf.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 38 #include <machine/locore.h> /* cpu_id */ 39 #include <machine/bootinfo.h> /* bootinfo */ 40 #include <machine/sysconf.h> /* platform */ 41 42 #include <machine/platid.h> 43 #include <machine/platid_mask.h> 44 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 48 #include <hpcmips/hpcmips/machdep.h> /* cpu_model */ 49 50 #include <hpcmips/tx/tx39biureg.h> 51 #include <hpcmips/tx/tx39reg.h> 52 #include <hpcmips/tx/tx39var.h> 53 #ifdef TX391X 54 #include <hpcmips/tx/tx3912videovar.h> 55 #endif 56 57 #include <sys/termios.h> 58 #include <sys/ttydefaults.h> 59 #include <hpcmips/tx/tx39uartvar.h> 60 #ifndef CONSPEED 61 #define CONSPEED TTYDEF_SPEED 62 #endif 63 64 /* console keyboard */ 65 #if NP7416BUF > 0 66 #include <hpcmips/dev/p7416bufvar.h> 67 #endif 68 #if NM38813C > 0 69 #include <hpcmips/dev/m38813cvar.h> 70 #endif 71 #if NTC5165BUF > 0 72 #include <hpcmips/dev/tc5165bufvar.h> 73 #endif 74 75 extern unsigned nullclkread __P((void)); 76 extern unsigned (*clkread) __P((void)); 77 78 struct tx_chipset_tag tx_chipset; 79 80 #ifdef TX39_DEBUG 81 u_int32_t tx39debugflag; 82 #endif 83 84 void tx_init __P((void)); 85 int tx39icu_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t)); 86 int tx39_find_dram __P((u_int32_t, u_int32_t)); 87 void tx39clock_cpuspeed __P((int*, int*)); 88 89 /* TX39-specific initialization vector */ 90 void tx_os_init __P((void)); 91 void tx_bus_reset __P((void)); 92 void tx_cons_init __P((void)); 93 void tx_device_register __P((struct device *, void *)); 94 void tx_fb_init __P((caddr_t*)); 95 int tx_mem_init __P((caddr_t)); 96 void tx_reboot __P((int howto, char *bootstr)); 97 int tx_intr __P((u_int32_t mask, u_int32_t pc, u_int32_t statusReg, 98 u_int32_t causeReg)); 99 100 void 101 tx_init() 102 { 103 tx_chipset_tag_t tc; 104 int model, rev; 105 int cpuclock; 106 107 tc = tx_conf_get_tag(); 108 /* 109 * Platform Specific Function Hooks 110 */ 111 platform.os_init = tx_os_init; 112 platform.bus_reset = tx_bus_reset; 113 platform.cons_init = tx_cons_init; 114 platform.device_register = tx_device_register; 115 platform.fb_init = tx_fb_init; 116 platform.mem_init = tx_mem_init; 117 platform.reboot = tx_reboot; 118 119 model = (cpu_id.cpu.cp_majrev << 4)| cpu_id.cpu.cp_minrev; 120 121 switch (model) { 122 default: 123 /* Unknown TOSHIBA TX39-series */ 124 sprintf(cpu_model, "Unknown TOSHIBA TX39-series %x.%x", 125 cpu_id.cpu.cp_majrev, cpu_id.cpu.cp_minrev); 126 break; 127 case TMPR3912: 128 tx39clock_cpuspeed(&cpuclock, &cpuspeed); 129 130 sprintf(cpu_model, "TOSHIBA TMPR3912 %d.%02d MHz", 131 cpuclock / 1000000, (cpuclock % 1000000) / 10000); 132 break; 133 case TMPR3922: 134 tx39clock_cpuspeed(&cpuclock, &cpuspeed); 135 rev = tx_conf_read(tc, TX3922_REVISION_REG); 136 137 sprintf(cpu_model, "TOSHIBA TMPR3922 rev. %x.%x " 138 "%d.%02d MHz", (rev >> 4) & 0xf, rev & 0xf, 139 cpuclock / 1000000, (cpuclock % 1000000) / 10000); 140 break; 141 } 142 } 143 144 void 145 tx_os_init() 146 { 147 /* 148 * Set up interrupt handling and I/O addresses. 149 */ 150 mips_hardware_intr = tx39icu_intr; 151 152 splvec.splbio = MIPS_SPL_2_4; 153 splvec.splnet = MIPS_SPL_2_4; 154 splvec.spltty = MIPS_SPL_2_4; 155 splvec.splimp = MIPS_SPL_2_4; 156 splvec.splclock = MIPS_SPL_2_4; 157 splvec.splstatclock = MIPS_SPL_2_4; 158 159 /* no high resolution timer circuit; possibly never called */ 160 clkread = nullclkread; 161 } 162 163 void 164 tx_fb_init(kernend) 165 caddr_t *kernend; 166 { 167 #ifdef TX391X 168 tx_chipset_tag_t tc; 169 u_int32_t fb_start, fb_addr, fb_size, fb_line_bytes; 170 171 /* Initialize to access TX39 configuration register */ 172 tc = tx_conf_get_tag(); 173 174 fb_start = MIPS_KSEG0_TO_PHYS(*kernend); 175 tx3912video_init(tc, fb_start, bootinfo->fb_width, 176 bootinfo->fb_height, &fb_addr, &fb_size, 177 &fb_line_bytes); 178 179 /* Setup bootinfo */ 180 bootinfo->fb_line_bytes = fb_line_bytes; 181 bootinfo->fb_addr = (unsigned char*)MIPS_PHYS_TO_KSEG1(fb_addr); 182 183 /* Skip V-RAM area */ 184 *kernend += fb_size; 185 #endif /* TX391X */ 186 #ifdef TX392X 187 /* 188 * Plum V-RAM isn't accessible until pmap_bootstrap, 189 * at this time, frame buffer device is disabled. 190 */ 191 bootinfo->fb_addr = 0; 192 #endif /* TX392X */ 193 } 194 195 int 196 tx_mem_init(kernend) 197 caddr_t kernend; /* kseg0 */ 198 { 199 u_int32_t startaddr, endaddr; 200 int npage, xpage, kpage; 201 202 startaddr = MIPS_PHYS_TO_KSEG1( 203 (btoc((u_int32_t)kernend - MIPS_KSEG0_START)) << PGSHIFT); 204 endaddr = MIPS_PHYS_TO_KSEG1(TX39_SYSADDR_DRAMBANK0CS1 + 205 TX39_SYSADDR_DRAMBANK_LEN); 206 kpage = btoc(MIPS_KSEG1_TO_PHYS(startaddr)); 207 208 /* D-RAM bank0 */ 209 npage = tx39_find_dram(startaddr, endaddr); 210 211 printf("DRAM bank0: %d pages (%dMByte) reserved %d pages\n", 212 npage + 1, ((npage + 1) * NBPG) / 0x100000, kpage + 1); 213 npage -= kpage; /* exclude kernel area */ 214 215 /* Clear DRAM area */ 216 memset((void*)startaddr, 0, npage * NBPG); 217 218 /* D-RAM bank1 XXX find only. not usable yet */ 219 startaddr = MIPS_PHYS_TO_KSEG1(TX39_SYSADDR_DRAMBANK1CS1); 220 endaddr = MIPS_PHYS_TO_KSEG1(TX39_SYSADDR_DRAMBANK1CS1 + 221 TX39_SYSADDR_DRAMBANK_LEN); 222 xpage = tx39_find_dram(startaddr, endaddr); 223 printf("DRAM bank1: %d pages (%dMByte) ...but not usable yet\n", 224 xpage + 1, ((xpage + 1) * NBPG) / 0x100000); 225 226 /* 227 * Clear currently unused D-RAM area 228 * (For reboot Windows CE clearly) 229 */ 230 memset((void*)startaddr, 0, npage * NBPG); 231 memset((void*)(KERNBASE + 0x400), 0, 232 KERNTEXTOFF - KERNBASE - 0x800); 233 234 return npage; /* Return bank0's memory only */ 235 } 236 237 void 238 tx_reboot(howto, bootstr) 239 int howto; 240 char *bootstr; 241 { 242 goto *(u_int32_t *)MIPS_RESET_EXC_VEC; 243 } 244 245 int 246 tx39_find_dram(startaddr, endaddr) 247 u_int32_t startaddr; /* kseg1 */ 248 u_int32_t endaddr; /* kseg1 */ 249 { 250 #define DRAM_MAGIC0 0xac1dcafe 251 #define DRAM_MAGIC1 0x19700220 252 u_int32_t page; 253 int npage; 254 255 page = startaddr; 256 ((volatile int *)page)[0] = DRAM_MAGIC0; 257 ((volatile int *)page)[4] = DRAM_MAGIC1; 258 page += NBPG; 259 for (npage = 0; page < endaddr; page += NBPG, npage++) { 260 if ((((volatile int *)page)[0] == DRAM_MAGIC0 && 261 ((volatile int *)page)[4] == DRAM_MAGIC1)) { 262 return npage; 263 } 264 } 265 /* no memory in this bank */ 266 return 0; 267 } 268 269 void 270 tx_bus_reset() 271 { 272 /* hpcmips port don't use */ 273 } 274 275 void 276 tx_cons_init() 277 { 278 int slot; 279 #define CONSPLATIDMATCH(p) \ 280 platid_match(&platid, &platid_mask_MACH_##p) 281 282 #ifdef SERIALCONSSLOT 283 slot = SERIALCONSSLOT; 284 #else 285 slot = TX39_UARTA; 286 #endif 287 if (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) { 288 if(txcom_cnattach(slot, CONSPEED, 289 (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | 290 CS8)) { 291 panic("tx_cons_init: can't attach serial console."); 292 } 293 } else { 294 #if NP7416BUF > 0 295 if(CONSPLATIDMATCH(COMPAQ_C) && 296 p7416buf_cnattach(TX39_SYSADDR_CS3)) { 297 panic("tx_cons_init: can't init console"); 298 } 299 #endif 300 #if NM38813C > 0 301 if(CONSPLATIDMATCH(VICTOR_INTERLINK) && 302 m38813c_cnattach(TX39_SYSADDR_CARD1)) { 303 panic("tx_cons_init: can't init console"); 304 } 305 #endif 306 #if NTC5165BUF > 0 307 if(CONSPLATIDMATCH(SHARP_TELIOS) && 308 tc5165buf_cnattach(TX39_SYSADDR_CS1)) { 309 panic("tx_cons_init: can't init console"); 310 } 311 #endif 312 } 313 314 } 315 316 void 317 tx_device_register(dev, aux) 318 struct device *dev; 319 void *aux; 320 { 321 /* hpcmips port don't use */ 322 } 323 324 void 325 tx_conf_register_intr(t, intrt) 326 tx_chipset_tag_t t; 327 void *intrt; 328 { 329 if (tx_chipset.tc_intrt) { 330 panic("duplicate intrt"); 331 } 332 333 if (t != &tx_chipset) { 334 panic("bogus tx_chipset_tag"); 335 } 336 337 tx_chipset.tc_intrt = intrt; 338 } 339 340 #ifdef TX39_PREFER_FUNCTION 341 tx_chipset_tag_t 342 tx_conf_get_tag() 343 { 344 return (tx_chipset_tag_t)&tx_chipset; 345 } 346 347 txreg_t 348 tx_conf_read(t, reg) 349 tx_chipset_tag_t t; 350 int reg; 351 { 352 return *((volatile txreg_t*)(TX39_SYSADDR_CONFIG_REG_KSEG1 + reg)); 353 } 354 355 void 356 tx_conf_write(t, reg, val) 357 tx_chipset_tag_t t; 358 int reg; 359 txreg_t val; 360 { 361 *((volatile txreg_t*)(TX39_SYSADDR_CONFIG_REG_KSEG1 + reg)) = val; 362 } 363 #endif /* TX39_PREFER_FUNCTION */ 364 365 int 366 __is_set_print(reg, mask, name) 367 u_int32_t reg; 368 int mask; 369 char *name; 370 { 371 if (reg & mask) { 372 printf("%s ", name); 373 return 1; 374 } 375 return 0; 376 } 377
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