tx3912video.c revision 1.1
1 /* $NetBSD: tx3912video.c,v 1.1 1999/11/20 19:56:31 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include "opt_tx39_debug.h" 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/device.h> 33 #include <sys/extent.h> 34 35 #include <machine/bus.h> 36 37 #include <hpcmips/tx/tx39var.h> 38 #include <hpcmips/tx/tx3912videovar.h> 39 #include <hpcmips/tx/tx3912videoreg.h> 40 41 void tx3912video_framebuffer_init __P((tx_chipset_tag_t, u_int32_t, u_int32_t)); 42 int tx3912video_framebuffer_alloc __P((tx_chipset_tag_t, u_int32_t, int, int, int, u_int32_t*, u_int32_t*)); 43 void tx3912video_reset __P((tx_chipset_tag_t)); 44 void tx3912video_resolution_init __P((tx_chipset_tag_t, int, int)); 45 int tx3912video_fbdepth __P((tx_chipset_tag_t, int)); 46 47 static u_int32_t framebuffer, framebuffersize; 48 49 int tx3912video_match __P((struct device*, struct cfdata*, void*)); 50 void tx3912video_attach __P((struct device*, struct device*, void*)); 51 int tx3912video_print __P((void*, const char*)); 52 53 struct tx3912video_softc { 54 struct device sc_dev; 55 u_int32_t sc_fbaddr; 56 u_int32_t sc_fbsize; 57 }; 58 59 struct fb_attach_args { 60 const char *fba_name; 61 }; 62 63 struct cfattach tx3912video_ca = { 64 sizeof(struct tx3912video_softc), tx3912video_match, tx3912video_attach 65 }; 66 67 int 68 tx3912video_match(parent, cf, aux) 69 struct device *parent; 70 struct cfdata *cf; 71 void *aux; 72 { 73 return 1; 74 } 75 76 void 77 tx3912video_attach(parent, self, aux) 78 struct device *parent; 79 struct device *self; 80 void *aux; 81 { 82 struct txsim_attach_args *ta = aux; 83 struct tx3912video_softc *sc = (void*)self; 84 tx_chipset_tag_t tc = ta->ta_tc; 85 struct fb_attach_args fba; 86 87 printf("\n"); 88 sc->sc_fbaddr = framebuffer; 89 sc->sc_fbsize = framebuffersize; 90 printf("TMPR3912 video module ["); 91 tx3912video_fbdepth(tc, 1); 92 printf("] frame buffer: 0x%08x-0x%08x\n", sc->sc_fbaddr, 93 sc->sc_fbaddr + sc->sc_fbsize); 94 95 /* Attach frame buffer device */ 96 fba.fba_name = "fb"; 97 config_found(self, &fba, tx3912video_print); 98 } 99 100 int 101 tx3912video_print(aux, pnp) 102 void *aux; 103 const char *pnp; 104 { 105 return pnp ? QUIET : UNCONF; 106 } 107 108 int 109 tx3912video_init(tc, fb_start, fb_width, fb_height, fb_addr, fb_size, 110 fb_line_bytes) 111 tx_chipset_tag_t tc; 112 u_int32_t fb_start; /* Physical address */ 113 int fb_width, fb_height; 114 u_int32_t *fb_addr, *fb_size; 115 int *fb_line_bytes; 116 { 117 u_int32_t addr, size; 118 int fb_depth; 119 120 /* Inquire bit depth */ 121 fb_depth = tx3912video_fbdepth(tc, 0); 122 123 /* Allocate framebuffer area */ 124 if (tx3912video_framebuffer_alloc(tc, fb_start, fb_width, fb_height, 125 fb_depth, &addr, &size)) { 126 return 1; 127 } 128 #if notyet 129 tx3912video_resolution_init(tc, fb_width, fb_height); 130 #else 131 /* Use Windows CE setting. */ 132 #endif 133 /* Set DMA transfer address to VID module */ 134 tx3912video_framebuffer_init(tc, addr, size); 135 136 /* Syncronize framebuffer addr to frame signal */ 137 tx3912video_reset(tc); 138 139 *fb_line_bytes = (fb_width * fb_depth) / 8; 140 *fb_addr = addr; /* Phsical address */ 141 *fb_size = size; 142 143 return 0; 144 } 145 146 int 147 tx3912video_framebuffer_alloc(tc, start, h, v, depth, fb_addr, fb_size) 148 tx_chipset_tag_t tc; 149 u_int32_t start; 150 int h, v, depth; 151 u_int32_t *fb_addr, *fb_size; 152 { 153 struct extent_fixed ex_fixed[2]; 154 struct extent *ex; 155 u_long addr, size; 156 int err; 157 158 /* Calcurate frame buffer size */ 159 size = (h * v * depth) / 8; 160 161 /* Allocate V-RAM area */ 162 if (!(ex = extent_create("Frame buffer address", start, 163 start + TX3912_FRAMEBUFFER_MAX, 164 0, (caddr_t)ex_fixed, sizeof ex_fixed, 165 EX_NOWAIT))) { 166 return 1; 167 } 168 if((err = extent_alloc_subregion(ex, start, start + size, size, 169 TX3912_FRAMEBUFFER_ALIGNMENT, 170 TX3912_FRAMEBUFFER_BOUNDARY, 171 EX_FAST|EX_NOWAIT, &addr))) { 172 return 1; 173 } 174 framebuffer = addr; 175 framebuffersize = size; 176 *fb_addr = addr; 177 *fb_size = size; 178 179 return 0; 180 } 181 182 void 183 tx3912video_framebuffer_init(tc, fb_addr, fb_size) 184 tx_chipset_tag_t tc; 185 u_int32_t fb_addr, fb_size; 186 { 187 u_int32_t reg, vaddr, bank, base; 188 189 /* XXX currently I don't set DFVAL, so force DF signal toggled on 190 * XXX each frame. */ 191 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 192 reg &= ~TX3912_VIDEOCTRL1_DFMODE; 193 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 194 195 /* Set DMA transfer start and end address */ 196 197 bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr); 198 base = TX3912_VIDEOCTRL3_VIDBASEHI(fb_addr); 199 reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank); 200 /* Upper address counter */ 201 reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base); 202 tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg); 203 204 /* Lower address counter */ 205 base = TX3912_VIDEOCTRL4_VIDBASELO(fb_addr + fb_size); 206 reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base); 207 208 /* Set DF-signal rate */ 209 reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/ 210 211 /* Set VIDDONE signal delay after FRAME signal */ 212 /* XXX not yet*/ 213 tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg); 214 215 /* Clear frame buffer */ 216 vaddr = MIPS_PHYS_TO_KSEG1(fb_addr); 217 bzero((void*)vaddr, fb_size); 218 } 219 220 void 221 tx3912video_resolution_init(tc, h, v) 222 tx_chipset_tag_t tc; 223 int h; 224 int v; 225 { 226 u_int32_t reg, val; 227 int split, bit8, horzval, lineval; 228 229 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 230 split = reg & TX3912_VIDEOCTRL1_DISPSPLIT; 231 bit8 = (TX3912_VIDEOCTRL1_BITSEL(reg) == 232 TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR); 233 val = TX3912_VIDEOCTRL1_BITSEL(reg); 234 235 if ((val == TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR) && 236 !split) { 237 horzval = (h / 8) * 3 - 1; /* (LCD horizontal pixels / 8bit) * RGB - 1 */ 238 } else { 239 horzval = h / 4 - 1; 240 } 241 lineval = (split ? v / 2 : v) - 1; 242 243 /* Video rate */ 244 /* XXX probably This value should be determined from DFINT and LCDINT */ 245 reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1); 246 /* Horizontal size of LCD */ 247 reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval); 248 /* # of lines for the LCD */ 249 reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval); 250 251 tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg); 252 } 253 254 int 255 tx3912video_fbdepth(tc, verbose) 256 tx_chipset_tag_t tc; 257 int verbose; 258 { 259 u_int32_t reg, val; 260 261 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 262 val = TX3912_VIDEOCTRL1_BITSEL(reg); 263 switch (val) { 264 case TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR: 265 if (verbose) 266 printf("8bit color"); 267 return 8; 268 case TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE: 269 if (verbose) 270 printf("4bit greyscale"); 271 return 4; 272 case TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE: 273 if (verbose) 274 printf("2bit greyscale"); 275 return 2; 276 case TX3912_VIDEOCTRL1_BITSEL_MONOCHROME: 277 if (verbose) 278 printf("monochrome"); 279 return 1; 280 } 281 return 0; 282 } 283 284 void 285 tx3912video_reset(tc) 286 tx_chipset_tag_t tc; 287 { 288 u_int32_t reg; 289 290 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 291 /* Disable video logic at end of this frame */ 292 reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME; 293 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 294 /* Wait for end of frame */ 295 delay(300 * 1000); 296 /* Make sure to disable video logic */ 297 reg &= ~TX3912_VIDEOCTRL1_ENVID; 298 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 299 delay(1000); 300 /* Enable video logic again */ 301 reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME; 302 reg |= TX3912_VIDEOCTRL1_ENVID; 303 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 304 delay(1000); 305 } 306 307 308
Indexes created Fri Oct 31 11:10:07 GMT 2025