tx3912video.c revision 1.17
1 /* $NetBSD: tx3912video.c,v 1.17 2000/06/29 08:18:00 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 UCHIYAMA Yasushi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 #define TX3912VIDEO_DEBUG 29 30 #include "opt_tx39_debug.h" 31 #include "hpcfb.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/extent.h> 37 38 #include <sys/ioctl.h> 39 #include <sys/buf.h> 40 41 #include <uvm/uvm_extern.h> 42 43 #include <machine/bus.h> 44 #include <machine/bootinfo.h> 45 46 #include <hpcmips/tx/tx39var.h> 47 #include <hpcmips/tx/tx3912videovar.h> 48 #include <hpcmips/tx/tx3912videoreg.h> 49 50 /* CLUT */ 51 #include <dev/wscons/wsdisplayvar.h> 52 #include <dev/rasops/rasops.h> 53 #include <arch/hpcmips/dev/video_subr.h> 54 55 #include <dev/wscons/wsconsio.h> 56 #include <arch/hpcmips/dev/hpcfbvar.h> 57 #include <arch/hpcmips/dev/hpcfbio.h> 58 59 struct tx3912video_softc { 60 struct device sc_dev; 61 struct hpcfb_fbconf sc_fbconf; 62 struct hpcfb_dspconf sc_dspconf; 63 struct video_chip *sc_chip; 64 }; 65 66 /* TX3912 built-in video chip itself */ 67 static struct video_chip tx3912video_chip; 68 69 void tx3912video_framebuffer_init __P((struct video_chip *)); 70 int tx3912video_framebuffer_alloc __P((struct video_chip *, 71 paddr_t, paddr_t *)); 72 void tx3912video_reset __P((struct video_chip *)); 73 void tx3912video_resolution_init __P((struct video_chip *)); 74 75 int tx3912video_match __P((struct device *, struct cfdata *, void *)); 76 void tx3912video_attach __P((struct device *, struct device *, void *)); 77 int tx3912video_print __P((void *, const char *)); 78 79 void tx3912video_hpcfbinit __P((struct tx3912video_softc *)); 80 int tx3912video_ioctl __P((void *, u_long, caddr_t, int, struct proc *)); 81 paddr_t tx3912video_mmap __P((void *, off_t, int)); 82 83 void tx3912video_clut_init __P((struct tx3912video_softc *)); 84 void tx3912video_clut_install __P((void *, struct rasops_info *)); 85 void tx3912video_clut_get __P((struct tx3912video_softc *, 86 u_int32_t *, int, int)); 87 static int __get_color8 __P((int)); 88 static int __get_color4 __P((int)); 89 90 struct cfattach tx3912video_ca = { 91 sizeof(struct tx3912video_softc), tx3912video_match, 92 tx3912video_attach 93 }; 94 95 struct hpcfb_accessops tx3912video_ha = { 96 tx3912video_ioctl, tx3912video_mmap, 0, 0, 0, 0, 97 tx3912video_clut_install 98 }; 99 100 int 101 tx3912video_match(parent, cf, aux) 102 struct device *parent; 103 struct cfdata *cf; 104 void *aux; 105 { 106 return (1); 107 } 108 109 void 110 tx3912video_attach(parent, self, aux) 111 struct device *parent; 112 struct device *self; 113 void *aux; 114 { 115 struct tx3912video_softc *sc = (void *)self; 116 struct video_chip *chip; 117 const char *depth_print[] = { 118 [TX3912_VIDEOCTRL1_BITSEL_MONOCHROME] = "monochrome", 119 [TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE] = "2bit greyscale", 120 [TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE] = "4bit greyscale", 121 [TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR] = "8bit color" 122 }; 123 struct hpcfb_attach_args ha; 124 tx_chipset_tag_t tc; 125 txreg_t val; 126 int console = (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) ? 0 : 1; 127 128 sc->sc_chip = chip = &tx3912video_chip; 129 130 /* print video module information */ 131 printf(": %s, frame buffer 0x%08x-0x%08x\n", 132 depth_print[(ffs(chip->vc_fbdepth) - 1) & 0x3], 133 (unsigned)chip->vc_fbpaddr, 134 (unsigned)(chip->vc_fbpaddr + chip->vc_fbsize)); 135 136 /* don't inverse VDAT[3:0] signal */ 137 tc = chip->vc_v; 138 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 139 val &= ~TX3912_VIDEOCTRL1_INVVID; 140 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 141 142 /* install default CLUT */ 143 tx3912video_clut_init(sc); 144 145 /* if serial console, power off video module */ 146 #ifndef TX3912VIDEO_DEBUG 147 if (!console) { 148 printf("%s: power off\n", sc->sc_dev.dv_xname); 149 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 150 val &= ~(TX3912_VIDEOCTRL1_DISPON | 151 TX3912_VIDEOCTRL1_ENVID); 152 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 153 } 154 #endif /* TX3912VIDEO_DEBUG */ 155 156 #ifdef TX3912VIDEO_DEBUG 157 /* attach debug draw routine (debugging use) */ 158 video_attach_drawfunc(sc->sc_chip); 159 tx_conf_register_video(tc, sc->sc_chip); 160 #endif 161 162 /* Attach frame buffer device */ 163 tx3912video_hpcfbinit(sc); 164 165 if (console && hpcfb_cnattach(&sc->sc_fbconf) != 0) { 166 panic("tx3912video_attach: can't init fb console"); 167 } 168 169 ha.ha_console = console; 170 ha.ha_accessops = &tx3912video_ha; 171 ha.ha_accessctx = sc; 172 ha.ha_curfbconf = 0; 173 ha.ha_nfbconf = 1; 174 ha.ha_fbconflist = &sc->sc_fbconf; 175 ha.ha_curdspconf = 0; 176 ha.ha_ndspconf = 1; 177 ha.ha_dspconflist = &sc->sc_dspconf; 178 179 config_found(self, &ha, hpcfbprint); 180 } 181 182 void 183 tx3912video_hpcfbinit(sc) 184 struct tx3912video_softc *sc; 185 { 186 struct video_chip *chip = sc->sc_chip; 187 struct hpcfb_fbconf *fb = &sc->sc_fbconf; 188 vaddr_t fbvaddr = (vaddr_t)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 189 190 memset(fb, 0, sizeof(struct hpcfb_fbconf)); 191 192 fb->hf_conf_index = 0; /* configuration index */ 193 fb->hf_nconfs = 1; /* how many configurations */ 194 strncpy(fb->hf_name, "TX3912 built-in video", HPCFB_MAXNAMELEN); 195 /* frame buffer name */ 196 strncpy(fb->hf_conf_name, "LCD", HPCFB_MAXNAMELEN); 197 /* configuration name */ 198 fb->hf_height = chip->vc_fbheight; 199 fb->hf_width = chip->vc_fbwidth; 200 fb->hf_baseaddr = mips_ptob(mips_btop(fbvaddr)); 201 fb->hf_offset = (u_long)fbvaddr - fb->hf_baseaddr; 202 /* frame buffer start offset */ 203 fb->hf_bytes_per_line = (chip->vc_fbwidth * chip->vc_fbdepth) 204 / NBBY; 205 fb->hf_nplanes = 1; 206 fb->hf_bytes_per_plane = chip->vc_fbheight * fb->hf_bytes_per_line; 207 208 fb->hf_access_flags |= HPCFB_ACCESS_BYTE; 209 fb->hf_access_flags |= HPCFB_ACCESS_WORD; 210 fb->hf_access_flags |= HPCFB_ACCESS_DWORD; 211 212 switch (chip->vc_fbdepth) { 213 default: 214 panic("tx3912video_hpcfbinit: not supported color depth\n"); 215 /* NOTREACHED */ 216 case 2: 217 fb->hf_class = HPCFB_CLASS_GRAYSCALE; 218 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 219 fb->hf_pack_width = 8; 220 fb->hf_pixels_per_pack = 4; 221 fb->hf_pixel_width = 2; 222 fb->hf_class_data_length = sizeof(struct hf_gray_tag); 223 /* reserved for future use */ 224 fb->hf_u.hf_gray.hf_flags = 0; 225 break; 226 case 8: 227 fb->hf_class = HPCFB_CLASS_INDEXCOLOR; 228 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 229 fb->hf_pack_width = 8; 230 fb->hf_pixels_per_pack = 1; 231 fb->hf_pixel_width = 8; 232 fb->hf_class_data_length = sizeof(struct hf_indexed_tag); 233 /* reserved for future use */ 234 fb->hf_u.hf_indexed.hf_flags = 0; 235 break; 236 } 237 } 238 239 int 240 tx3912video_init(fb_start, fb_end) 241 paddr_t fb_start, *fb_end; 242 { 243 struct video_chip *chip = &tx3912video_chip; 244 tx_chipset_tag_t tc; 245 txreg_t reg; 246 int fbdepth; 247 int error; 248 249 chip->vc_v = tc = tx_conf_get_tag(); 250 251 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 252 fbdepth = 1 << (TX3912_VIDEOCTRL1_BITSEL(reg)); 253 254 switch (fbdepth) { 255 case 2: 256 bootinfo->fb_type = BIFB_D2_M2L_0; 257 break; 258 case 4: 259 /* XXX should implement rasops4.c */ 260 fbdepth = 2; 261 bootinfo->fb_type = BIFB_D2_M2L_0; 262 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 263 TX3912_VIDEOCTRL1_BITSEL_CLR(reg); 264 reg = TX3912_VIDEOCTRL1_BITSEL_SET( 265 reg, TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE); 266 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 267 break; 268 case 8: 269 bootinfo->fb_type = BIFB_D8_FF; 270 break; 271 } 272 273 chip->vc_fbdepth = fbdepth; 274 chip->vc_fbwidth = bootinfo->fb_width; 275 chip->vc_fbheight= bootinfo->fb_height; 276 277 /* Allocate framebuffer area */ 278 error = tx3912video_framebuffer_alloc(chip, fb_start, fb_end); 279 if (error != 0) 280 return (1); 281 282 #if notyet 283 tx3912video_resolution_init(chip); 284 #else 285 /* Use Windows CE setting. */ 286 #endif 287 /* Set DMA transfer address to VID module */ 288 tx3912video_framebuffer_init(chip); 289 290 /* Syncronize framebuffer addr to frame signal */ 291 tx3912video_reset(chip); 292 293 bootinfo->fb_line_bytes = (chip->vc_fbwidth * fbdepth) / NBBY; 294 bootinfo->fb_addr = (void *)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 295 296 return (0); 297 } 298 299 int 300 tx3912video_framebuffer_alloc(chip, fb_start, fb_end) 301 struct video_chip *chip; 302 paddr_t fb_start, *fb_end; /* buffer allocation hint */ 303 { 304 struct extent_fixed ex_fixed[10]; 305 struct extent *ex; 306 u_long addr, size; 307 int error; 308 309 /* calcurate frame buffer size */ 310 size = (chip->vc_fbwidth * chip->vc_fbheight * chip->vc_fbdepth) / 311 NBBY; 312 313 /* extent V-RAM region */ 314 ex = extent_create("Frame buffer address", fb_start, *fb_end, 315 0, (caddr_t)ex_fixed, sizeof ex_fixed, 316 EX_NOWAIT); 317 if (ex == 0) 318 return (1); 319 320 /* Allocate V-RAM area */ 321 error = extent_alloc_subregion(ex, fb_start, fb_start + size - 1, 322 size, TX3912_FRAMEBUFFER_ALIGNMENT, 323 TX3912_FRAMEBUFFER_BOUNDARY, 324 EX_FAST|EX_NOWAIT, &addr); 325 extent_destroy(ex); 326 327 if (error != 0) { 328 return (1); 329 } 330 331 chip->vc_fbpaddr = addr; 332 chip->vc_fbvaddr = MIPS_PHYS_TO_KSEG1(addr); 333 chip->vc_fbsize = size; 334 335 *fb_end = addr + size; 336 337 return (0); 338 } 339 340 void 341 tx3912video_framebuffer_init(chip) 342 struct video_chip *chip; 343 { 344 u_int32_t fb_addr, fb_size, vaddr, bank, base; 345 txreg_t reg; 346 tx_chipset_tag_t tc = chip->vc_v; 347 348 fb_addr = chip->vc_fbpaddr; 349 fb_size = chip->vc_fbsize; 350 351 /* XXX currently I don't set DFVAL, so force DF signal toggled on 352 * XXX each frame. */ 353 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 354 reg &= ~TX3912_VIDEOCTRL1_DFMODE; 355 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 356 357 /* Set DMA transfer start and end address */ 358 359 bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr); 360 base = TX3912_VIDEOCTRL3_VIDBASEHI(fb_addr); 361 reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank); 362 /* Upper address counter */ 363 reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base); 364 tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg); 365 366 /* Lower address counter */ 367 base = TX3912_VIDEOCTRL4_VIDBASELO(fb_addr + fb_size); 368 reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base); 369 370 /* Set DF-signal rate */ 371 reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/ 372 373 /* Set VIDDONE signal delay after FRAME signal */ 374 /* XXX not yet*/ 375 tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg); 376 377 /* Clear frame buffer */ 378 vaddr = MIPS_PHYS_TO_KSEG1(fb_addr); 379 memset((void*)vaddr, 0, fb_size); 380 } 381 382 void 383 tx3912video_resolution_init(chip) 384 struct video_chip *chip; 385 { 386 int h, v, split, bit8, horzval, lineval; 387 tx_chipset_tag_t tc = chip->vc_v; 388 txreg_t reg; 389 u_int32_t val; 390 391 h = chip->vc_fbwidth; 392 v = chip->vc_fbheight; 393 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 394 split = reg & TX3912_VIDEOCTRL1_DISPSPLIT; 395 bit8 = (TX3912_VIDEOCTRL1_BITSEL(reg) == 396 TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR); 397 val = TX3912_VIDEOCTRL1_BITSEL(reg); 398 399 if ((val == TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR) && 400 !split) { 401 /* (LCD horizontal pixels / 8bit) * RGB - 1 */ 402 horzval = (h / 8) * 3 - 1; 403 } else { 404 horzval = h / 4 - 1; 405 } 406 lineval = (split ? v / 2 : v) - 1; 407 408 /* Video rate */ 409 /* XXX 410 * probably This value should be determined from DFINT and LCDINT 411 */ 412 reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1); 413 /* Horizontal size of LCD */ 414 reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval); 415 /* # of lines for the LCD */ 416 reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval); 417 418 tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg); 419 } 420 421 void 422 tx3912video_reset(chip) 423 struct video_chip *chip; 424 { 425 tx_chipset_tag_t tc = chip->vc_v; 426 txreg_t reg; 427 428 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 429 430 /* Disable video logic at end of this frame */ 431 reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME; 432 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 433 434 /* Wait for end of frame */ 435 delay(30 * 1000); 436 437 /* Make sure to disable video logic */ 438 reg &= ~TX3912_VIDEOCTRL1_ENVID; 439 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 440 441 delay(1000); 442 443 /* Enable video logic again */ 444 reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME; 445 reg |= TX3912_VIDEOCTRL1_ENVID; 446 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 447 448 delay(1000); 449 } 450 451 int 452 tx3912video_ioctl(v, cmd, data, flag, p) 453 void *v; 454 u_long cmd; 455 caddr_t data; 456 int flag; 457 struct proc *p; 458 { 459 struct tx3912video_softc *sc = (struct tx3912video_softc *)v; 460 struct hpcfb_fbconf *fbconf; 461 struct hpcfb_dspconf *dspconf; 462 struct wsdisplay_cmap *cmap; 463 u_int8_t *r, *g, *b; 464 u_int32_t *rgb; 465 int idx, cnt, error; 466 467 switch (cmd) { 468 case WSDISPLAYIO_GETCMAP: 469 cmap = (struct wsdisplay_cmap*)data; 470 cnt = cmap->count; 471 idx = cmap->index; 472 473 if (sc->sc_fbconf.hf_class != HPCFB_CLASS_INDEXCOLOR || 474 sc->sc_fbconf.hf_pack_width != 8 || 475 !LEGAL_CLUT_INDEX(idx) || 476 !LEGAL_CLUT_INDEX(idx + cnt -1)) { 477 return (EINVAL); 478 } 479 480 if (!uvm_useracc(cmap->red, cnt, B_WRITE) || 481 !uvm_useracc(cmap->green, cnt, B_WRITE) || 482 !uvm_useracc(cmap->blue, cnt, B_WRITE)) { 483 return (EFAULT); 484 } 485 486 error = cmap_work_alloc(&r, &g, &b, &rgb, cnt); 487 if (error != 0) { 488 cmap_work_free(r, g, b, rgb); 489 return (ENOMEM); 490 } 491 tx3912video_clut_get(sc, rgb, idx, cnt); 492 rgb24_decompose(rgb, r, g, b, cnt); 493 494 copyout(r, cmap->red, cnt); 495 copyout(g, cmap->green,cnt); 496 copyout(b, cmap->blue, cnt); 497 498 cmap_work_free(r, g, b, rgb); 499 500 return (0); 501 502 case WSDISPLAYIO_PUTCMAP: 503 /* 504 * TX3912 can't change CLUT index. R:G:B = 3:3:2 505 */ 506 return (0); 507 508 case HPCFBIO_GCONF: 509 fbconf = (struct hpcfb_fbconf *)data; 510 if (fbconf->hf_conf_index != 0 && 511 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 512 return (EINVAL); 513 } 514 *fbconf = sc->sc_fbconf; /* structure assignment */ 515 return (0); 516 517 case HPCFBIO_SCONF: 518 fbconf = (struct hpcfb_fbconf *)data; 519 if (fbconf->hf_conf_index != 0 && 520 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 521 return (EINVAL); 522 } 523 /* 524 * nothing to do because we have only one configration 525 */ 526 return (0); 527 528 case HPCFBIO_GDSPCONF: 529 dspconf = (struct hpcfb_dspconf *)data; 530 if ((dspconf->hd_unit_index != 0 && 531 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 532 (dspconf->hd_conf_index != 0 && 533 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 534 return (EINVAL); 535 } 536 *dspconf = sc->sc_dspconf; /* structure assignment */ 537 return (0); 538 539 case HPCFBIO_SDSPCONF: 540 dspconf = (struct hpcfb_dspconf *)data; 541 if ((dspconf->hd_unit_index != 0 && 542 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 543 (dspconf->hd_conf_index != 0 && 544 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 545 return (EINVAL); 546 } 547 /* 548 * nothing to do 549 * because we have only one unit and one configration 550 */ 551 return (0); 552 553 case HPCFBIO_GOP: 554 case HPCFBIO_SOP: 555 /* XXX not implemented yet */ 556 return (EINVAL); 557 } 558 559 return (ENOTTY); 560 } 561 562 paddr_t 563 tx3912video_mmap(ctx, offset, prot) 564 void *ctx; 565 off_t offset; 566 int prot; 567 { 568 struct tx3912video_softc *sc = (struct tx3912video_softc *)ctx; 569 570 if (offset < 0 || (sc->sc_fbconf.hf_bytes_per_plane + 571 sc->sc_fbconf.hf_offset) < offset) { 572 return (-1); 573 } 574 575 return (mips_btop(sc->sc_chip->vc_fbpaddr + offset)); 576 } 577 578 /* 579 * CLUT staff 580 */ 581 static const struct { 582 int mul, div; 583 } dither_list [] = { 584 [TX3912_VIDEO_DITHER_DUTYCYCLE_1] = { 1, 1 }, 585 [TX3912_VIDEO_DITHER_DUTYCYCLE_6_7] = { 6, 7 }, 586 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_5] = { 4, 5 }, 587 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_4] = { 3, 4 }, 588 [TX3912_VIDEO_DITHER_DUTYCYCLE_5_7] = { 5, 7 }, 589 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_3] = { 2, 3 }, 590 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_5] = { 3, 5 }, 591 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_7] = { 4, 7 }, 592 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_4] = { 2, 4 }, 593 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_7] = { 3, 7 }, 594 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_5] = { 2, 5 }, 595 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_3] = { 1, 3 }, 596 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_7] = { 2, 7 }, 597 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_5] = { 1, 5 }, 598 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_7] = { 1, 7 }, 599 [TX3912_VIDEO_DITHER_DUTYCYCLE_0] = { 0, 1 } 600 }, *dlp; 601 602 static const int dither_level8[8] = { 603 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 604 TX3912_VIDEO_DITHER_DUTYCYCLE_2_7, 605 TX3912_VIDEO_DITHER_DUTYCYCLE_2_5, 606 TX3912_VIDEO_DITHER_DUTYCYCLE_2_4, 607 TX3912_VIDEO_DITHER_DUTYCYCLE_3_5, 608 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 609 TX3912_VIDEO_DITHER_DUTYCYCLE_4_5, 610 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 611 }; 612 613 static const int dither_level4[4] = { 614 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 615 TX3912_VIDEO_DITHER_DUTYCYCLE_1_3, 616 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 617 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 618 }; 619 620 static int 621 __get_color8(luti) 622 int luti; 623 { 624 KASSERT(luti >=0 && luti < 8); 625 dlp = &dither_list[dither_level8[luti]]; 626 627 return ((0xff * dlp->mul) / dlp->div); 628 } 629 630 static int 631 __get_color4(luti) 632 int luti; 633 { 634 KASSERT(luti >=0 && luti < 4); 635 dlp = &dither_list[dither_level4[luti]]; 636 637 return ((0xff * dlp->mul) / dlp->div); 638 } 639 640 void 641 tx3912video_clut_get(sc, rgb, beg, cnt) 642 struct tx3912video_softc *sc; 643 u_int32_t *rgb; 644 int beg, cnt; 645 { 646 int i; 647 648 KASSERT(rgb); 649 KASSERT(LEGAL_CLUT_INDEX(beg)); 650 KASSERT(LEGAL_CLUT_INDEX(beg + cnt - 1)); 651 652 for (i = beg; i < beg + cnt; i++) { 653 *rgb++ = RGB24(__get_color8((i >> 5) & 0x7), 654 __get_color8((i >> 2) & 0x7), 655 __get_color4(i & 0x3)); 656 } 657 } 658 659 void 660 tx3912video_clut_install(ctx, ri) 661 void *ctx; 662 struct rasops_info *ri; 663 { 664 struct tx3912video_softc *sc = ctx; 665 const int system_cmap[0x10] = { 666 TX3912VIDEO_BLACK, 667 TX3912VIDEO_RED, 668 TX3912VIDEO_GREEN, 669 TX3912VIDEO_YELLOW, 670 TX3912VIDEO_BLUE, 671 TX3912VIDEO_MAGENTA, 672 TX3912VIDEO_CYAN, 673 TX3912VIDEO_WHITE, 674 TX3912VIDEO_DARK_BLACK, 675 TX3912VIDEO_DARK_RED, 676 TX3912VIDEO_DARK_GREEN, 677 TX3912VIDEO_DARK_YELLOW, 678 TX3912VIDEO_DARK_BLUE, 679 TX3912VIDEO_DARK_MAGENTA, 680 TX3912VIDEO_DARK_CYAN, 681 TX3912VIDEO_DARK_WHITE, 682 }; 683 684 KASSERT(ri); 685 686 if (sc->sc_chip->vc_fbdepth == 8) { 687 /* XXX 2bit gray scale LUT not supported */ 688 memcpy(ri->ri_devcmap, system_cmap, sizeof system_cmap); 689 } 690 } 691 692 void 693 tx3912video_clut_init(sc) 694 struct tx3912video_softc *sc; 695 { 696 tx_chipset_tag_t tc = sc->sc_chip->vc_v; 697 698 if (sc->sc_chip->vc_fbdepth != 8) { 699 return; /* XXX 2bit gray scale LUT not supported */ 700 } 701 702 /* 703 * time-based dithering pattern (TOSHIBA recommended pattern) 704 */ 705 /* 2/3, 1/3 */ 706 tx_conf_write(tc, TX3912_VIDEOCTRL8_REG, 707 TX3912_VIDEOCTRL8_PAT2_3_DEFAULT); 708 /* 3/4, 2/4 */ 709 tx_conf_write(tc, TX3912_VIDEOCTRL9_REG, 710 (TX3912_VIDEOCTRL9_PAT3_4_DEFAULT << 16) | 711 TX3912_VIDEOCTRL9_PAT2_4_DEFAULT); 712 /* 4/5, 1/5 */ 713 tx_conf_write(tc, TX3912_VIDEOCTRL10_REG, 714 TX3912_VIDEOCTRL10_PAT4_5_DEFAULT); 715 /* 3/5, 2/5 */ 716 tx_conf_write(tc, TX3912_VIDEOCTRL11_REG, 717 TX3912_VIDEOCTRL11_PAT3_5_DEFAULT); 718 /* 6/7, 1/7 */ 719 tx_conf_write(tc, TX3912_VIDEOCTRL12_REG, 720 TX3912_VIDEOCTRL12_PAT6_7_DEFAULT); 721 /* 5/7, 2/7 */ 722 tx_conf_write(tc, TX3912_VIDEOCTRL13_REG, 723 TX3912_VIDEOCTRL13_PAT5_7_DEFAULT); 724 /* 4/7, 3/7 */ 725 tx_conf_write(tc, TX3912_VIDEOCTRL14_REG, 726 TX3912_VIDEOCTRL14_PAT4_7_DEFAULT); 727 728 /* 729 * dither-pattern look-up table. (selected by uch) 730 */ 731 /* red */ 732 tx_conf_write(tc, TX3912_VIDEOCTRL5_REG, 733 (dither_level8[7] << 28) | 734 (dither_level8[6] << 24) | 735 (dither_level8[5] << 20) | 736 (dither_level8[4] << 16) | 737 (dither_level8[3] << 12) | 738 (dither_level8[2] << 8) | 739 (dither_level8[1] << 4) | 740 (dither_level8[0] << 0)); 741 /* green */ 742 tx_conf_write(tc, TX3912_VIDEOCTRL6_REG, 743 (dither_level8[7] << 28) | 744 (dither_level8[6] << 24) | 745 (dither_level8[5] << 20) | 746 (dither_level8[4] << 16) | 747 (dither_level8[3] << 12) | 748 (dither_level8[2] << 8) | 749 (dither_level8[1] << 4) | 750 (dither_level8[0] << 0)); 751 /* blue (2bit gray scale also use this look-up table) */ 752 tx_conf_write(tc, TX3912_VIDEOCTRL7_REG, 753 (dither_level4[3] << 12) | 754 (dither_level4[2] << 8) | 755 (dither_level4[1] << 4) | 756 (dither_level4[0] << 0)); 757 758 tx3912video_reset(sc->sc_chip); 759 } 760
Indexes created Fri Oct 31 11:10:07 GMT 2025