tx3912video.c revision 1.2
1 /* $NetBSD: tx3912video.c,v 1.2 1999/11/29 17:21:22 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include "opt_tx39_debug.h" 29 #include "fb.h" 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/device.h> 34 #include <sys/extent.h> 35 36 #include <machine/bus.h> 37 #include <machine/bootinfo.h> /* bootinfo */ 38 39 #include <hpcmips/tx/tx39var.h> 40 #include <hpcmips/tx/tx3912videovar.h> 41 #include <hpcmips/tx/tx3912videoreg.h> 42 43 #if NFB > 0 44 #include <dev/rcons/raster.h> 45 #include <dev/wscons/wsdisplayvar.h> 46 #include <arch/hpcmips/dev/fbvar.h> 47 #endif 48 49 void tx3912video_framebuffer_init __P((tx_chipset_tag_t, u_int32_t, u_int32_t)); 50 int tx3912video_framebuffer_alloc __P((tx_chipset_tag_t, u_int32_t, int, int, int, u_int32_t*, u_int32_t*)); 51 void tx3912video_reset __P((tx_chipset_tag_t)); 52 void tx3912video_resolution_init __P((tx_chipset_tag_t, int, int)); 53 int tx3912video_fbdepth __P((tx_chipset_tag_t, int)); 54 55 static u_int32_t framebuffer, framebuffersize; 56 57 int tx3912video_match __P((struct device*, struct cfdata*, void*)); 58 void tx3912video_attach __P((struct device*, struct device*, void*)); 59 int tx3912video_print __P((void*, const char*)); 60 61 struct tx3912video_softc { 62 struct device sc_dev; 63 u_int32_t sc_fbaddr; 64 u_int32_t sc_fbsize; 65 }; 66 67 struct fb_attach_args { 68 const char *fba_name; 69 }; 70 71 struct cfattach tx3912video_ca = { 72 sizeof(struct tx3912video_softc), tx3912video_match, tx3912video_attach 73 }; 74 75 int 76 tx3912video_match(parent, cf, aux) 77 struct device *parent; 78 struct cfdata *cf; 79 void *aux; 80 { 81 return 1; 82 } 83 84 void 85 tx3912video_attach(parent, self, aux) 86 struct device *parent; 87 struct device *self; 88 void *aux; 89 { 90 struct txsim_attach_args *ta = aux; 91 struct tx3912video_softc *sc = (void*)self; 92 tx_chipset_tag_t tc = ta->ta_tc; 93 struct fb_attach_args fba; 94 95 printf("\n"); 96 sc->sc_fbaddr = framebuffer; 97 sc->sc_fbsize = framebuffersize; 98 printf("TMPR3912 video module ["); 99 tx3912video_fbdepth(tc, 1); 100 printf("] frame buffer: 0x%08x-0x%08x\n", sc->sc_fbaddr, 101 sc->sc_fbaddr + sc->sc_fbsize); 102 103 /* Attach frame buffer device */ 104 #if NFB > 0 105 if (!(bootinfo->bi_cnuse & BI_CNUSE_SERIAL)) { 106 if (fb_cnattach(0, 0, 0, 0)) { 107 panic("tx3912video_attach: can't init fb console"); 108 } 109 } 110 fba.fba_name = "fb"; 111 config_found(self, &fba, tx3912video_print); 112 #endif 113 } 114 115 int 116 tx3912video_print(aux, pnp) 117 void *aux; 118 const char *pnp; 119 { 120 return pnp ? QUIET : UNCONF; 121 } 122 123 int 124 tx3912video_init(tc, fb_start, fb_width, fb_height, fb_addr, fb_size, 125 fb_line_bytes) 126 tx_chipset_tag_t tc; 127 u_int32_t fb_start; /* Physical address */ 128 int fb_width, fb_height; 129 u_int32_t *fb_addr, *fb_size; 130 int *fb_line_bytes; 131 { 132 u_int32_t addr, size; 133 int fb_depth; 134 135 /* Inquire bit depth */ 136 fb_depth = tx3912video_fbdepth(tc, 0); 137 138 /* Allocate framebuffer area */ 139 if (tx3912video_framebuffer_alloc(tc, fb_start, fb_width, fb_height, 140 fb_depth, &addr, &size)) { 141 return 1; 142 } 143 #if notyet 144 tx3912video_resolution_init(tc, fb_width, fb_height); 145 #else 146 /* Use Windows CE setting. */ 147 #endif 148 /* Set DMA transfer address to VID module */ 149 tx3912video_framebuffer_init(tc, addr, size); 150 151 /* Syncronize framebuffer addr to frame signal */ 152 tx3912video_reset(tc); 153 154 *fb_line_bytes = (fb_width * fb_depth) / 8; 155 *fb_addr = addr; /* Phsical address */ 156 *fb_size = size; 157 158 return 0; 159 } 160 161 int 162 tx3912video_framebuffer_alloc(tc, start, h, v, depth, fb_addr, fb_size) 163 tx_chipset_tag_t tc; 164 u_int32_t start; 165 int h, v, depth; 166 u_int32_t *fb_addr, *fb_size; 167 { 168 struct extent_fixed ex_fixed[2]; 169 struct extent *ex; 170 u_long addr, size; 171 int err; 172 173 /* Calcurate frame buffer size */ 174 size = (h * v * depth) / 8; 175 176 /* Allocate V-RAM area */ 177 if (!(ex = extent_create("Frame buffer address", start, 178 start + TX3912_FRAMEBUFFER_MAX, 179 0, (caddr_t)ex_fixed, sizeof ex_fixed, 180 EX_NOWAIT))) { 181 return 1; 182 } 183 if((err = extent_alloc_subregion(ex, start, start + size, size, 184 TX3912_FRAMEBUFFER_ALIGNMENT, 185 TX3912_FRAMEBUFFER_BOUNDARY, 186 EX_FAST|EX_NOWAIT, &addr))) { 187 return 1; 188 } 189 framebuffer = addr; 190 framebuffersize = size; 191 *fb_addr = addr; 192 *fb_size = size; 193 194 return 0; 195 } 196 197 void 198 tx3912video_framebuffer_init(tc, fb_addr, fb_size) 199 tx_chipset_tag_t tc; 200 u_int32_t fb_addr, fb_size; 201 { 202 u_int32_t reg, vaddr, bank, base; 203 204 /* XXX currently I don't set DFVAL, so force DF signal toggled on 205 * XXX each frame. */ 206 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 207 reg &= ~TX3912_VIDEOCTRL1_DFMODE; 208 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 209 210 /* Set DMA transfer start and end address */ 211 212 bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr); 213 base = TX3912_VIDEOCTRL3_VIDBASEHI(fb_addr); 214 reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank); 215 /* Upper address counter */ 216 reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base); 217 tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg); 218 219 /* Lower address counter */ 220 base = TX3912_VIDEOCTRL4_VIDBASELO(fb_addr + fb_size); 221 reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base); 222 223 /* Set DF-signal rate */ 224 reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/ 225 226 /* Set VIDDONE signal delay after FRAME signal */ 227 /* XXX not yet*/ 228 tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg); 229 230 /* Clear frame buffer */ 231 vaddr = MIPS_PHYS_TO_KSEG1(fb_addr); 232 bzero((void*)vaddr, fb_size); 233 } 234 235 void 236 tx3912video_resolution_init(tc, h, v) 237 tx_chipset_tag_t tc; 238 int h; 239 int v; 240 { 241 u_int32_t reg, val; 242 int split, bit8, horzval, lineval; 243 244 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 245 split = reg & TX3912_VIDEOCTRL1_DISPSPLIT; 246 bit8 = (TX3912_VIDEOCTRL1_BITSEL(reg) == 247 TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR); 248 val = TX3912_VIDEOCTRL1_BITSEL(reg); 249 250 if ((val == TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR) && 251 !split) { 252 horzval = (h / 8) * 3 - 1; /* (LCD horizontal pixels / 8bit) * RGB - 1 */ 253 } else { 254 horzval = h / 4 - 1; 255 } 256 lineval = (split ? v / 2 : v) - 1; 257 258 /* Video rate */ 259 /* XXX probably This value should be determined from DFINT and LCDINT */ 260 reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1); 261 /* Horizontal size of LCD */ 262 reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval); 263 /* # of lines for the LCD */ 264 reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval); 265 266 tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg); 267 } 268 269 int 270 tx3912video_fbdepth(tc, verbose) 271 tx_chipset_tag_t tc; 272 int verbose; 273 { 274 u_int32_t reg, val; 275 276 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 277 val = TX3912_VIDEOCTRL1_BITSEL(reg); 278 switch (val) { 279 case TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR: 280 if (verbose) 281 printf("8bit color"); 282 return 8; 283 case TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE: 284 if (verbose) 285 printf("4bit greyscale"); 286 return 4; 287 case TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE: 288 if (verbose) 289 printf("2bit greyscale"); 290 return 2; 291 case TX3912_VIDEOCTRL1_BITSEL_MONOCHROME: 292 if (verbose) 293 printf("monochrome"); 294 return 1; 295 } 296 return 0; 297 } 298 299 void 300 tx3912video_reset(tc) 301 tx_chipset_tag_t tc; 302 { 303 u_int32_t reg; 304 305 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 306 /* Disable video logic at end of this frame */ 307 reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME; 308 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 309 /* Wait for end of frame */ 310 delay(300 * 1000); 311 /* Make sure to disable video logic */ 312 reg &= ~TX3912_VIDEOCTRL1_ENVID; 313 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 314 delay(1000); 315 /* Enable video logic again */ 316 reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME; 317 reg |= TX3912_VIDEOCTRL1_ENVID; 318 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 319 delay(1000); 320 } 321 322 323
Indexes created Fri Oct 31 11:10:07 GMT 2025