tx3912video.c revision 1.20
1 /* $NetBSD: tx3912video.c,v 1.20 2000/10/22 12:49:27 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #define TX3912VIDEO_DEBUG 40 41 #include "opt_tx39_debug.h" 42 #include "hpcfb.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/extent.h> 48 49 #include <sys/ioctl.h> 50 #include <sys/buf.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <dev/cons.h> /* consdev */ 55 56 #include <machine/bus.h> 57 #include <machine/bootinfo.h> 58 #include <machine/config_hook.h> 59 60 #include <hpcmips/tx/tx39var.h> 61 #include <hpcmips/tx/tx3912videovar.h> 62 #include <hpcmips/tx/tx3912videoreg.h> 63 64 /* CLUT */ 65 #include <dev/wscons/wsdisplayvar.h> 66 #include <dev/rasops/rasops.h> 67 #include <arch/hpcmips/dev/video_subr.h> 68 69 #include <dev/wscons/wsconsio.h> 70 #include <arch/hpcmips/dev/hpcfbvar.h> 71 #include <arch/hpcmips/dev/hpcfbio.h> 72 73 #ifdef TX3912VIDEO_DEBUG 74 int tx3912video_debug = 1; 75 #define DPRINTF(arg) if (tx3912video_debug) printf arg; 76 #define DPRINTFN(n, arg) if (tx3912video_debug > (n)) printf arg; 77 #else 78 #define DPRINTF(arg) 79 #define DPRINTFN(n, arg) 80 #endif 81 82 struct tx3912video_softc { 83 struct device sc_dev; 84 void *sc_powerhook; /* power management hook */ 85 int sc_console; 86 struct hpcfb_fbconf sc_fbconf; 87 struct hpcfb_dspconf sc_dspconf; 88 struct video_chip *sc_chip; 89 }; 90 91 /* TX3912 built-in video chip itself */ 92 static struct video_chip tx3912video_chip; 93 94 int tx3912video_power(void *, int, long, void *); 95 void tx3912video_framebuffer_init(struct video_chip *); 96 int tx3912video_framebuffer_alloc(struct video_chip *, paddr_t, paddr_t *); 97 void tx3912video_reset(struct video_chip *); 98 void tx3912video_resolution_init(struct video_chip *); 99 int tx3912video_match(struct device *, struct cfdata *, void *); 100 void tx3912video_attach(struct device *, struct device *, void *); 101 int tx3912video_print(void *, const char *); 102 103 void tx3912video_hpcfbinit(struct tx3912video_softc *); 104 int tx3912video_ioctl(void *, u_long, caddr_t, int, struct proc *); 105 paddr_t tx3912video_mmap(void *, off_t, int); 106 107 void tx3912video_clut_init(struct tx3912video_softc *); 108 void tx3912video_clut_install(void *, struct rasops_info *); 109 void tx3912video_clut_get(struct tx3912video_softc *, u_int32_t *, int, int); 110 111 static int __get_color8(int); 112 static int __get_color4(int); 113 114 struct cfattach tx3912video_ca = { 115 sizeof(struct tx3912video_softc), tx3912video_match, 116 tx3912video_attach 117 }; 118 119 struct hpcfb_accessops tx3912video_ha = { 120 tx3912video_ioctl, tx3912video_mmap, 0, 0, 0, 0, 121 tx3912video_clut_install 122 }; 123 124 int 125 tx3912video_match(struct device *parent, struct cfdata *cf, void *aux) 126 { 127 return ATTACH_NORMAL; 128 } 129 130 void 131 tx3912video_attach(struct device *parent, struct device *self, void *aux) 132 { 133 struct tx3912video_softc *sc = (void *)self; 134 struct video_chip *chip; 135 const char *depth_print[] = { 136 [TX3912_VIDEOCTRL1_BITSEL_MONOCHROME] = "monochrome", 137 [TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE] = "2bit greyscale", 138 [TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE] = "4bit greyscale", 139 [TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR] = "8bit color" 140 }; 141 struct hpcfb_attach_args ha; 142 tx_chipset_tag_t tc; 143 txreg_t val; 144 int console; 145 146 sc->sc_console = console = cn_tab ? 0 : 1; 147 sc->sc_chip = chip = &tx3912video_chip; 148 149 /* print video module information */ 150 printf(": %s, frame buffer 0x%08x-0x%08x\n", 151 depth_print[(ffs(chip->vc_fbdepth) - 1) & 0x3], 152 (unsigned)chip->vc_fbpaddr, 153 (unsigned)(chip->vc_fbpaddr + chip->vc_fbsize)); 154 155 /* don't inverse VDAT[3:0] signal */ 156 tc = chip->vc_v; 157 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 158 val &= ~TX3912_VIDEOCTRL1_INVVID; 159 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 160 161 /* install default CLUT */ 162 tx3912video_clut_init(sc); 163 164 /* if serial console, power off video module */ 165 tx3912video_power(sc, 0, 0, (void *) 166 (console ? PWR_RESUME : PWR_SUSPEND)); 167 168 /* Add a hard power hook to power saving */ 169 sc->sc_powerhook = config_hook(CONFIG_HOOK_PMEVENT, 170 CONFIG_HOOK_PMEVENT_HARDPOWER, 171 CONFIG_HOOK_SHARE, 172 tx3912video_power, sc); 173 if (sc->sc_powerhook == 0) 174 printf("WARNING unable to establish hard power hook"); 175 176 #ifdef TX3912VIDEO_DEBUG 177 /* attach debug draw routine (debugging use) */ 178 video_attach_drawfunc(sc->sc_chip); 179 tx_conf_register_video(tc, sc->sc_chip); 180 #endif 181 182 /* Attach frame buffer device */ 183 tx3912video_hpcfbinit(sc); 184 185 if (console && hpcfb_cnattach(&sc->sc_fbconf) != 0) { 186 panic("tx3912video_attach: can't init fb console"); 187 } 188 189 ha.ha_console = console; 190 ha.ha_accessops = &tx3912video_ha; 191 ha.ha_accessctx = sc; 192 ha.ha_curfbconf = 0; 193 ha.ha_nfbconf = 1; 194 ha.ha_fbconflist = &sc->sc_fbconf; 195 ha.ha_curdspconf = 0; 196 ha.ha_ndspconf = 1; 197 ha.ha_dspconflist = &sc->sc_dspconf; 198 199 config_found(self, &ha, hpcfbprint); 200 } 201 202 int 203 tx3912video_power(void *ctx, int type, long id, void *msg) 204 { 205 struct tx3912video_softc *sc = ctx; 206 struct video_chip *chip = sc->sc_chip; 207 tx_chipset_tag_t tc = chip->vc_v; 208 int why = (int)msg; 209 txreg_t val; 210 211 switch (why) { 212 case PWR_RESUME: 213 if (!sc->sc_console) 214 return 0; /* serial console */ 215 216 DPRINTF(("%s: ON\n", sc->sc_dev.dv_xname)); 217 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 218 val |= (TX3912_VIDEOCTRL1_DISPON | TX3912_VIDEOCTRL1_ENVID); 219 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 220 break; 221 case PWR_SUSPEND: 222 /* FALLTHROUGH */ 223 case PWR_STANDBY: 224 DPRINTF(("%s: OFF\n", sc->sc_dev.dv_xname)); 225 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 226 val &= ~(TX3912_VIDEOCTRL1_DISPON | TX3912_VIDEOCTRL1_ENVID); 227 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 228 break; 229 } 230 231 return 0; 232 } 233 234 void 235 tx3912video_hpcfbinit(sc) 236 struct tx3912video_softc *sc; 237 { 238 struct video_chip *chip = sc->sc_chip; 239 struct hpcfb_fbconf *fb = &sc->sc_fbconf; 240 vaddr_t fbvaddr = (vaddr_t)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 241 242 memset(fb, 0, sizeof(struct hpcfb_fbconf)); 243 244 fb->hf_conf_index = 0; /* configuration index */ 245 fb->hf_nconfs = 1; /* how many configurations */ 246 strncpy(fb->hf_name, "TX3912 built-in video", HPCFB_MAXNAMELEN); 247 /* frame buffer name */ 248 strncpy(fb->hf_conf_name, "LCD", HPCFB_MAXNAMELEN); 249 /* configuration name */ 250 fb->hf_height = chip->vc_fbheight; 251 fb->hf_width = chip->vc_fbwidth; 252 fb->hf_baseaddr = mips_ptob(mips_btop(fbvaddr)); 253 fb->hf_offset = (u_long)fbvaddr - fb->hf_baseaddr; 254 /* frame buffer start offset */ 255 fb->hf_bytes_per_line = (chip->vc_fbwidth * chip->vc_fbdepth) 256 / NBBY; 257 fb->hf_nplanes = 1; 258 fb->hf_bytes_per_plane = chip->vc_fbheight * fb->hf_bytes_per_line; 259 260 fb->hf_access_flags |= HPCFB_ACCESS_BYTE; 261 fb->hf_access_flags |= HPCFB_ACCESS_WORD; 262 fb->hf_access_flags |= HPCFB_ACCESS_DWORD; 263 if (video_reverse_color()) 264 fb->hf_access_flags |= HPCFB_ACCESS_REVERSE; 265 266 267 switch (chip->vc_fbdepth) { 268 default: 269 panic("tx3912video_hpcfbinit: not supported color depth\n"); 270 /* NOTREACHED */ 271 case 2: 272 fb->hf_class = HPCFB_CLASS_GRAYSCALE; 273 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 274 fb->hf_pack_width = 8; 275 fb->hf_pixels_per_pack = 4; 276 fb->hf_pixel_width = 2; 277 fb->hf_class_data_length = sizeof(struct hf_gray_tag); 278 /* reserved for future use */ 279 fb->hf_u.hf_gray.hf_flags = 0; 280 break; 281 case 8: 282 fb->hf_class = HPCFB_CLASS_INDEXCOLOR; 283 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 284 fb->hf_pack_width = 8; 285 fb->hf_pixels_per_pack = 1; 286 fb->hf_pixel_width = 8; 287 fb->hf_class_data_length = sizeof(struct hf_indexed_tag); 288 /* reserved for future use */ 289 fb->hf_u.hf_indexed.hf_flags = 0; 290 break; 291 } 292 } 293 294 int 295 tx3912video_init(paddr_t fb_start, paddr_t *fb_end) 296 { 297 struct video_chip *chip = &tx3912video_chip; 298 tx_chipset_tag_t tc; 299 txreg_t reg; 300 int fbdepth, reverse, error; 301 302 reverse = video_reverse_color(); 303 chip->vc_v = tc = tx_conf_get_tag(); 304 305 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 306 fbdepth = 1 << (TX3912_VIDEOCTRL1_BITSEL(reg)); 307 308 switch (fbdepth) { 309 case 2: 310 bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; 311 break; 312 case 4: 313 /* XXX should implement rasops4.c */ 314 fbdepth = 2; 315 bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; 316 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 317 TX3912_VIDEOCTRL1_BITSEL_CLR(reg); 318 reg = TX3912_VIDEOCTRL1_BITSEL_SET( 319 reg, TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE); 320 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 321 break; 322 case 8: 323 bootinfo->fb_type = reverse ? BIFB_D8_FF : BIFB_D8_00; 324 break; 325 } 326 327 chip->vc_fbdepth = fbdepth; 328 chip->vc_fbwidth = bootinfo->fb_width; 329 chip->vc_fbheight= bootinfo->fb_height; 330 331 /* Allocate framebuffer area */ 332 error = tx3912video_framebuffer_alloc(chip, fb_start, fb_end); 333 if (error != 0) 334 return (1); 335 336 #if notyet 337 tx3912video_resolution_init(chip); 338 #else 339 /* Use Windows CE setting. */ 340 #endif 341 /* Set DMA transfer address to VID module */ 342 tx3912video_framebuffer_init(chip); 343 344 /* Syncronize framebuffer addr to frame signal */ 345 tx3912video_reset(chip); 346 347 bootinfo->fb_line_bytes = (chip->vc_fbwidth * fbdepth) / NBBY; 348 bootinfo->fb_addr = (void *)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 349 350 return (0); 351 } 352 353 int 354 tx3912video_framebuffer_alloc(struct video_chip *chip, paddr_t fb_start, 355 paddr_t *fb_end /* buffer allocation hint */) 356 { 357 struct extent_fixed ex_fixed[10]; 358 struct extent *ex; 359 u_long addr, size; 360 int error; 361 362 /* calcurate frame buffer size */ 363 size = (chip->vc_fbwidth * chip->vc_fbheight * chip->vc_fbdepth) / 364 NBBY; 365 366 /* extent V-RAM region */ 367 ex = extent_create("Frame buffer address", fb_start, *fb_end, 368 0, (caddr_t)ex_fixed, sizeof ex_fixed, 369 EX_NOWAIT); 370 if (ex == 0) 371 return (1); 372 373 /* Allocate V-RAM area */ 374 error = extent_alloc_subregion(ex, fb_start, fb_start + size - 1, 375 size, TX3912_FRAMEBUFFER_ALIGNMENT, 376 TX3912_FRAMEBUFFER_BOUNDARY, 377 EX_FAST|EX_NOWAIT, &addr); 378 extent_destroy(ex); 379 380 if (error != 0) { 381 return (1); 382 } 383 384 chip->vc_fbpaddr = addr; 385 chip->vc_fbvaddr = MIPS_PHYS_TO_KSEG1(addr); 386 chip->vc_fbsize = size; 387 388 *fb_end = addr + size; 389 390 return (0); 391 } 392 393 void 394 tx3912video_framebuffer_init(struct video_chip *chip) 395 { 396 u_int32_t fb_addr, fb_size, vaddr, bank, base; 397 txreg_t reg; 398 tx_chipset_tag_t tc = chip->vc_v; 399 400 fb_addr = chip->vc_fbpaddr; 401 fb_size = chip->vc_fbsize; 402 403 /* XXX currently I don't set DFVAL, so force DF signal toggled on 404 * XXX each frame. */ 405 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 406 reg &= ~TX3912_VIDEOCTRL1_DFMODE; 407 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 408 409 /* Set DMA transfer start and end address */ 410 411 bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr); 412 base = TX3912_VIDEOCTRL3_VIDBASEHI(fb_addr); 413 reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank); 414 /* Upper address counter */ 415 reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base); 416 tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg); 417 418 /* Lower address counter */ 419 base = TX3912_VIDEOCTRL4_VIDBASELO(fb_addr + fb_size); 420 reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base); 421 422 /* Set DF-signal rate */ 423 reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/ 424 425 /* Set VIDDONE signal delay after FRAME signal */ 426 /* XXX not yet*/ 427 tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg); 428 429 /* Clear frame buffer */ 430 vaddr = MIPS_PHYS_TO_KSEG1(fb_addr); 431 memset((void*)vaddr, 0, fb_size); 432 } 433 434 void 435 tx3912video_resolution_init(struct video_chip *chip) 436 { 437 int h, v, split, bit8, horzval, lineval; 438 tx_chipset_tag_t tc = chip->vc_v; 439 txreg_t reg; 440 u_int32_t val; 441 442 h = chip->vc_fbwidth; 443 v = chip->vc_fbheight; 444 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 445 split = reg & TX3912_VIDEOCTRL1_DISPSPLIT; 446 bit8 = (TX3912_VIDEOCTRL1_BITSEL(reg) == 447 TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR); 448 val = TX3912_VIDEOCTRL1_BITSEL(reg); 449 450 if ((val == TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR) && 451 !split) { 452 /* (LCD horizontal pixels / 8bit) * RGB - 1 */ 453 horzval = (h / 8) * 3 - 1; 454 } else { 455 horzval = h / 4 - 1; 456 } 457 lineval = (split ? v / 2 : v) - 1; 458 459 /* Video rate */ 460 /* XXX 461 * probably This value should be determined from DFINT and LCDINT 462 */ 463 reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1); 464 /* Horizontal size of LCD */ 465 reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval); 466 /* # of lines for the LCD */ 467 reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval); 468 469 tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg); 470 } 471 472 void 473 tx3912video_reset(struct video_chip *chip) 474 { 475 tx_chipset_tag_t tc = chip->vc_v; 476 txreg_t reg; 477 478 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 479 480 /* Disable video logic at end of this frame */ 481 reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME; 482 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 483 484 /* Wait for end of frame */ 485 delay(30 * 1000); 486 487 /* Make sure to disable video logic */ 488 reg &= ~TX3912_VIDEOCTRL1_ENVID; 489 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 490 491 delay(1000); 492 493 /* Enable video logic again */ 494 reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME; 495 reg |= TX3912_VIDEOCTRL1_ENVID; 496 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 497 498 delay(1000); 499 } 500 501 int 502 tx3912video_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 503 { 504 struct tx3912video_softc *sc = (struct tx3912video_softc *)v; 505 struct hpcfb_fbconf *fbconf; 506 struct hpcfb_dspconf *dspconf; 507 struct wsdisplay_cmap *cmap; 508 u_int8_t *r, *g, *b; 509 u_int32_t *rgb; 510 int idx, cnt, error; 511 512 switch (cmd) { 513 case WSDISPLAYIO_GETCMAP: 514 cmap = (struct wsdisplay_cmap*)data; 515 cnt = cmap->count; 516 idx = cmap->index; 517 518 if (sc->sc_fbconf.hf_class != HPCFB_CLASS_INDEXCOLOR || 519 sc->sc_fbconf.hf_pack_width != 8 || 520 !LEGAL_CLUT_INDEX(idx) || 521 !LEGAL_CLUT_INDEX(idx + cnt -1)) { 522 return (EINVAL); 523 } 524 525 if (!uvm_useracc(cmap->red, cnt, B_WRITE) || 526 !uvm_useracc(cmap->green, cnt, B_WRITE) || 527 !uvm_useracc(cmap->blue, cnt, B_WRITE)) { 528 return (EFAULT); 529 } 530 531 error = cmap_work_alloc(&r, &g, &b, &rgb, cnt); 532 if (error != 0) { 533 cmap_work_free(r, g, b, rgb); 534 return (ENOMEM); 535 } 536 tx3912video_clut_get(sc, rgb, idx, cnt); 537 rgb24_decompose(rgb, r, g, b, cnt); 538 539 copyout(r, cmap->red, cnt); 540 copyout(g, cmap->green,cnt); 541 copyout(b, cmap->blue, cnt); 542 543 cmap_work_free(r, g, b, rgb); 544 545 return (0); 546 547 case WSDISPLAYIO_PUTCMAP: 548 /* 549 * TX3912 can't change CLUT index. R:G:B = 3:3:2 550 */ 551 return (0); 552 553 case HPCFBIO_GCONF: 554 fbconf = (struct hpcfb_fbconf *)data; 555 if (fbconf->hf_conf_index != 0 && 556 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 557 return (EINVAL); 558 } 559 *fbconf = sc->sc_fbconf; /* structure assignment */ 560 return (0); 561 562 case HPCFBIO_SCONF: 563 fbconf = (struct hpcfb_fbconf *)data; 564 if (fbconf->hf_conf_index != 0 && 565 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 566 return (EINVAL); 567 } 568 /* 569 * nothing to do because we have only one configration 570 */ 571 return (0); 572 573 case HPCFBIO_GDSPCONF: 574 dspconf = (struct hpcfb_dspconf *)data; 575 if ((dspconf->hd_unit_index != 0 && 576 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 577 (dspconf->hd_conf_index != 0 && 578 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 579 return (EINVAL); 580 } 581 *dspconf = sc->sc_dspconf; /* structure assignment */ 582 return (0); 583 584 case HPCFBIO_SDSPCONF: 585 dspconf = (struct hpcfb_dspconf *)data; 586 if ((dspconf->hd_unit_index != 0 && 587 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 588 (dspconf->hd_conf_index != 0 && 589 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 590 return (EINVAL); 591 } 592 /* 593 * nothing to do 594 * because we have only one unit and one configration 595 */ 596 return (0); 597 598 case HPCFBIO_GOP: 599 case HPCFBIO_SOP: 600 /* XXX not implemented yet */ 601 return (EINVAL); 602 } 603 604 return (ENOTTY); 605 } 606 607 paddr_t 608 tx3912video_mmap(void *ctx, off_t offset, int prot) 609 { 610 struct tx3912video_softc *sc = (struct tx3912video_softc *)ctx; 611 612 if (offset < 0 || (sc->sc_fbconf.hf_bytes_per_plane + 613 sc->sc_fbconf.hf_offset) < offset) { 614 return (-1); 615 } 616 617 return (mips_btop(sc->sc_chip->vc_fbpaddr + offset)); 618 } 619 620 /* 621 * CLUT staff 622 */ 623 static const struct { 624 int mul, div; 625 } dither_list [] = { 626 [TX3912_VIDEO_DITHER_DUTYCYCLE_1] = { 1, 1 }, 627 [TX3912_VIDEO_DITHER_DUTYCYCLE_6_7] = { 6, 7 }, 628 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_5] = { 4, 5 }, 629 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_4] = { 3, 4 }, 630 [TX3912_VIDEO_DITHER_DUTYCYCLE_5_7] = { 5, 7 }, 631 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_3] = { 2, 3 }, 632 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_5] = { 3, 5 }, 633 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_7] = { 4, 7 }, 634 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_4] = { 2, 4 }, 635 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_7] = { 3, 7 }, 636 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_5] = { 2, 5 }, 637 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_3] = { 1, 3 }, 638 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_7] = { 2, 7 }, 639 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_5] = { 1, 5 }, 640 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_7] = { 1, 7 }, 641 [TX3912_VIDEO_DITHER_DUTYCYCLE_0] = { 0, 1 } 642 }, *dlp; 643 644 static const int dither_level8[8] = { 645 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 646 TX3912_VIDEO_DITHER_DUTYCYCLE_2_7, 647 TX3912_VIDEO_DITHER_DUTYCYCLE_2_5, 648 TX3912_VIDEO_DITHER_DUTYCYCLE_2_4, 649 TX3912_VIDEO_DITHER_DUTYCYCLE_3_5, 650 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 651 TX3912_VIDEO_DITHER_DUTYCYCLE_4_5, 652 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 653 }; 654 655 static const int dither_level4[4] = { 656 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 657 TX3912_VIDEO_DITHER_DUTYCYCLE_1_3, 658 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 659 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 660 }; 661 662 static int 663 __get_color8(int luti) 664 { 665 KASSERT(luti >=0 && luti < 8); 666 dlp = &dither_list[dither_level8[luti]]; 667 668 return ((0xff * dlp->mul) / dlp->div); 669 } 670 671 static int 672 __get_color4(int luti) 673 { 674 KASSERT(luti >=0 && luti < 4); 675 dlp = &dither_list[dither_level4[luti]]; 676 677 return ((0xff * dlp->mul) / dlp->div); 678 } 679 680 void 681 tx3912video_clut_get(struct tx3912video_softc *sc, u_int32_t *rgb, int beg, 682 int cnt) 683 { 684 int i; 685 686 KASSERT(rgb); 687 KASSERT(LEGAL_CLUT_INDEX(beg)); 688 KASSERT(LEGAL_CLUT_INDEX(beg + cnt - 1)); 689 690 for (i = beg; i < beg + cnt; i++) { 691 *rgb++ = RGB24(__get_color8((i >> 5) & 0x7), 692 __get_color8((i >> 2) & 0x7), 693 __get_color4(i & 0x3)); 694 } 695 } 696 697 void 698 tx3912video_clut_install(void *ctx, struct rasops_info *ri) 699 { 700 struct tx3912video_softc *sc = ctx; 701 const int system_cmap[0x10] = { 702 TX3912VIDEO_BLACK, 703 TX3912VIDEO_RED, 704 TX3912VIDEO_GREEN, 705 TX3912VIDEO_YELLOW, 706 TX3912VIDEO_BLUE, 707 TX3912VIDEO_MAGENTA, 708 TX3912VIDEO_CYAN, 709 TX3912VIDEO_WHITE, 710 TX3912VIDEO_DARK_BLACK, 711 TX3912VIDEO_DARK_RED, 712 TX3912VIDEO_DARK_GREEN, 713 TX3912VIDEO_DARK_YELLOW, 714 TX3912VIDEO_DARK_BLUE, 715 TX3912VIDEO_DARK_MAGENTA, 716 TX3912VIDEO_DARK_CYAN, 717 TX3912VIDEO_DARK_WHITE, 718 }; 719 720 KASSERT(ri); 721 722 if (sc->sc_chip->vc_fbdepth == 8) { 723 /* XXX 2bit gray scale LUT not supported */ 724 memcpy(ri->ri_devcmap, system_cmap, sizeof system_cmap); 725 } 726 } 727 728 void 729 tx3912video_clut_init(struct tx3912video_softc *sc) 730 { 731 tx_chipset_tag_t tc = sc->sc_chip->vc_v; 732 733 if (sc->sc_chip->vc_fbdepth != 8) { 734 return; /* XXX 2bit gray scale LUT not supported */ 735 } 736 737 /* 738 * time-based dithering pattern (TOSHIBA recommended pattern) 739 */ 740 /* 2/3, 1/3 */ 741 tx_conf_write(tc, TX3912_VIDEOCTRL8_REG, 742 TX3912_VIDEOCTRL8_PAT2_3_DEFAULT); 743 /* 3/4, 2/4 */ 744 tx_conf_write(tc, TX3912_VIDEOCTRL9_REG, 745 (TX3912_VIDEOCTRL9_PAT3_4_DEFAULT << 16) | 746 TX3912_VIDEOCTRL9_PAT2_4_DEFAULT); 747 /* 4/5, 1/5 */ 748 tx_conf_write(tc, TX3912_VIDEOCTRL10_REG, 749 TX3912_VIDEOCTRL10_PAT4_5_DEFAULT); 750 /* 3/5, 2/5 */ 751 tx_conf_write(tc, TX3912_VIDEOCTRL11_REG, 752 TX3912_VIDEOCTRL11_PAT3_5_DEFAULT); 753 /* 6/7, 1/7 */ 754 tx_conf_write(tc, TX3912_VIDEOCTRL12_REG, 755 TX3912_VIDEOCTRL12_PAT6_7_DEFAULT); 756 /* 5/7, 2/7 */ 757 tx_conf_write(tc, TX3912_VIDEOCTRL13_REG, 758 TX3912_VIDEOCTRL13_PAT5_7_DEFAULT); 759 /* 4/7, 3/7 */ 760 tx_conf_write(tc, TX3912_VIDEOCTRL14_REG, 761 TX3912_VIDEOCTRL14_PAT4_7_DEFAULT); 762 763 /* 764 * dither-pattern look-up table. (selected by uch) 765 */ 766 /* red */ 767 tx_conf_write(tc, TX3912_VIDEOCTRL5_REG, 768 (dither_level8[7] << 28) | 769 (dither_level8[6] << 24) | 770 (dither_level8[5] << 20) | 771 (dither_level8[4] << 16) | 772 (dither_level8[3] << 12) | 773 (dither_level8[2] << 8) | 774 (dither_level8[1] << 4) | 775 (dither_level8[0] << 0)); 776 /* green */ 777 tx_conf_write(tc, TX3912_VIDEOCTRL6_REG, 778 (dither_level8[7] << 28) | 779 (dither_level8[6] << 24) | 780 (dither_level8[5] << 20) | 781 (dither_level8[4] << 16) | 782 (dither_level8[3] << 12) | 783 (dither_level8[2] << 8) | 784 (dither_level8[1] << 4) | 785 (dither_level8[0] << 0)); 786 /* blue (2bit gray scale also use this look-up table) */ 787 tx_conf_write(tc, TX3912_VIDEOCTRL7_REG, 788 (dither_level4[3] << 12) | 789 (dither_level4[2] << 8) | 790 (dither_level4[1] << 4) | 791 (dither_level4[0] << 0)); 792 793 tx3912video_reset(sc->sc_chip); 794 } 795
Indexes created Fri Oct 31 11:10:07 GMT 2025