tx3912video.c revision 1.22.2.1
1 /* $NetBSD: tx3912video.c,v 1.22.2.1 2001/06/21 19:24:23 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #define TX3912VIDEO_DEBUG 40 41 #include "opt_tx39_debug.h" 42 #include "hpcfb.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/extent.h> 48 49 #include <sys/ioctl.h> 50 #include <sys/buf.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <dev/cons.h> /* consdev */ 55 56 #include <machine/bus.h> 57 #include <machine/bootinfo.h> 58 #include <machine/config_hook.h> 59 60 #include <hpcmips/tx/tx39var.h> 61 #include <hpcmips/tx/tx3912videovar.h> 62 #include <hpcmips/tx/tx3912videoreg.h> 63 64 /* CLUT */ 65 #include <dev/wscons/wsdisplayvar.h> 66 #include <dev/rasops/rasops.h> 67 #include <dev/hpc/video_subr.h> 68 69 #include <dev/wscons/wsconsio.h> 70 #include <dev/hpc/hpcfbvar.h> 71 #include <dev/hpc/hpcfbio.h> 72 73 #ifdef TX3912VIDEO_DEBUG 74 int tx3912video_debug = 1; 75 #define DPRINTF(arg) if (tx3912video_debug) printf arg; 76 #define DPRINTFN(n, arg) if (tx3912video_debug > (n)) printf arg; 77 #else 78 #define DPRINTF(arg) 79 #define DPRINTFN(n, arg) 80 #endif 81 82 struct tx3912video_softc { 83 struct device sc_dev; 84 void *sc_powerhook; /* power management hook */ 85 int sc_console; 86 struct hpcfb_fbconf sc_fbconf; 87 struct hpcfb_dspconf sc_dspconf; 88 struct video_chip *sc_chip; 89 }; 90 91 /* TX3912 built-in video chip itself */ 92 static struct video_chip tx3912video_chip; 93 94 int tx3912video_power(void *, int, long, void *); 95 void tx3912video_framebuffer_init(struct video_chip *); 96 int tx3912video_framebuffer_alloc(struct video_chip *, paddr_t, paddr_t *); 97 void tx3912video_reset(struct video_chip *); 98 void tx3912video_resolution_init(struct video_chip *); 99 int tx3912video_match(struct device *, struct cfdata *, void *); 100 void tx3912video_attach(struct device *, struct device *, void *); 101 int tx3912video_print(void *, const char *); 102 103 void tx3912video_hpcfbinit(struct tx3912video_softc *); 104 int tx3912video_ioctl(void *, u_long, caddr_t, int, struct proc *); 105 paddr_t tx3912video_mmap(void *, off_t, int); 106 107 void tx3912video_clut_init(struct tx3912video_softc *); 108 void tx3912video_clut_install(void *, struct rasops_info *); 109 void tx3912video_clut_get(struct tx3912video_softc *, u_int32_t *, int, 110 int); 111 112 static int __get_color8(int); 113 static int __get_color4(int); 114 115 struct cfattach tx3912video_ca = { 116 sizeof(struct tx3912video_softc), tx3912video_match, 117 tx3912video_attach 118 }; 119 120 struct hpcfb_accessops tx3912video_ha = { 121 tx3912video_ioctl, tx3912video_mmap, 0, 0, 0, 0, 122 tx3912video_clut_install 123 }; 124 125 int 126 tx3912video_match(struct device *parent, struct cfdata *cf, void *aux) 127 { 128 return (ATTACH_NORMAL); 129 } 130 131 void 132 tx3912video_attach(struct device *parent, struct device *self, void *aux) 133 { 134 struct tx3912video_softc *sc = (void *)self; 135 struct video_chip *chip; 136 const char *depth_print[] = { 137 [TX3912_VIDEOCTRL1_BITSEL_MONOCHROME] = "monochrome", 138 [TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE] = "2bit greyscale", 139 [TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE] = "4bit greyscale", 140 [TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR] = "8bit color" 141 }; 142 struct hpcfb_attach_args ha; 143 tx_chipset_tag_t tc; 144 txreg_t val; 145 int console; 146 147 sc->sc_console = console = cn_tab ? 0 : 1; 148 sc->sc_chip = chip = &tx3912video_chip; 149 150 /* print video module information */ 151 printf(": %s, frame buffer 0x%08x-0x%08x\n", 152 depth_print[(ffs(chip->vc_fbdepth) - 1) & 0x3], 153 (unsigned)chip->vc_fbpaddr, 154 (unsigned)(chip->vc_fbpaddr + chip->vc_fbsize)); 155 156 /* don't inverse VDAT[3:0] signal */ 157 tc = chip->vc_v; 158 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 159 val &= ~TX3912_VIDEOCTRL1_INVVID; 160 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 161 162 /* install default CLUT */ 163 tx3912video_clut_init(sc); 164 165 /* if serial console, power off video module */ 166 tx3912video_power(sc, 0, 0, (void *) 167 (console ? PWR_RESUME : PWR_SUSPEND)); 168 169 /* Add a hard power hook to power saving */ 170 sc->sc_powerhook = config_hook(CONFIG_HOOK_PMEVENT, 171 CONFIG_HOOK_PMEVENT_HARDPOWER, CONFIG_HOOK_SHARE, 172 tx3912video_power, sc); 173 if (sc->sc_powerhook == 0) 174 printf("WARNING unable to establish hard power hook"); 175 176 #ifdef TX3912VIDEO_DEBUG 177 /* attach debug draw routine (debugging use) */ 178 video_attach_drawfunc(sc->sc_chip); 179 tx_conf_register_video(tc, sc->sc_chip); 180 #endif 181 182 /* Attach frame buffer device */ 183 tx3912video_hpcfbinit(sc); 184 185 if (console && hpcfb_cnattach(&sc->sc_fbconf) != 0) { 186 panic("tx3912video_attach: can't init fb console"); 187 } 188 189 ha.ha_console = console; 190 ha.ha_accessops = &tx3912video_ha; 191 ha.ha_accessctx = sc; 192 ha.ha_curfbconf = 0; 193 ha.ha_nfbconf = 1; 194 ha.ha_fbconflist = &sc->sc_fbconf; 195 ha.ha_curdspconf = 0; 196 ha.ha_ndspconf = 1; 197 ha.ha_dspconflist = &sc->sc_dspconf; 198 199 config_found(self, &ha, hpcfbprint); 200 } 201 202 int 203 tx3912video_power(void *ctx, int type, long id, void *msg) 204 { 205 struct tx3912video_softc *sc = ctx; 206 struct video_chip *chip = sc->sc_chip; 207 tx_chipset_tag_t tc = chip->vc_v; 208 int why = (int)msg; 209 txreg_t val; 210 211 switch (why) { 212 case PWR_RESUME: 213 if (!sc->sc_console) 214 return (0); /* serial console */ 215 216 DPRINTF(("%s: ON\n", sc->sc_dev.dv_xname)); 217 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 218 val |= (TX3912_VIDEOCTRL1_DISPON | TX3912_VIDEOCTRL1_ENVID); 219 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 220 break; 221 case PWR_SUSPEND: 222 /* FALLTHROUGH */ 223 case PWR_STANDBY: 224 DPRINTF(("%s: OFF\n", sc->sc_dev.dv_xname)); 225 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 226 val &= ~(TX3912_VIDEOCTRL1_DISPON | TX3912_VIDEOCTRL1_ENVID); 227 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 228 break; 229 } 230 231 return (0); 232 } 233 234 void 235 tx3912video_hpcfbinit(sc) 236 struct tx3912video_softc *sc; 237 { 238 struct video_chip *chip = sc->sc_chip; 239 struct hpcfb_fbconf *fb = &sc->sc_fbconf; 240 vaddr_t fbvaddr = (vaddr_t)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 241 242 memset(fb, 0, sizeof(struct hpcfb_fbconf)); 243 244 fb->hf_conf_index = 0; /* configuration index */ 245 fb->hf_nconfs = 1; /* how many configurations */ 246 strncpy(fb->hf_name, "TX3912 built-in video", HPCFB_MAXNAMELEN); 247 /* frame buffer name */ 248 strncpy(fb->hf_conf_name, "LCD", HPCFB_MAXNAMELEN); 249 /* configuration name */ 250 fb->hf_height = chip->vc_fbheight; 251 fb->hf_width = chip->vc_fbwidth; 252 fb->hf_baseaddr = (u_long)fbvaddr; 253 fb->hf_offset = (u_long)fbvaddr - 254 mips_ptob(mips_btop(fbvaddr)); 255 /* frame buffer start offset */ 256 fb->hf_bytes_per_line = (chip->vc_fbwidth * chip->vc_fbdepth) 257 / NBBY; 258 fb->hf_nplanes = 1; 259 fb->hf_bytes_per_plane = chip->vc_fbheight * fb->hf_bytes_per_line; 260 261 fb->hf_access_flags |= HPCFB_ACCESS_BYTE; 262 fb->hf_access_flags |= HPCFB_ACCESS_WORD; 263 fb->hf_access_flags |= HPCFB_ACCESS_DWORD; 264 if (video_reverse_color()) 265 fb->hf_access_flags |= HPCFB_ACCESS_REVERSE; 266 267 268 switch (chip->vc_fbdepth) { 269 default: 270 panic("tx3912video_hpcfbinit: not supported color depth\n"); 271 /* NOTREACHED */ 272 case 2: 273 fb->hf_class = HPCFB_CLASS_GRAYSCALE; 274 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 275 fb->hf_pack_width = 8; 276 fb->hf_pixels_per_pack = 4; 277 fb->hf_pixel_width = 2; 278 fb->hf_class_data_length = sizeof(struct hf_gray_tag); 279 /* reserved for future use */ 280 fb->hf_u.hf_gray.hf_flags = 0; 281 break; 282 case 8: 283 fb->hf_class = HPCFB_CLASS_INDEXCOLOR; 284 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 285 fb->hf_pack_width = 8; 286 fb->hf_pixels_per_pack = 1; 287 fb->hf_pixel_width = 8; 288 fb->hf_class_data_length = sizeof(struct hf_indexed_tag); 289 /* reserved for future use */ 290 fb->hf_u.hf_indexed.hf_flags = 0; 291 break; 292 } 293 } 294 295 int 296 tx3912video_init(paddr_t fb_start, paddr_t *fb_end) 297 { 298 struct video_chip *chip = &tx3912video_chip; 299 tx_chipset_tag_t tc; 300 txreg_t reg; 301 int fbdepth, reverse, error; 302 303 reverse = video_reverse_color(); 304 chip->vc_v = tc = tx_conf_get_tag(); 305 306 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 307 fbdepth = 1 << (TX3912_VIDEOCTRL1_BITSEL(reg)); 308 309 switch (fbdepth) { 310 case 2: 311 bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; 312 break; 313 case 4: 314 /* XXX should implement rasops4.c */ 315 fbdepth = 2; 316 bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; 317 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 318 TX3912_VIDEOCTRL1_BITSEL_CLR(reg); 319 reg = TX3912_VIDEOCTRL1_BITSEL_SET(reg, 320 TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE); 321 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 322 break; 323 case 8: 324 bootinfo->fb_type = reverse ? BIFB_D8_FF : BIFB_D8_00; 325 break; 326 } 327 328 chip->vc_fbdepth = fbdepth; 329 chip->vc_fbwidth = bootinfo->fb_width; 330 chip->vc_fbheight= bootinfo->fb_height; 331 332 /* Allocate framebuffer area */ 333 error = tx3912video_framebuffer_alloc(chip, fb_start, fb_end); 334 if (error != 0) 335 return (1); 336 337 #if notyet 338 tx3912video_resolution_init(chip); 339 #else 340 /* Use Windows CE setting. */ 341 #endif 342 /* Set DMA transfer address to VID module */ 343 tx3912video_framebuffer_init(chip); 344 345 /* Syncronize framebuffer addr to frame signal */ 346 tx3912video_reset(chip); 347 348 bootinfo->fb_line_bytes = (chip->vc_fbwidth * fbdepth) / NBBY; 349 bootinfo->fb_addr = (void *)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 350 351 return (0); 352 } 353 354 int 355 tx3912video_framebuffer_alloc(struct video_chip *chip, paddr_t fb_start, 356 paddr_t *fb_end /* buffer allocation hint */) 357 { 358 struct extent_fixed ex_fixed[10]; 359 struct extent *ex; 360 u_long addr, size; 361 int error; 362 363 /* calcurate frame buffer size */ 364 size = (chip->vc_fbwidth * chip->vc_fbheight * chip->vc_fbdepth) / 365 NBBY; 366 367 /* extent V-RAM region */ 368 ex = extent_create("Frame buffer address", fb_start, *fb_end, 369 0, (caddr_t)ex_fixed, sizeof ex_fixed, 370 EX_NOWAIT); 371 if (ex == 0) 372 return (1); 373 374 /* Allocate V-RAM area */ 375 error = extent_alloc_subregion(ex, fb_start, fb_start + size - 1, 376 size, TX3912_FRAMEBUFFER_ALIGNMENT, 377 TX3912_FRAMEBUFFER_BOUNDARY, EX_FAST|EX_NOWAIT, &addr); 378 extent_destroy(ex); 379 380 if (error != 0) 381 return (1); 382 383 chip->vc_fbpaddr = addr; 384 chip->vc_fbvaddr = MIPS_PHYS_TO_KSEG1(addr); 385 chip->vc_fbsize = size; 386 387 *fb_end = addr + size; 388 389 return (0); 390 } 391 392 void 393 tx3912video_framebuffer_init(struct video_chip *chip) 394 { 395 u_int32_t fb_addr, fb_size, vaddr, bank, base; 396 txreg_t reg; 397 tx_chipset_tag_t tc = chip->vc_v; 398 399 fb_addr = chip->vc_fbpaddr; 400 fb_size = chip->vc_fbsize; 401 402 /* XXX currently I don't set DFVAL, so force DF signal toggled on 403 * XXX each frame. */ 404 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 405 reg &= ~TX3912_VIDEOCTRL1_DFMODE; 406 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 407 408 /* Set DMA transfer start and end address */ 409 410 bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr); 411 base = TX3912_VIDEOCTRL3_VIDBASEHI(fb_addr); 412 reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank); 413 /* Upper address counter */ 414 reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base); 415 tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg); 416 417 /* Lower address counter */ 418 base = TX3912_VIDEOCTRL4_VIDBASELO(fb_addr + fb_size); 419 reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base); 420 421 /* Set DF-signal rate */ 422 reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/ 423 424 /* Set VIDDONE signal delay after FRAME signal */ 425 /* XXX not yet*/ 426 tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg); 427 428 /* Clear frame buffer */ 429 vaddr = MIPS_PHYS_TO_KSEG1(fb_addr); 430 memset((void*)vaddr, 0, fb_size); 431 } 432 433 void 434 tx3912video_resolution_init(struct video_chip *chip) 435 { 436 int h, v, split, bit8, horzval, lineval; 437 tx_chipset_tag_t tc = chip->vc_v; 438 txreg_t reg; 439 u_int32_t val; 440 441 h = chip->vc_fbwidth; 442 v = chip->vc_fbheight; 443 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 444 split = reg & TX3912_VIDEOCTRL1_DISPSPLIT; 445 bit8 = (TX3912_VIDEOCTRL1_BITSEL(reg) == 446 TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR); 447 val = TX3912_VIDEOCTRL1_BITSEL(reg); 448 449 if ((val == TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR) && !split) { 450 /* (LCD horizontal pixels / 8bit) * RGB - 1 */ 451 horzval = (h / 8) * 3 - 1; 452 } else { 453 horzval = h / 4 - 1; 454 } 455 lineval = (split ? v / 2 : v) - 1; 456 457 /* Video rate */ 458 /* XXX 459 * probably This value should be determined from DFINT and LCDINT 460 */ 461 reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1); 462 /* Horizontal size of LCD */ 463 reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval); 464 /* # of lines for the LCD */ 465 reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval); 466 467 tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg); 468 } 469 470 void 471 tx3912video_reset(struct video_chip *chip) 472 { 473 tx_chipset_tag_t tc = chip->vc_v; 474 txreg_t reg; 475 476 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 477 478 /* Disable video logic at end of this frame */ 479 reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME; 480 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 481 482 /* Wait for end of frame */ 483 delay(30 * 1000); 484 485 /* Make sure to disable video logic */ 486 reg &= ~TX3912_VIDEOCTRL1_ENVID; 487 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 488 489 delay(1000); 490 491 /* Enable video logic again */ 492 reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME; 493 reg |= TX3912_VIDEOCTRL1_ENVID; 494 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 495 496 delay(1000); 497 } 498 499 int 500 tx3912video_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 501 { 502 struct tx3912video_softc *sc = (struct tx3912video_softc *)v; 503 struct hpcfb_fbconf *fbconf; 504 struct hpcfb_dspconf *dspconf; 505 struct wsdisplay_cmap *cmap; 506 u_int8_t *r, *g, *b; 507 u_int32_t *rgb; 508 int idx, cnt, error; 509 510 switch (cmd) { 511 case WSDISPLAYIO_GETCMAP: 512 cmap = (struct wsdisplay_cmap*)data; 513 cnt = cmap->count; 514 idx = cmap->index; 515 516 if (sc->sc_fbconf.hf_class != HPCFB_CLASS_INDEXCOLOR || 517 sc->sc_fbconf.hf_pack_width != 8 || 518 !LEGAL_CLUT_INDEX(idx) || 519 !LEGAL_CLUT_INDEX(idx + cnt -1)) { 520 return (EINVAL); 521 } 522 523 if (!uvm_useracc(cmap->red, cnt, B_WRITE) || 524 !uvm_useracc(cmap->green, cnt, B_WRITE) || 525 !uvm_useracc(cmap->blue, cnt, B_WRITE)) { 526 return (EFAULT); 527 } 528 529 error = cmap_work_alloc(&r, &g, &b, &rgb, cnt); 530 if (error != 0) { 531 cmap_work_free(r, g, b, rgb); 532 return (ENOMEM); 533 } 534 tx3912video_clut_get(sc, rgb, idx, cnt); 535 rgb24_decompose(rgb, r, g, b, cnt); 536 537 copyout(r, cmap->red, cnt); 538 copyout(g, cmap->green,cnt); 539 copyout(b, cmap->blue, cnt); 540 541 cmap_work_free(r, g, b, rgb); 542 543 return (0); 544 545 case WSDISPLAYIO_PUTCMAP: 546 /* 547 * TX3912 can't change CLUT index. R:G:B = 3:3:2 548 */ 549 return (0); 550 551 case HPCFBIO_GCONF: 552 fbconf = (struct hpcfb_fbconf *)data; 553 if (fbconf->hf_conf_index != 0 && 554 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 555 return (EINVAL); 556 } 557 *fbconf = sc->sc_fbconf; /* structure assignment */ 558 return (0); 559 560 case HPCFBIO_SCONF: 561 fbconf = (struct hpcfb_fbconf *)data; 562 if (fbconf->hf_conf_index != 0 && 563 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 564 return (EINVAL); 565 } 566 /* 567 * nothing to do because we have only one configration 568 */ 569 return (0); 570 571 case HPCFBIO_GDSPCONF: 572 dspconf = (struct hpcfb_dspconf *)data; 573 if ((dspconf->hd_unit_index != 0 && 574 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 575 (dspconf->hd_conf_index != 0 && 576 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 577 return (EINVAL); 578 } 579 *dspconf = sc->sc_dspconf; /* structure assignment */ 580 return (0); 581 582 case HPCFBIO_SDSPCONF: 583 dspconf = (struct hpcfb_dspconf *)data; 584 if ((dspconf->hd_unit_index != 0 && 585 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 586 (dspconf->hd_conf_index != 0 && 587 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 588 return (EINVAL); 589 } 590 /* 591 * nothing to do 592 * because we have only one unit and one configration 593 */ 594 return (0); 595 596 case HPCFBIO_GOP: 597 case HPCFBIO_SOP: 598 /* XXX not implemented yet */ 599 return (EINVAL); 600 } 601 602 return (ENOTTY); 603 } 604 605 paddr_t 606 tx3912video_mmap(void *ctx, off_t offset, int prot) 607 { 608 struct tx3912video_softc *sc = (struct tx3912video_softc *)ctx; 609 610 if (offset < 0 || (sc->sc_fbconf.hf_bytes_per_plane + 611 sc->sc_fbconf.hf_offset) < offset) { 612 return (-1); 613 } 614 615 return (mips_btop(sc->sc_chip->vc_fbpaddr + offset)); 616 } 617 618 /* 619 * CLUT staff 620 */ 621 static const struct { 622 int mul, div; 623 } dither_list [] = { 624 [TX3912_VIDEO_DITHER_DUTYCYCLE_1] = { 1, 1 }, 625 [TX3912_VIDEO_DITHER_DUTYCYCLE_6_7] = { 6, 7 }, 626 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_5] = { 4, 5 }, 627 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_4] = { 3, 4 }, 628 [TX3912_VIDEO_DITHER_DUTYCYCLE_5_7] = { 5, 7 }, 629 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_3] = { 2, 3 }, 630 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_5] = { 3, 5 }, 631 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_7] = { 4, 7 }, 632 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_4] = { 2, 4 }, 633 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_7] = { 3, 7 }, 634 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_5] = { 2, 5 }, 635 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_3] = { 1, 3 }, 636 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_7] = { 2, 7 }, 637 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_5] = { 1, 5 }, 638 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_7] = { 1, 7 }, 639 [TX3912_VIDEO_DITHER_DUTYCYCLE_0] = { 0, 1 } 640 }, *dlp; 641 642 static const int dither_level8[8] = { 643 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 644 TX3912_VIDEO_DITHER_DUTYCYCLE_2_7, 645 TX3912_VIDEO_DITHER_DUTYCYCLE_2_5, 646 TX3912_VIDEO_DITHER_DUTYCYCLE_2_4, 647 TX3912_VIDEO_DITHER_DUTYCYCLE_3_5, 648 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 649 TX3912_VIDEO_DITHER_DUTYCYCLE_4_5, 650 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 651 }; 652 653 static const int dither_level4[4] = { 654 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 655 TX3912_VIDEO_DITHER_DUTYCYCLE_1_3, 656 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 657 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 658 }; 659 660 static int 661 __get_color8(int luti) 662 { 663 KASSERT(luti >=0 && luti < 8); 664 dlp = &dither_list[dither_level8[luti]]; 665 666 return ((0xff * dlp->mul) / dlp->div); 667 } 668 669 static int 670 __get_color4(int luti) 671 { 672 KASSERT(luti >=0 && luti < 4); 673 dlp = &dither_list[dither_level4[luti]]; 674 675 return ((0xff * dlp->mul) / dlp->div); 676 } 677 678 void 679 tx3912video_clut_get(struct tx3912video_softc *sc, u_int32_t *rgb, int beg, 680 int cnt) 681 { 682 int i; 683 684 KASSERT(rgb); 685 KASSERT(LEGAL_CLUT_INDEX(beg)); 686 KASSERT(LEGAL_CLUT_INDEX(beg + cnt - 1)); 687 688 for (i = beg; i < beg + cnt; i++) { 689 *rgb++ = RGB24(__get_color8((i >> 5) & 0x7), 690 __get_color8((i >> 2) & 0x7), 691 __get_color4(i & 0x3)); 692 } 693 } 694 695 void 696 tx3912video_clut_install(void *ctx, struct rasops_info *ri) 697 { 698 struct tx3912video_softc *sc = ctx; 699 const int system_cmap[0x10] = { 700 TX3912VIDEO_BLACK, 701 TX3912VIDEO_RED, 702 TX3912VIDEO_GREEN, 703 TX3912VIDEO_YELLOW, 704 TX3912VIDEO_BLUE, 705 TX3912VIDEO_MAGENTA, 706 TX3912VIDEO_CYAN, 707 TX3912VIDEO_WHITE, 708 TX3912VIDEO_DARK_BLACK, 709 TX3912VIDEO_DARK_RED, 710 TX3912VIDEO_DARK_GREEN, 711 TX3912VIDEO_DARK_YELLOW, 712 TX3912VIDEO_DARK_BLUE, 713 TX3912VIDEO_DARK_MAGENTA, 714 TX3912VIDEO_DARK_CYAN, 715 TX3912VIDEO_DARK_WHITE, 716 }; 717 718 KASSERT(ri); 719 720 if (sc->sc_chip->vc_fbdepth == 8) { 721 /* XXX 2bit gray scale LUT not supported */ 722 memcpy(ri->ri_devcmap, system_cmap, sizeof system_cmap); 723 } 724 } 725 726 void 727 tx3912video_clut_init(struct tx3912video_softc *sc) 728 { 729 tx_chipset_tag_t tc = sc->sc_chip->vc_v; 730 731 if (sc->sc_chip->vc_fbdepth != 8) { 732 return; /* XXX 2bit gray scale LUT not supported */ 733 } 734 735 /* 736 * time-based dithering pattern (TOSHIBA recommended pattern) 737 */ 738 /* 2/3, 1/3 */ 739 tx_conf_write(tc, TX3912_VIDEOCTRL8_REG, 740 TX3912_VIDEOCTRL8_PAT2_3_DEFAULT); 741 /* 3/4, 2/4 */ 742 tx_conf_write(tc, TX3912_VIDEOCTRL9_REG, 743 (TX3912_VIDEOCTRL9_PAT3_4_DEFAULT << 16) | 744 TX3912_VIDEOCTRL9_PAT2_4_DEFAULT); 745 /* 4/5, 1/5 */ 746 tx_conf_write(tc, TX3912_VIDEOCTRL10_REG, 747 TX3912_VIDEOCTRL10_PAT4_5_DEFAULT); 748 /* 3/5, 2/5 */ 749 tx_conf_write(tc, TX3912_VIDEOCTRL11_REG, 750 TX3912_VIDEOCTRL11_PAT3_5_DEFAULT); 751 /* 6/7, 1/7 */ 752 tx_conf_write(tc, TX3912_VIDEOCTRL12_REG, 753 TX3912_VIDEOCTRL12_PAT6_7_DEFAULT); 754 /* 5/7, 2/7 */ 755 tx_conf_write(tc, TX3912_VIDEOCTRL13_REG, 756 TX3912_VIDEOCTRL13_PAT5_7_DEFAULT); 757 /* 4/7, 3/7 */ 758 tx_conf_write(tc, TX3912_VIDEOCTRL14_REG, 759 TX3912_VIDEOCTRL14_PAT4_7_DEFAULT); 760 761 /* 762 * dither-pattern look-up table. (selected by uch) 763 */ 764 /* red */ 765 tx_conf_write(tc, TX3912_VIDEOCTRL5_REG, 766 (dither_level8[7] << 28) | 767 (dither_level8[6] << 24) | 768 (dither_level8[5] << 20) | 769 (dither_level8[4] << 16) | 770 (dither_level8[3] << 12) | 771 (dither_level8[2] << 8) | 772 (dither_level8[1] << 4) | 773 (dither_level8[0] << 0)); 774 /* green */ 775 tx_conf_write(tc, TX3912_VIDEOCTRL6_REG, 776 (dither_level8[7] << 28) | 777 (dither_level8[6] << 24) | 778 (dither_level8[5] << 20) | 779 (dither_level8[4] << 16) | 780 (dither_level8[3] << 12) | 781 (dither_level8[2] << 8) | 782 (dither_level8[1] << 4) | 783 (dither_level8[0] << 0)); 784 /* blue (2bit gray scale also use this look-up table) */ 785 tx_conf_write(tc, TX3912_VIDEOCTRL7_REG, 786 (dither_level4[3] << 12) | 787 (dither_level4[2] << 8) | 788 (dither_level4[1] << 4) | 789 (dither_level4[0] << 0)); 790 791 tx3912video_reset(sc->sc_chip); 792 } 793
Indexes created Thu Nov 06 21:09:53 GMT 2025