tx3912video.c revision 1.23.2.1
1 /* $NetBSD: tx3912video.c,v 1.23.2.1 2002/02/11 20:08:10 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #define TX3912VIDEO_DEBUG 40 41 #include "hpcfb.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/extent.h> 47 48 #include <sys/ioctl.h> 49 #include <sys/buf.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <dev/cons.h> /* consdev */ 54 55 #include <machine/bus.h> 56 #include <machine/bootinfo.h> 57 #include <machine/config_hook.h> 58 59 #include <hpcmips/tx/tx39var.h> 60 #include <hpcmips/tx/tx3912videovar.h> 61 #include <hpcmips/tx/tx3912videoreg.h> 62 63 /* CLUT */ 64 #include <dev/wscons/wsdisplayvar.h> 65 #include <dev/rasops/rasops.h> 66 #include <dev/hpc/video_subr.h> 67 68 #include <dev/wscons/wsconsio.h> 69 #include <dev/hpc/hpcfbvar.h> 70 #include <dev/hpc/hpcfbio.h> 71 72 #ifdef TX3912VIDEO_DEBUG 73 int tx3912video_debug = 1; 74 #define DPRINTF(arg) if (tx3912video_debug) printf arg; 75 #define DPRINTFN(n, arg) if (tx3912video_debug > (n)) printf arg; 76 #else 77 #define DPRINTF(arg) 78 #define DPRINTFN(n, arg) 79 #endif 80 81 struct tx3912video_softc { 82 struct device sc_dev; 83 void *sc_powerhook; /* power management hook */ 84 int sc_console; 85 struct hpcfb_fbconf sc_fbconf; 86 struct hpcfb_dspconf sc_dspconf; 87 struct video_chip *sc_chip; 88 }; 89 90 /* TX3912 built-in video chip itself */ 91 static struct video_chip tx3912video_chip; 92 93 int tx3912video_power(void *, int, long, void *); 94 void tx3912video_framebuffer_init(struct video_chip *); 95 int tx3912video_framebuffer_alloc(struct video_chip *, paddr_t, paddr_t *); 96 void tx3912video_reset(struct video_chip *); 97 void tx3912video_resolution_init(struct video_chip *); 98 int tx3912video_match(struct device *, struct cfdata *, void *); 99 void tx3912video_attach(struct device *, struct device *, void *); 100 int tx3912video_print(void *, const char *); 101 102 void tx3912video_hpcfbinit(struct tx3912video_softc *); 103 int tx3912video_ioctl(void *, u_long, caddr_t, int, struct proc *); 104 paddr_t tx3912video_mmap(void *, off_t, int); 105 106 void tx3912video_clut_init(struct tx3912video_softc *); 107 void tx3912video_clut_install(void *, struct rasops_info *); 108 void tx3912video_clut_get(struct tx3912video_softc *, u_int32_t *, int, 109 int); 110 111 static int __get_color8(int); 112 static int __get_color4(int); 113 114 struct cfattach tx3912video_ca = { 115 sizeof(struct tx3912video_softc), tx3912video_match, 116 tx3912video_attach 117 }; 118 119 struct hpcfb_accessops tx3912video_ha = { 120 tx3912video_ioctl, tx3912video_mmap, 0, 0, 0, 0, 121 tx3912video_clut_install 122 }; 123 124 int 125 tx3912video_match(struct device *parent, struct cfdata *cf, void *aux) 126 { 127 return (ATTACH_NORMAL); 128 } 129 130 void 131 tx3912video_attach(struct device *parent, struct device *self, void *aux) 132 { 133 struct tx3912video_softc *sc = (void *)self; 134 struct video_chip *chip; 135 const char *depth_print[] = { 136 [TX3912_VIDEOCTRL1_BITSEL_MONOCHROME] = "monochrome", 137 [TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE] = "2bit greyscale", 138 [TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE] = "4bit greyscale", 139 [TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR] = "8bit color" 140 }; 141 struct hpcfb_attach_args ha; 142 tx_chipset_tag_t tc; 143 txreg_t val; 144 int console; 145 146 sc->sc_console = console = cn_tab ? 0 : 1; 147 sc->sc_chip = chip = &tx3912video_chip; 148 149 /* print video module information */ 150 printf(": %s, frame buffer 0x%08x-0x%08x\n", 151 depth_print[(ffs(chip->vc_fbdepth) - 1) & 0x3], 152 (unsigned)chip->vc_fbpaddr, 153 (unsigned)(chip->vc_fbpaddr + chip->vc_fbsize)); 154 155 /* don't inverse VDAT[3:0] signal */ 156 tc = chip->vc_v; 157 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 158 val &= ~TX3912_VIDEOCTRL1_INVVID; 159 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 160 161 /* install default CLUT */ 162 tx3912video_clut_init(sc); 163 164 /* if serial console, power off video module */ 165 tx3912video_power(sc, 0, 0, (void *) 166 (console ? PWR_RESUME : PWR_SUSPEND)); 167 168 /* Add a hard power hook to power saving */ 169 sc->sc_powerhook = config_hook(CONFIG_HOOK_PMEVENT, 170 CONFIG_HOOK_PMEVENT_HARDPOWER, CONFIG_HOOK_SHARE, 171 tx3912video_power, sc); 172 if (sc->sc_powerhook == 0) 173 printf("WARNING unable to establish hard power hook"); 174 175 #ifdef TX3912VIDEO_DEBUG 176 /* attach debug draw routine (debugging use) */ 177 video_attach_drawfunc(sc->sc_chip); 178 tx_conf_register_video(tc, sc->sc_chip); 179 #endif 180 181 /* Attach frame buffer device */ 182 tx3912video_hpcfbinit(sc); 183 184 if (console && hpcfb_cnattach(&sc->sc_fbconf) != 0) { 185 panic("tx3912video_attach: can't init fb console"); 186 } 187 188 ha.ha_console = console; 189 ha.ha_accessops = &tx3912video_ha; 190 ha.ha_accessctx = sc; 191 ha.ha_curfbconf = 0; 192 ha.ha_nfbconf = 1; 193 ha.ha_fbconflist = &sc->sc_fbconf; 194 ha.ha_curdspconf = 0; 195 ha.ha_ndspconf = 1; 196 ha.ha_dspconflist = &sc->sc_dspconf; 197 198 config_found(self, &ha, hpcfbprint); 199 } 200 201 int 202 tx3912video_power(void *ctx, int type, long id, void *msg) 203 { 204 struct tx3912video_softc *sc = ctx; 205 struct video_chip *chip = sc->sc_chip; 206 tx_chipset_tag_t tc = chip->vc_v; 207 int why = (int)msg; 208 txreg_t val; 209 210 switch (why) { 211 case PWR_RESUME: 212 if (!sc->sc_console) 213 return (0); /* serial console */ 214 215 DPRINTF(("%s: ON\n", sc->sc_dev.dv_xname)); 216 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 217 val |= (TX3912_VIDEOCTRL1_DISPON | TX3912_VIDEOCTRL1_ENVID); 218 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 219 break; 220 case PWR_SUSPEND: 221 /* FALLTHROUGH */ 222 case PWR_STANDBY: 223 DPRINTF(("%s: OFF\n", sc->sc_dev.dv_xname)); 224 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 225 val &= ~(TX3912_VIDEOCTRL1_DISPON | TX3912_VIDEOCTRL1_ENVID); 226 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 227 break; 228 } 229 230 return (0); 231 } 232 233 void 234 tx3912video_hpcfbinit(sc) 235 struct tx3912video_softc *sc; 236 { 237 struct video_chip *chip = sc->sc_chip; 238 struct hpcfb_fbconf *fb = &sc->sc_fbconf; 239 vaddr_t fbvaddr = (vaddr_t)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 240 241 memset(fb, 0, sizeof(struct hpcfb_fbconf)); 242 243 fb->hf_conf_index = 0; /* configuration index */ 244 fb->hf_nconfs = 1; /* how many configurations */ 245 strncpy(fb->hf_name, "TX3912 built-in video", HPCFB_MAXNAMELEN); 246 /* frame buffer name */ 247 strncpy(fb->hf_conf_name, "LCD", HPCFB_MAXNAMELEN); 248 /* configuration name */ 249 fb->hf_height = chip->vc_fbheight; 250 fb->hf_width = chip->vc_fbwidth; 251 fb->hf_baseaddr = (u_long)fbvaddr; 252 fb->hf_offset = (u_long)fbvaddr - 253 mips_ptob(mips_btop(fbvaddr)); 254 /* frame buffer start offset */ 255 fb->hf_bytes_per_line = (chip->vc_fbwidth * chip->vc_fbdepth) 256 / NBBY; 257 fb->hf_nplanes = 1; 258 fb->hf_bytes_per_plane = chip->vc_fbheight * fb->hf_bytes_per_line; 259 260 fb->hf_access_flags |= HPCFB_ACCESS_BYTE; 261 fb->hf_access_flags |= HPCFB_ACCESS_WORD; 262 fb->hf_access_flags |= HPCFB_ACCESS_DWORD; 263 if (video_reverse_color()) 264 fb->hf_access_flags |= HPCFB_ACCESS_REVERSE; 265 266 267 switch (chip->vc_fbdepth) { 268 default: 269 panic("tx3912video_hpcfbinit: not supported color depth\n"); 270 /* NOTREACHED */ 271 case 2: 272 fb->hf_class = HPCFB_CLASS_GRAYSCALE; 273 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 274 fb->hf_pack_width = 8; 275 fb->hf_pixels_per_pack = 4; 276 fb->hf_pixel_width = 2; 277 fb->hf_class_data_length = sizeof(struct hf_gray_tag); 278 /* reserved for future use */ 279 fb->hf_u.hf_gray.hf_flags = 0; 280 break; 281 case 8: 282 fb->hf_class = HPCFB_CLASS_INDEXCOLOR; 283 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 284 fb->hf_pack_width = 8; 285 fb->hf_pixels_per_pack = 1; 286 fb->hf_pixel_width = 8; 287 fb->hf_class_data_length = sizeof(struct hf_indexed_tag); 288 /* reserved for future use */ 289 fb->hf_u.hf_indexed.hf_flags = 0; 290 break; 291 } 292 } 293 294 int 295 tx3912video_init(paddr_t fb_start, paddr_t *fb_end) 296 { 297 struct video_chip *chip = &tx3912video_chip; 298 tx_chipset_tag_t tc; 299 txreg_t reg; 300 int fbdepth, reverse, error; 301 302 reverse = video_reverse_color(); 303 chip->vc_v = tc = tx_conf_get_tag(); 304 305 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 306 fbdepth = 1 << (TX3912_VIDEOCTRL1_BITSEL(reg)); 307 308 switch (fbdepth) { 309 case 2: 310 bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; 311 break; 312 case 4: 313 /* XXX should implement rasops4.c */ 314 fbdepth = 2; 315 bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; 316 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 317 TX3912_VIDEOCTRL1_BITSEL_CLR(reg); 318 reg = TX3912_VIDEOCTRL1_BITSEL_SET(reg, 319 TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE); 320 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 321 break; 322 case 8: 323 bootinfo->fb_type = reverse ? BIFB_D8_FF : BIFB_D8_00; 324 break; 325 } 326 327 chip->vc_fbdepth = fbdepth; 328 chip->vc_fbwidth = bootinfo->fb_width; 329 chip->vc_fbheight= bootinfo->fb_height; 330 331 /* Allocate framebuffer area */ 332 error = tx3912video_framebuffer_alloc(chip, fb_start, fb_end); 333 if (error != 0) 334 return (1); 335 336 #if notyet 337 tx3912video_resolution_init(chip); 338 #else 339 /* Use Windows CE setting. */ 340 #endif 341 /* Set DMA transfer address to VID module */ 342 tx3912video_framebuffer_init(chip); 343 344 /* Syncronize framebuffer addr to frame signal */ 345 tx3912video_reset(chip); 346 347 bootinfo->fb_line_bytes = (chip->vc_fbwidth * fbdepth) / NBBY; 348 bootinfo->fb_addr = (void *)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 349 350 return (0); 351 } 352 353 int 354 tx3912video_framebuffer_alloc(struct video_chip *chip, paddr_t fb_start, 355 paddr_t *fb_end /* buffer allocation hint */) 356 { 357 struct extent_fixed ex_fixed[10]; 358 struct extent *ex; 359 u_long addr, size; 360 int error; 361 362 /* calcurate frame buffer size */ 363 size = (chip->vc_fbwidth * chip->vc_fbheight * chip->vc_fbdepth) / 364 NBBY; 365 366 /* extent V-RAM region */ 367 ex = extent_create("Frame buffer address", fb_start, *fb_end, 368 0, (caddr_t)ex_fixed, sizeof ex_fixed, 369 EX_NOWAIT); 370 if (ex == 0) 371 return (1); 372 373 /* Allocate V-RAM area */ 374 error = extent_alloc_subregion(ex, fb_start, fb_start + size - 1, 375 size, TX3912_FRAMEBUFFER_ALIGNMENT, 376 TX3912_FRAMEBUFFER_BOUNDARY, EX_FAST|EX_NOWAIT, &addr); 377 extent_destroy(ex); 378 379 if (error != 0) 380 return (1); 381 382 chip->vc_fbpaddr = addr; 383 chip->vc_fbvaddr = MIPS_PHYS_TO_KSEG1(addr); 384 chip->vc_fbsize = size; 385 386 *fb_end = addr + size; 387 388 return (0); 389 } 390 391 void 392 tx3912video_framebuffer_init(struct video_chip *chip) 393 { 394 u_int32_t fb_addr, fb_size, vaddr, bank, base; 395 txreg_t reg; 396 tx_chipset_tag_t tc = chip->vc_v; 397 398 fb_addr = chip->vc_fbpaddr; 399 fb_size = chip->vc_fbsize; 400 401 /* XXX currently I don't set DFVAL, so force DF signal toggled on 402 * XXX each frame. */ 403 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 404 reg &= ~TX3912_VIDEOCTRL1_DFMODE; 405 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 406 407 /* Set DMA transfer start and end address */ 408 409 bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr); 410 base = TX3912_VIDEOCTRL3_VIDBASEHI(fb_addr); 411 reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank); 412 /* Upper address counter */ 413 reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base); 414 tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg); 415 416 /* Lower address counter */ 417 base = TX3912_VIDEOCTRL4_VIDBASELO(fb_addr + fb_size); 418 reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base); 419 420 /* Set DF-signal rate */ 421 reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/ 422 423 /* Set VIDDONE signal delay after FRAME signal */ 424 /* XXX not yet*/ 425 tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg); 426 427 /* Clear frame buffer */ 428 vaddr = MIPS_PHYS_TO_KSEG1(fb_addr); 429 memset((void*)vaddr, 0, fb_size); 430 } 431 432 void 433 tx3912video_resolution_init(struct video_chip *chip) 434 { 435 int h, v, split, bit8, horzval, lineval; 436 tx_chipset_tag_t tc = chip->vc_v; 437 txreg_t reg; 438 u_int32_t val; 439 440 h = chip->vc_fbwidth; 441 v = chip->vc_fbheight; 442 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 443 split = reg & TX3912_VIDEOCTRL1_DISPSPLIT; 444 bit8 = (TX3912_VIDEOCTRL1_BITSEL(reg) == 445 TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR); 446 val = TX3912_VIDEOCTRL1_BITSEL(reg); 447 448 if ((val == TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR) && !split) { 449 /* (LCD horizontal pixels / 8bit) * RGB - 1 */ 450 horzval = (h / 8) * 3 - 1; 451 } else { 452 horzval = h / 4 - 1; 453 } 454 lineval = (split ? v / 2 : v) - 1; 455 456 /* Video rate */ 457 /* XXX 458 * probably This value should be determined from DFINT and LCDINT 459 */ 460 reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1); 461 /* Horizontal size of LCD */ 462 reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval); 463 /* # of lines for the LCD */ 464 reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval); 465 466 tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg); 467 } 468 469 void 470 tx3912video_reset(struct video_chip *chip) 471 { 472 tx_chipset_tag_t tc = chip->vc_v; 473 txreg_t reg; 474 475 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 476 477 /* Disable video logic at end of this frame */ 478 reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME; 479 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 480 481 /* Wait for end of frame */ 482 delay(30 * 1000); 483 484 /* Make sure to disable video logic */ 485 reg &= ~TX3912_VIDEOCTRL1_ENVID; 486 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 487 488 delay(1000); 489 490 /* Enable video logic again */ 491 reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME; 492 reg |= TX3912_VIDEOCTRL1_ENVID; 493 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 494 495 delay(1000); 496 } 497 498 int 499 tx3912video_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 500 { 501 struct tx3912video_softc *sc = (struct tx3912video_softc *)v; 502 struct hpcfb_fbconf *fbconf; 503 struct hpcfb_dspconf *dspconf; 504 struct wsdisplay_cmap *cmap; 505 u_int8_t *r, *g, *b; 506 u_int32_t *rgb; 507 int idx, cnt, error; 508 509 switch (cmd) { 510 case WSDISPLAYIO_GETCMAP: 511 cmap = (struct wsdisplay_cmap*)data; 512 cnt = cmap->count; 513 idx = cmap->index; 514 515 if (sc->sc_fbconf.hf_class != HPCFB_CLASS_INDEXCOLOR || 516 sc->sc_fbconf.hf_pack_width != 8 || 517 !LEGAL_CLUT_INDEX(idx) || 518 !LEGAL_CLUT_INDEX(idx + cnt -1)) { 519 return (EINVAL); 520 } 521 522 if (!uvm_useracc(cmap->red, cnt, B_WRITE) || 523 !uvm_useracc(cmap->green, cnt, B_WRITE) || 524 !uvm_useracc(cmap->blue, cnt, B_WRITE)) { 525 return (EFAULT); 526 } 527 528 error = cmap_work_alloc(&r, &g, &b, &rgb, cnt); 529 if (error != 0) { 530 cmap_work_free(r, g, b, rgb); 531 return (ENOMEM); 532 } 533 tx3912video_clut_get(sc, rgb, idx, cnt); 534 rgb24_decompose(rgb, r, g, b, cnt); 535 536 copyout(r, cmap->red, cnt); 537 copyout(g, cmap->green,cnt); 538 copyout(b, cmap->blue, cnt); 539 540 cmap_work_free(r, g, b, rgb); 541 542 return (0); 543 544 case WSDISPLAYIO_PUTCMAP: 545 /* 546 * TX3912 can't change CLUT index. R:G:B = 3:3:2 547 */ 548 return (0); 549 550 case HPCFBIO_GCONF: 551 fbconf = (struct hpcfb_fbconf *)data; 552 if (fbconf->hf_conf_index != 0 && 553 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 554 return (EINVAL); 555 } 556 *fbconf = sc->sc_fbconf; /* structure assignment */ 557 return (0); 558 559 case HPCFBIO_SCONF: 560 fbconf = (struct hpcfb_fbconf *)data; 561 if (fbconf->hf_conf_index != 0 && 562 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 563 return (EINVAL); 564 } 565 /* 566 * nothing to do because we have only one configration 567 */ 568 return (0); 569 570 case HPCFBIO_GDSPCONF: 571 dspconf = (struct hpcfb_dspconf *)data; 572 if ((dspconf->hd_unit_index != 0 && 573 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 574 (dspconf->hd_conf_index != 0 && 575 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 576 return (EINVAL); 577 } 578 *dspconf = sc->sc_dspconf; /* structure assignment */ 579 return (0); 580 581 case HPCFBIO_SDSPCONF: 582 dspconf = (struct hpcfb_dspconf *)data; 583 if ((dspconf->hd_unit_index != 0 && 584 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 585 (dspconf->hd_conf_index != 0 && 586 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 587 return (EINVAL); 588 } 589 /* 590 * nothing to do 591 * because we have only one unit and one configration 592 */ 593 return (0); 594 595 case HPCFBIO_GOP: 596 case HPCFBIO_SOP: 597 /* XXX not implemented yet */ 598 return (EINVAL); 599 } 600 601 return (ENOTTY); 602 } 603 604 paddr_t 605 tx3912video_mmap(void *ctx, off_t offset, int prot) 606 { 607 struct tx3912video_softc *sc = (struct tx3912video_softc *)ctx; 608 609 if (offset < 0 || (sc->sc_fbconf.hf_bytes_per_plane + 610 sc->sc_fbconf.hf_offset) < offset) { 611 return (-1); 612 } 613 614 return (mips_btop(sc->sc_chip->vc_fbpaddr + offset)); 615 } 616 617 /* 618 * CLUT staff 619 */ 620 static const struct { 621 int mul, div; 622 } dither_list [] = { 623 [TX3912_VIDEO_DITHER_DUTYCYCLE_1] = { 1, 1 }, 624 [TX3912_VIDEO_DITHER_DUTYCYCLE_6_7] = { 6, 7 }, 625 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_5] = { 4, 5 }, 626 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_4] = { 3, 4 }, 627 [TX3912_VIDEO_DITHER_DUTYCYCLE_5_7] = { 5, 7 }, 628 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_3] = { 2, 3 }, 629 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_5] = { 3, 5 }, 630 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_7] = { 4, 7 }, 631 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_4] = { 2, 4 }, 632 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_7] = { 3, 7 }, 633 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_5] = { 2, 5 }, 634 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_3] = { 1, 3 }, 635 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_7] = { 2, 7 }, 636 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_5] = { 1, 5 }, 637 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_7] = { 1, 7 }, 638 [TX3912_VIDEO_DITHER_DUTYCYCLE_0] = { 0, 1 } 639 }, *dlp; 640 641 static const int dither_level8[8] = { 642 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 643 TX3912_VIDEO_DITHER_DUTYCYCLE_2_7, 644 TX3912_VIDEO_DITHER_DUTYCYCLE_2_5, 645 TX3912_VIDEO_DITHER_DUTYCYCLE_2_4, 646 TX3912_VIDEO_DITHER_DUTYCYCLE_3_5, 647 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 648 TX3912_VIDEO_DITHER_DUTYCYCLE_4_5, 649 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 650 }; 651 652 static const int dither_level4[4] = { 653 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 654 TX3912_VIDEO_DITHER_DUTYCYCLE_1_3, 655 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 656 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 657 }; 658 659 static int 660 __get_color8(int luti) 661 { 662 KASSERT(luti >=0 && luti < 8); 663 dlp = &dither_list[dither_level8[luti]]; 664 665 return ((0xff * dlp->mul) / dlp->div); 666 } 667 668 static int 669 __get_color4(int luti) 670 { 671 KASSERT(luti >=0 && luti < 4); 672 dlp = &dither_list[dither_level4[luti]]; 673 674 return ((0xff * dlp->mul) / dlp->div); 675 } 676 677 void 678 tx3912video_clut_get(struct tx3912video_softc *sc, u_int32_t *rgb, int beg, 679 int cnt) 680 { 681 int i; 682 683 KASSERT(rgb); 684 KASSERT(LEGAL_CLUT_INDEX(beg)); 685 KASSERT(LEGAL_CLUT_INDEX(beg + cnt - 1)); 686 687 for (i = beg; i < beg + cnt; i++) { 688 *rgb++ = RGB24(__get_color8((i >> 5) & 0x7), 689 __get_color8((i >> 2) & 0x7), 690 __get_color4(i & 0x3)); 691 } 692 } 693 694 void 695 tx3912video_clut_install(void *ctx, struct rasops_info *ri) 696 { 697 struct tx3912video_softc *sc = ctx; 698 const int system_cmap[0x10] = { 699 TX3912VIDEO_BLACK, 700 TX3912VIDEO_RED, 701 TX3912VIDEO_GREEN, 702 TX3912VIDEO_YELLOW, 703 TX3912VIDEO_BLUE, 704 TX3912VIDEO_MAGENTA, 705 TX3912VIDEO_CYAN, 706 TX3912VIDEO_WHITE, 707 TX3912VIDEO_DARK_BLACK, 708 TX3912VIDEO_DARK_RED, 709 TX3912VIDEO_DARK_GREEN, 710 TX3912VIDEO_DARK_YELLOW, 711 TX3912VIDEO_DARK_BLUE, 712 TX3912VIDEO_DARK_MAGENTA, 713 TX3912VIDEO_DARK_CYAN, 714 TX3912VIDEO_DARK_WHITE, 715 }; 716 717 KASSERT(ri); 718 719 if (sc->sc_chip->vc_fbdepth == 8) { 720 /* XXX 2bit gray scale LUT not supported */ 721 memcpy(ri->ri_devcmap, system_cmap, sizeof system_cmap); 722 } 723 } 724 725 void 726 tx3912video_clut_init(struct tx3912video_softc *sc) 727 { 728 tx_chipset_tag_t tc = sc->sc_chip->vc_v; 729 730 if (sc->sc_chip->vc_fbdepth != 8) { 731 return; /* XXX 2bit gray scale LUT not supported */ 732 } 733 734 /* 735 * time-based dithering pattern (TOSHIBA recommended pattern) 736 */ 737 /* 2/3, 1/3 */ 738 tx_conf_write(tc, TX3912_VIDEOCTRL8_REG, 739 TX3912_VIDEOCTRL8_PAT2_3_DEFAULT); 740 /* 3/4, 2/4 */ 741 tx_conf_write(tc, TX3912_VIDEOCTRL9_REG, 742 (TX3912_VIDEOCTRL9_PAT3_4_DEFAULT << 16) | 743 TX3912_VIDEOCTRL9_PAT2_4_DEFAULT); 744 /* 4/5, 1/5 */ 745 tx_conf_write(tc, TX3912_VIDEOCTRL10_REG, 746 TX3912_VIDEOCTRL10_PAT4_5_DEFAULT); 747 /* 3/5, 2/5 */ 748 tx_conf_write(tc, TX3912_VIDEOCTRL11_REG, 749 TX3912_VIDEOCTRL11_PAT3_5_DEFAULT); 750 /* 6/7, 1/7 */ 751 tx_conf_write(tc, TX3912_VIDEOCTRL12_REG, 752 TX3912_VIDEOCTRL12_PAT6_7_DEFAULT); 753 /* 5/7, 2/7 */ 754 tx_conf_write(tc, TX3912_VIDEOCTRL13_REG, 755 TX3912_VIDEOCTRL13_PAT5_7_DEFAULT); 756 /* 4/7, 3/7 */ 757 tx_conf_write(tc, TX3912_VIDEOCTRL14_REG, 758 TX3912_VIDEOCTRL14_PAT4_7_DEFAULT); 759 760 /* 761 * dither-pattern look-up table. (selected by uch) 762 */ 763 /* red */ 764 tx_conf_write(tc, TX3912_VIDEOCTRL5_REG, 765 (dither_level8[7] << 28) | 766 (dither_level8[6] << 24) | 767 (dither_level8[5] << 20) | 768 (dither_level8[4] << 16) | 769 (dither_level8[3] << 12) | 770 (dither_level8[2] << 8) | 771 (dither_level8[1] << 4) | 772 (dither_level8[0] << 0)); 773 /* green */ 774 tx_conf_write(tc, TX3912_VIDEOCTRL6_REG, 775 (dither_level8[7] << 28) | 776 (dither_level8[6] << 24) | 777 (dither_level8[5] << 20) | 778 (dither_level8[4] << 16) | 779 (dither_level8[3] << 12) | 780 (dither_level8[2] << 8) | 781 (dither_level8[1] << 4) | 782 (dither_level8[0] << 0)); 783 /* blue (2bit gray scale also use this look-up table) */ 784 tx_conf_write(tc, TX3912_VIDEOCTRL7_REG, 785 (dither_level4[3] << 12) | 786 (dither_level4[2] << 8) | 787 (dither_level4[1] << 4) | 788 (dither_level4[0] << 0)); 789 790 tx3912video_reset(sc->sc_chip); 791 } 792
Indexes created Thu Nov 06 21:09:53 GMT 2025