tx3912video.c revision 1.23.2.2
1 /* $NetBSD: tx3912video.c,v 1.23.2.2 2002/03/16 15:57:59 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #define TX3912VIDEO_DEBUG 40 41 #include "hpcfb.h" 42 #include "bivideo.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/extent.h> 48 49 #include <sys/ioctl.h> 50 #include <sys/buf.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <dev/cons.h> /* consdev */ 55 56 #include <machine/bus.h> 57 #include <machine/bootinfo.h> 58 #include <machine/config_hook.h> 59 60 #include <hpcmips/tx/tx39var.h> 61 #include <hpcmips/tx/tx3912videovar.h> 62 #include <hpcmips/tx/tx3912videoreg.h> 63 64 /* CLUT */ 65 #include <dev/wscons/wsdisplayvar.h> 66 #include <dev/rasops/rasops.h> 67 #include <dev/hpc/video_subr.h> 68 69 #include <dev/wscons/wsconsio.h> 70 #include <dev/hpc/hpcfbvar.h> 71 #include <dev/hpc/hpcfbio.h> 72 #if NBIVIDEO > 0 73 #include <dev/hpc/bivideovar.h> 74 #endif 75 76 #ifdef TX3912VIDEO_DEBUG 77 int tx3912video_debug = 1; 78 #define DPRINTF(arg) if (tx3912video_debug) printf arg; 79 #define DPRINTFN(n, arg) if (tx3912video_debug > (n)) printf arg; 80 #else 81 #define DPRINTF(arg) 82 #define DPRINTFN(n, arg) 83 #endif 84 85 struct tx3912video_softc { 86 struct device sc_dev; 87 void *sc_powerhook; /* power management hook */ 88 int sc_console; 89 struct hpcfb_fbconf sc_fbconf; 90 struct hpcfb_dspconf sc_dspconf; 91 struct video_chip *sc_chip; 92 }; 93 94 /* TX3912 built-in video chip itself */ 95 static struct video_chip tx3912video_chip; 96 97 int tx3912video_power(void *, int, long, void *); 98 void tx3912video_framebuffer_init(struct video_chip *); 99 int tx3912video_framebuffer_alloc(struct video_chip *, paddr_t, paddr_t *); 100 void tx3912video_reset(struct video_chip *); 101 void tx3912video_resolution_init(struct video_chip *); 102 int tx3912video_match(struct device *, struct cfdata *, void *); 103 void tx3912video_attach(struct device *, struct device *, void *); 104 int tx3912video_print(void *, const char *); 105 106 void tx3912video_hpcfbinit(struct tx3912video_softc *); 107 int tx3912video_ioctl(void *, u_long, caddr_t, int, struct proc *); 108 paddr_t tx3912video_mmap(void *, off_t, int); 109 110 void tx3912video_clut_init(struct tx3912video_softc *); 111 void tx3912video_clut_install(void *, struct rasops_info *); 112 void tx3912video_clut_get(struct tx3912video_softc *, u_int32_t *, int, 113 int); 114 115 static int __get_color8(int); 116 static int __get_color4(int); 117 118 struct cfattach tx3912video_ca = { 119 sizeof(struct tx3912video_softc), tx3912video_match, 120 tx3912video_attach 121 }; 122 123 struct hpcfb_accessops tx3912video_ha = { 124 tx3912video_ioctl, tx3912video_mmap, 0, 0, 0, 0, 125 tx3912video_clut_install 126 }; 127 128 int 129 tx3912video_match(struct device *parent, struct cfdata *cf, void *aux) 130 { 131 return (ATTACH_NORMAL); 132 } 133 134 void 135 tx3912video_attach(struct device *parent, struct device *self, void *aux) 136 { 137 struct tx3912video_softc *sc = (void *)self; 138 struct video_chip *chip; 139 const char *depth_print[] = { 140 [TX3912_VIDEOCTRL1_BITSEL_MONOCHROME] = "monochrome", 141 [TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE] = "2bit greyscale", 142 [TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE] = "4bit greyscale", 143 [TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR] = "8bit color" 144 }; 145 struct hpcfb_attach_args ha; 146 tx_chipset_tag_t tc; 147 txreg_t val; 148 int console; 149 150 sc->sc_console = console = cn_tab ? 0 : 1; 151 sc->sc_chip = chip = &tx3912video_chip; 152 153 /* print video module information */ 154 printf(": %s, frame buffer 0x%08x-0x%08x\n", 155 depth_print[(ffs(chip->vc_fbdepth) - 1) & 0x3], 156 (unsigned)chip->vc_fbpaddr, 157 (unsigned)(chip->vc_fbpaddr + chip->vc_fbsize)); 158 159 /* don't inverse VDAT[3:0] signal */ 160 tc = chip->vc_v; 161 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 162 val &= ~TX3912_VIDEOCTRL1_INVVID; 163 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 164 165 /* install default CLUT */ 166 tx3912video_clut_init(sc); 167 168 /* if serial console, power off video module */ 169 tx3912video_power(sc, 0, 0, (void *) 170 (console ? PWR_RESUME : PWR_SUSPEND)); 171 172 /* Add a hard power hook to power saving */ 173 sc->sc_powerhook = config_hook(CONFIG_HOOK_PMEVENT, 174 CONFIG_HOOK_PMEVENT_HARDPOWER, CONFIG_HOOK_SHARE, 175 tx3912video_power, sc); 176 if (sc->sc_powerhook == 0) 177 printf("WARNING unable to establish hard power hook"); 178 179 #ifdef TX3912VIDEO_DEBUG 180 /* attach debug draw routine (debugging use) */ 181 video_attach_drawfunc(sc->sc_chip); 182 tx_conf_register_video(tc, sc->sc_chip); 183 #endif 184 185 /* Attach frame buffer device */ 186 tx3912video_hpcfbinit(sc); 187 188 if (console && hpcfb_cnattach(&sc->sc_fbconf) != 0) { 189 panic("tx3912video_attach: can't init fb console"); 190 } 191 192 ha.ha_console = console; 193 ha.ha_accessops = &tx3912video_ha; 194 ha.ha_accessctx = sc; 195 ha.ha_curfbconf = 0; 196 ha.ha_nfbconf = 1; 197 ha.ha_fbconflist = &sc->sc_fbconf; 198 ha.ha_curdspconf = 0; 199 ha.ha_ndspconf = 1; 200 ha.ha_dspconflist = &sc->sc_dspconf; 201 202 config_found(self, &ha, hpcfbprint); 203 #if NBIVIDEO > 0 204 /* bivideo is no longer need */ 205 bivideo_dont_attach = 1; 206 #endif /* NBIVIDEO > 0 */ 207 } 208 209 int 210 tx3912video_power(void *ctx, int type, long id, void *msg) 211 { 212 struct tx3912video_softc *sc = ctx; 213 struct video_chip *chip = sc->sc_chip; 214 tx_chipset_tag_t tc = chip->vc_v; 215 int why = (int)msg; 216 txreg_t val; 217 218 switch (why) { 219 case PWR_RESUME: 220 if (!sc->sc_console) 221 return (0); /* serial console */ 222 223 DPRINTF(("%s: ON\n", sc->sc_dev.dv_xname)); 224 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 225 val |= (TX3912_VIDEOCTRL1_DISPON | TX3912_VIDEOCTRL1_ENVID); 226 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 227 break; 228 case PWR_SUSPEND: 229 /* FALLTHROUGH */ 230 case PWR_STANDBY: 231 DPRINTF(("%s: OFF\n", sc->sc_dev.dv_xname)); 232 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 233 val &= ~(TX3912_VIDEOCTRL1_DISPON | TX3912_VIDEOCTRL1_ENVID); 234 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 235 break; 236 } 237 238 return (0); 239 } 240 241 void 242 tx3912video_hpcfbinit(sc) 243 struct tx3912video_softc *sc; 244 { 245 struct video_chip *chip = sc->sc_chip; 246 struct hpcfb_fbconf *fb = &sc->sc_fbconf; 247 vaddr_t fbvaddr = (vaddr_t)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 248 249 memset(fb, 0, sizeof(struct hpcfb_fbconf)); 250 251 fb->hf_conf_index = 0; /* configuration index */ 252 fb->hf_nconfs = 1; /* how many configurations */ 253 strncpy(fb->hf_name, "TX3912 built-in video", HPCFB_MAXNAMELEN); 254 /* frame buffer name */ 255 strncpy(fb->hf_conf_name, "LCD", HPCFB_MAXNAMELEN); 256 /* configuration name */ 257 fb->hf_height = chip->vc_fbheight; 258 fb->hf_width = chip->vc_fbwidth; 259 fb->hf_baseaddr = (u_long)fbvaddr; 260 fb->hf_offset = (u_long)fbvaddr - 261 mips_ptob(mips_btop(fbvaddr)); 262 /* frame buffer start offset */ 263 fb->hf_bytes_per_line = (chip->vc_fbwidth * chip->vc_fbdepth) 264 / NBBY; 265 fb->hf_nplanes = 1; 266 fb->hf_bytes_per_plane = chip->vc_fbheight * fb->hf_bytes_per_line; 267 268 fb->hf_access_flags |= HPCFB_ACCESS_BYTE; 269 fb->hf_access_flags |= HPCFB_ACCESS_WORD; 270 fb->hf_access_flags |= HPCFB_ACCESS_DWORD; 271 if (video_reverse_color()) 272 fb->hf_access_flags |= HPCFB_ACCESS_REVERSE; 273 274 275 switch (chip->vc_fbdepth) { 276 default: 277 panic("tx3912video_hpcfbinit: not supported color depth\n"); 278 /* NOTREACHED */ 279 case 2: 280 fb->hf_class = HPCFB_CLASS_GRAYSCALE; 281 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 282 fb->hf_pack_width = 8; 283 fb->hf_pixels_per_pack = 4; 284 fb->hf_pixel_width = 2; 285 fb->hf_class_data_length = sizeof(struct hf_gray_tag); 286 /* reserved for future use */ 287 fb->hf_u.hf_gray.hf_flags = 0; 288 break; 289 case 8: 290 fb->hf_order_flags = HPCFB_REVORDER_BYTE | HPCFB_REVORDER_WORD; 291 fb->hf_class = HPCFB_CLASS_INDEXCOLOR; 292 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 293 fb->hf_pack_width = 8; 294 fb->hf_pixels_per_pack = 1; 295 fb->hf_pixel_width = 8; 296 fb->hf_class_data_length = sizeof(struct hf_indexed_tag); 297 /* reserved for future use */ 298 fb->hf_u.hf_indexed.hf_flags = 0; 299 break; 300 } 301 } 302 303 int 304 tx3912video_init(paddr_t fb_start, paddr_t *fb_end) 305 { 306 struct video_chip *chip = &tx3912video_chip; 307 tx_chipset_tag_t tc; 308 txreg_t reg; 309 int fbdepth, reverse, error; 310 311 reverse = video_reverse_color(); 312 chip->vc_v = tc = tx_conf_get_tag(); 313 314 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 315 fbdepth = 1 << (TX3912_VIDEOCTRL1_BITSEL(reg)); 316 317 switch (fbdepth) { 318 case 2: 319 bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; 320 break; 321 case 4: 322 /* XXX should implement rasops4.c */ 323 fbdepth = 2; 324 bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; 325 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 326 TX3912_VIDEOCTRL1_BITSEL_CLR(reg); 327 reg = TX3912_VIDEOCTRL1_BITSEL_SET(reg, 328 TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE); 329 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 330 break; 331 case 8: 332 bootinfo->fb_type = reverse ? BIFB_D8_FF : BIFB_D8_00; 333 break; 334 } 335 336 chip->vc_fbdepth = fbdepth; 337 chip->vc_fbwidth = bootinfo->fb_width; 338 chip->vc_fbheight= bootinfo->fb_height; 339 340 /* Allocate framebuffer area */ 341 error = tx3912video_framebuffer_alloc(chip, fb_start, fb_end); 342 if (error != 0) 343 return (1); 344 345 #if notyet 346 tx3912video_resolution_init(chip); 347 #else 348 /* Use Windows CE setting. */ 349 #endif 350 /* Set DMA transfer address to VID module */ 351 tx3912video_framebuffer_init(chip); 352 353 /* Syncronize framebuffer addr to frame signal */ 354 tx3912video_reset(chip); 355 356 bootinfo->fb_line_bytes = (chip->vc_fbwidth * fbdepth) / NBBY; 357 bootinfo->fb_addr = (void *)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 358 359 return (0); 360 } 361 362 int 363 tx3912video_framebuffer_alloc(struct video_chip *chip, paddr_t fb_start, 364 paddr_t *fb_end /* buffer allocation hint */) 365 { 366 struct extent_fixed ex_fixed[10]; 367 struct extent *ex; 368 u_long addr, size; 369 int error; 370 371 /* calcurate frame buffer size */ 372 size = (chip->vc_fbwidth * chip->vc_fbheight * chip->vc_fbdepth) / 373 NBBY; 374 375 /* extent V-RAM region */ 376 ex = extent_create("Frame buffer address", fb_start, *fb_end, 377 0, (caddr_t)ex_fixed, sizeof ex_fixed, 378 EX_NOWAIT); 379 if (ex == 0) 380 return (1); 381 382 /* Allocate V-RAM area */ 383 error = extent_alloc_subregion(ex, fb_start, fb_start + size - 1, 384 size, TX3912_FRAMEBUFFER_ALIGNMENT, 385 TX3912_FRAMEBUFFER_BOUNDARY, EX_FAST|EX_NOWAIT, &addr); 386 extent_destroy(ex); 387 388 if (error != 0) 389 return (1); 390 391 chip->vc_fbpaddr = addr; 392 chip->vc_fbvaddr = MIPS_PHYS_TO_KSEG1(addr); 393 chip->vc_fbsize = size; 394 395 *fb_end = addr + size; 396 397 return (0); 398 } 399 400 void 401 tx3912video_framebuffer_init(struct video_chip *chip) 402 { 403 u_int32_t fb_addr, fb_size, vaddr, bank, base; 404 txreg_t reg; 405 tx_chipset_tag_t tc = chip->vc_v; 406 407 fb_addr = chip->vc_fbpaddr; 408 fb_size = chip->vc_fbsize; 409 410 /* XXX currently I don't set DFVAL, so force DF signal toggled on 411 * XXX each frame. */ 412 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 413 reg &= ~TX3912_VIDEOCTRL1_DFMODE; 414 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 415 416 /* Set DMA transfer start and end address */ 417 418 bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr); 419 base = TX3912_VIDEOCTRL3_VIDBASEHI(fb_addr); 420 reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank); 421 /* Upper address counter */ 422 reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base); 423 tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg); 424 425 /* Lower address counter */ 426 base = TX3912_VIDEOCTRL4_VIDBASELO(fb_addr + fb_size); 427 reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base); 428 429 /* Set DF-signal rate */ 430 reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/ 431 432 /* Set VIDDONE signal delay after FRAME signal */ 433 /* XXX not yet*/ 434 tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg); 435 436 /* Clear frame buffer */ 437 vaddr = MIPS_PHYS_TO_KSEG1(fb_addr); 438 memset((void*)vaddr, 0, fb_size); 439 } 440 441 void 442 tx3912video_resolution_init(struct video_chip *chip) 443 { 444 int h, v, split, bit8, horzval, lineval; 445 tx_chipset_tag_t tc = chip->vc_v; 446 txreg_t reg; 447 u_int32_t val; 448 449 h = chip->vc_fbwidth; 450 v = chip->vc_fbheight; 451 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 452 split = reg & TX3912_VIDEOCTRL1_DISPSPLIT; 453 bit8 = (TX3912_VIDEOCTRL1_BITSEL(reg) == 454 TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR); 455 val = TX3912_VIDEOCTRL1_BITSEL(reg); 456 457 if ((val == TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR) && !split) { 458 /* (LCD horizontal pixels / 8bit) * RGB - 1 */ 459 horzval = (h / 8) * 3 - 1; 460 } else { 461 horzval = h / 4 - 1; 462 } 463 lineval = (split ? v / 2 : v) - 1; 464 465 /* Video rate */ 466 /* XXX 467 * probably This value should be determined from DFINT and LCDINT 468 */ 469 reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1); 470 /* Horizontal size of LCD */ 471 reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval); 472 /* # of lines for the LCD */ 473 reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval); 474 475 tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg); 476 } 477 478 void 479 tx3912video_reset(struct video_chip *chip) 480 { 481 tx_chipset_tag_t tc = chip->vc_v; 482 txreg_t reg; 483 484 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 485 486 /* Disable video logic at end of this frame */ 487 reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME; 488 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 489 490 /* Wait for end of frame */ 491 delay(30 * 1000); 492 493 /* Make sure to disable video logic */ 494 reg &= ~TX3912_VIDEOCTRL1_ENVID; 495 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 496 497 delay(1000); 498 499 /* Enable video logic again */ 500 reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME; 501 reg |= TX3912_VIDEOCTRL1_ENVID; 502 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 503 504 delay(1000); 505 } 506 507 int 508 tx3912video_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 509 { 510 struct tx3912video_softc *sc = (struct tx3912video_softc *)v; 511 struct hpcfb_fbconf *fbconf; 512 struct hpcfb_dspconf *dspconf; 513 struct wsdisplay_cmap *cmap; 514 u_int8_t *r, *g, *b; 515 u_int32_t *rgb; 516 int idx, cnt, error; 517 518 switch (cmd) { 519 case WSDISPLAYIO_GETCMAP: 520 cmap = (struct wsdisplay_cmap*)data; 521 cnt = cmap->count; 522 idx = cmap->index; 523 524 if (sc->sc_fbconf.hf_class != HPCFB_CLASS_INDEXCOLOR || 525 sc->sc_fbconf.hf_pack_width != 8 || 526 !LEGAL_CLUT_INDEX(idx) || 527 !LEGAL_CLUT_INDEX(idx + cnt -1)) { 528 return (EINVAL); 529 } 530 531 if (!uvm_useracc(cmap->red, cnt, B_WRITE) || 532 !uvm_useracc(cmap->green, cnt, B_WRITE) || 533 !uvm_useracc(cmap->blue, cnt, B_WRITE)) { 534 return (EFAULT); 535 } 536 537 error = cmap_work_alloc(&r, &g, &b, &rgb, cnt); 538 if (error != 0) { 539 cmap_work_free(r, g, b, rgb); 540 return (ENOMEM); 541 } 542 tx3912video_clut_get(sc, rgb, idx, cnt); 543 rgb24_decompose(rgb, r, g, b, cnt); 544 545 copyout(r, cmap->red, cnt); 546 copyout(g, cmap->green,cnt); 547 copyout(b, cmap->blue, cnt); 548 549 cmap_work_free(r, g, b, rgb); 550 551 return (0); 552 553 case WSDISPLAYIO_PUTCMAP: 554 /* 555 * TX3912 can't change CLUT index. R:G:B = 3:3:2 556 */ 557 return (0); 558 559 case HPCFBIO_GCONF: 560 fbconf = (struct hpcfb_fbconf *)data; 561 if (fbconf->hf_conf_index != 0 && 562 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 563 return (EINVAL); 564 } 565 *fbconf = sc->sc_fbconf; /* structure assignment */ 566 return (0); 567 568 case HPCFBIO_SCONF: 569 fbconf = (struct hpcfb_fbconf *)data; 570 if (fbconf->hf_conf_index != 0 && 571 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 572 return (EINVAL); 573 } 574 /* 575 * nothing to do because we have only one configration 576 */ 577 return (0); 578 579 case HPCFBIO_GDSPCONF: 580 dspconf = (struct hpcfb_dspconf *)data; 581 if ((dspconf->hd_unit_index != 0 && 582 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 583 (dspconf->hd_conf_index != 0 && 584 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 585 return (EINVAL); 586 } 587 *dspconf = sc->sc_dspconf; /* structure assignment */ 588 return (0); 589 590 case HPCFBIO_SDSPCONF: 591 dspconf = (struct hpcfb_dspconf *)data; 592 if ((dspconf->hd_unit_index != 0 && 593 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 594 (dspconf->hd_conf_index != 0 && 595 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 596 return (EINVAL); 597 } 598 /* 599 * nothing to do 600 * because we have only one unit and one configration 601 */ 602 return (0); 603 604 case HPCFBIO_GOP: 605 case HPCFBIO_SOP: 606 /* XXX not implemented yet */ 607 return (EINVAL); 608 } 609 610 return (ENOTTY); 611 } 612 613 paddr_t 614 tx3912video_mmap(void *ctx, off_t offset, int prot) 615 { 616 struct tx3912video_softc *sc = (struct tx3912video_softc *)ctx; 617 618 if (offset < 0 || (sc->sc_fbconf.hf_bytes_per_plane + 619 sc->sc_fbconf.hf_offset) < offset) { 620 return (-1); 621 } 622 623 return (mips_btop(sc->sc_chip->vc_fbpaddr + offset)); 624 } 625 626 /* 627 * CLUT staff 628 */ 629 static const struct { 630 int mul, div; 631 } dither_list [] = { 632 [TX3912_VIDEO_DITHER_DUTYCYCLE_1] = { 1, 1 }, 633 [TX3912_VIDEO_DITHER_DUTYCYCLE_6_7] = { 6, 7 }, 634 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_5] = { 4, 5 }, 635 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_4] = { 3, 4 }, 636 [TX3912_VIDEO_DITHER_DUTYCYCLE_5_7] = { 5, 7 }, 637 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_3] = { 2, 3 }, 638 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_5] = { 3, 5 }, 639 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_7] = { 4, 7 }, 640 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_4] = { 2, 4 }, 641 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_7] = { 3, 7 }, 642 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_5] = { 2, 5 }, 643 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_3] = { 1, 3 }, 644 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_7] = { 2, 7 }, 645 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_5] = { 1, 5 }, 646 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_7] = { 1, 7 }, 647 [TX3912_VIDEO_DITHER_DUTYCYCLE_0] = { 0, 1 } 648 }, *dlp; 649 650 static const int dither_level8[8] = { 651 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 652 TX3912_VIDEO_DITHER_DUTYCYCLE_2_7, 653 TX3912_VIDEO_DITHER_DUTYCYCLE_2_5, 654 TX3912_VIDEO_DITHER_DUTYCYCLE_2_4, 655 TX3912_VIDEO_DITHER_DUTYCYCLE_3_5, 656 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 657 TX3912_VIDEO_DITHER_DUTYCYCLE_4_5, 658 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 659 }; 660 661 static const int dither_level4[4] = { 662 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 663 TX3912_VIDEO_DITHER_DUTYCYCLE_1_3, 664 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 665 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 666 }; 667 668 static int 669 __get_color8(int luti) 670 { 671 KASSERT(luti >=0 && luti < 8); 672 dlp = &dither_list[dither_level8[luti]]; 673 674 return ((0xff * dlp->mul) / dlp->div); 675 } 676 677 static int 678 __get_color4(int luti) 679 { 680 KASSERT(luti >=0 && luti < 4); 681 dlp = &dither_list[dither_level4[luti]]; 682 683 return ((0xff * dlp->mul) / dlp->div); 684 } 685 686 void 687 tx3912video_clut_get(struct tx3912video_softc *sc, u_int32_t *rgb, int beg, 688 int cnt) 689 { 690 int i; 691 692 KASSERT(rgb); 693 KASSERT(LEGAL_CLUT_INDEX(beg)); 694 KASSERT(LEGAL_CLUT_INDEX(beg + cnt - 1)); 695 696 for (i = beg; i < beg + cnt; i++) { 697 *rgb++ = RGB24(__get_color8((i >> 5) & 0x7), 698 __get_color8((i >> 2) & 0x7), 699 __get_color4(i & 0x3)); 700 } 701 } 702 703 void 704 tx3912video_clut_install(void *ctx, struct rasops_info *ri) 705 { 706 struct tx3912video_softc *sc = ctx; 707 const int system_cmap[0x10] = { 708 TX3912VIDEO_BLACK, 709 TX3912VIDEO_RED, 710 TX3912VIDEO_GREEN, 711 TX3912VIDEO_YELLOW, 712 TX3912VIDEO_BLUE, 713 TX3912VIDEO_MAGENTA, 714 TX3912VIDEO_CYAN, 715 TX3912VIDEO_WHITE, 716 TX3912VIDEO_DARK_BLACK, 717 TX3912VIDEO_DARK_RED, 718 TX3912VIDEO_DARK_GREEN, 719 TX3912VIDEO_DARK_YELLOW, 720 TX3912VIDEO_DARK_BLUE, 721 TX3912VIDEO_DARK_MAGENTA, 722 TX3912VIDEO_DARK_CYAN, 723 TX3912VIDEO_DARK_WHITE, 724 }; 725 726 KASSERT(ri); 727 728 if (sc->sc_chip->vc_fbdepth == 8) { 729 /* XXX 2bit gray scale LUT not supported */ 730 memcpy(ri->ri_devcmap, system_cmap, sizeof system_cmap); 731 } 732 } 733 734 void 735 tx3912video_clut_init(struct tx3912video_softc *sc) 736 { 737 tx_chipset_tag_t tc = sc->sc_chip->vc_v; 738 739 if (sc->sc_chip->vc_fbdepth != 8) { 740 return; /* XXX 2bit gray scale LUT not supported */ 741 } 742 743 /* 744 * time-based dithering pattern (TOSHIBA recommended pattern) 745 */ 746 /* 2/3, 1/3 */ 747 tx_conf_write(tc, TX3912_VIDEOCTRL8_REG, 748 TX3912_VIDEOCTRL8_PAT2_3_DEFAULT); 749 /* 3/4, 2/4 */ 750 tx_conf_write(tc, TX3912_VIDEOCTRL9_REG, 751 (TX3912_VIDEOCTRL9_PAT3_4_DEFAULT << 16) | 752 TX3912_VIDEOCTRL9_PAT2_4_DEFAULT); 753 /* 4/5, 1/5 */ 754 tx_conf_write(tc, TX3912_VIDEOCTRL10_REG, 755 TX3912_VIDEOCTRL10_PAT4_5_DEFAULT); 756 /* 3/5, 2/5 */ 757 tx_conf_write(tc, TX3912_VIDEOCTRL11_REG, 758 TX3912_VIDEOCTRL11_PAT3_5_DEFAULT); 759 /* 6/7, 1/7 */ 760 tx_conf_write(tc, TX3912_VIDEOCTRL12_REG, 761 TX3912_VIDEOCTRL12_PAT6_7_DEFAULT); 762 /* 5/7, 2/7 */ 763 tx_conf_write(tc, TX3912_VIDEOCTRL13_REG, 764 TX3912_VIDEOCTRL13_PAT5_7_DEFAULT); 765 /* 4/7, 3/7 */ 766 tx_conf_write(tc, TX3912_VIDEOCTRL14_REG, 767 TX3912_VIDEOCTRL14_PAT4_7_DEFAULT); 768 769 /* 770 * dither-pattern look-up table. (selected by uch) 771 */ 772 /* red */ 773 tx_conf_write(tc, TX3912_VIDEOCTRL5_REG, 774 (dither_level8[7] << 28) | 775 (dither_level8[6] << 24) | 776 (dither_level8[5] << 20) | 777 (dither_level8[4] << 16) | 778 (dither_level8[3] << 12) | 779 (dither_level8[2] << 8) | 780 (dither_level8[1] << 4) | 781 (dither_level8[0] << 0)); 782 /* green */ 783 tx_conf_write(tc, TX3912_VIDEOCTRL6_REG, 784 (dither_level8[7] << 28) | 785 (dither_level8[6] << 24) | 786 (dither_level8[5] << 20) | 787 (dither_level8[4] << 16) | 788 (dither_level8[3] << 12) | 789 (dither_level8[2] << 8) | 790 (dither_level8[1] << 4) | 791 (dither_level8[0] << 0)); 792 /* blue (2bit gray scale also use this look-up table) */ 793 tx_conf_write(tc, TX3912_VIDEOCTRL7_REG, 794 (dither_level4[3] << 12) | 795 (dither_level4[2] << 8) | 796 (dither_level4[1] << 4) | 797 (dither_level4[0] << 0)); 798 799 tx3912video_reset(sc->sc_chip); 800 } 801
Indexes created Thu Nov 06 21:09:53 GMT 2025