tx3912video.c revision 1.23.2.4
1 /* $NetBSD: tx3912video.c,v 1.23.2.4 2002/10/10 18:32:58 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #define TX3912VIDEO_DEBUG 40 41 #include "hpcfb.h" 42 #include "bivideo.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/extent.h> 48 49 #include <sys/ioctl.h> 50 #include <sys/buf.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <dev/cons.h> /* consdev */ 55 56 #include <machine/bus.h> 57 #include <machine/bootinfo.h> 58 #include <machine/config_hook.h> 59 60 #include <hpcmips/tx/tx39var.h> 61 #include <hpcmips/tx/tx3912videovar.h> 62 #include <hpcmips/tx/tx3912videoreg.h> 63 64 /* CLUT */ 65 #include <dev/wscons/wsdisplayvar.h> 66 #include <dev/rasops/rasops.h> 67 #include <dev/hpc/video_subr.h> 68 69 #include <dev/wscons/wsconsio.h> 70 #include <dev/hpc/hpcfbvar.h> 71 #include <dev/hpc/hpcfbio.h> 72 #if NBIVIDEO > 0 73 #include <dev/hpc/bivideovar.h> 74 #endif 75 76 #ifdef TX3912VIDEO_DEBUG 77 int tx3912video_debug = 1; 78 #define DPRINTF(arg) if (tx3912video_debug) printf arg; 79 #define DPRINTFN(n, arg) if (tx3912video_debug > (n)) printf arg; 80 #else 81 #define DPRINTF(arg) 82 #define DPRINTFN(n, arg) 83 #endif 84 85 struct tx3912video_softc { 86 struct device sc_dev; 87 void *sc_powerhook; /* power management hook */ 88 int sc_console; 89 struct hpcfb_fbconf sc_fbconf; 90 struct hpcfb_dspconf sc_dspconf; 91 struct video_chip *sc_chip; 92 }; 93 94 /* TX3912 built-in video chip itself */ 95 static struct video_chip tx3912video_chip; 96 97 int tx3912video_power(void *, int, long, void *); 98 void tx3912video_framebuffer_init(struct video_chip *); 99 int tx3912video_framebuffer_alloc(struct video_chip *, paddr_t, paddr_t *); 100 void tx3912video_reset(struct video_chip *); 101 void tx3912video_resolution_init(struct video_chip *); 102 int tx3912video_match(struct device *, struct cfdata *, void *); 103 void tx3912video_attach(struct device *, struct device *, void *); 104 int tx3912video_print(void *, const char *); 105 106 void tx3912video_hpcfbinit(struct tx3912video_softc *); 107 int tx3912video_ioctl(void *, u_long, caddr_t, int, struct proc *); 108 paddr_t tx3912video_mmap(void *, off_t, int); 109 110 void tx3912video_clut_init(struct tx3912video_softc *); 111 void tx3912video_clut_install(void *, struct rasops_info *); 112 void tx3912video_clut_get(struct tx3912video_softc *, u_int32_t *, int, 113 int); 114 115 static int __get_color8(int); 116 static int __get_color4(int); 117 118 CFATTACH_DECL(tx3912video, sizeof(struct tx3912video_softc), 119 tx3912video_match, tx3912video_attach, NULL, NULL); 120 121 struct hpcfb_accessops tx3912video_ha = { 122 tx3912video_ioctl, tx3912video_mmap, 0, 0, 0, 0, 123 tx3912video_clut_install 124 }; 125 126 int 127 tx3912video_match(struct device *parent, struct cfdata *cf, void *aux) 128 { 129 return (ATTACH_NORMAL); 130 } 131 132 void 133 tx3912video_attach(struct device *parent, struct device *self, void *aux) 134 { 135 struct tx3912video_softc *sc = (void *)self; 136 struct video_chip *chip; 137 static const char *const depth_print[] = { 138 [TX3912_VIDEOCTRL1_BITSEL_MONOCHROME] = "monochrome", 139 [TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE] = "2bit greyscale", 140 [TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE] = "4bit greyscale", 141 [TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR] = "8bit color" 142 }; 143 struct hpcfb_attach_args ha; 144 tx_chipset_tag_t tc; 145 txreg_t val; 146 int console; 147 148 sc->sc_console = console = cn_tab ? 0 : 1; 149 sc->sc_chip = chip = &tx3912video_chip; 150 151 /* print video module information */ 152 printf(": %s, frame buffer 0x%08x-0x%08x\n", 153 depth_print[(ffs(chip->vc_fbdepth) - 1) & 0x3], 154 (unsigned)chip->vc_fbpaddr, 155 (unsigned)(chip->vc_fbpaddr + chip->vc_fbsize)); 156 157 /* don't inverse VDAT[3:0] signal */ 158 tc = chip->vc_v; 159 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 160 val &= ~TX3912_VIDEOCTRL1_INVVID; 161 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 162 163 /* install default CLUT */ 164 tx3912video_clut_init(sc); 165 166 /* if serial console, power off video module */ 167 tx3912video_power(sc, 0, 0, (void *) 168 (console ? PWR_RESUME : PWR_SUSPEND)); 169 170 /* Add a hard power hook to power saving */ 171 sc->sc_powerhook = config_hook(CONFIG_HOOK_PMEVENT, 172 CONFIG_HOOK_PMEVENT_HARDPOWER, CONFIG_HOOK_SHARE, 173 tx3912video_power, sc); 174 if (sc->sc_powerhook == 0) 175 printf("WARNING unable to establish hard power hook"); 176 177 #ifdef TX3912VIDEO_DEBUG 178 /* attach debug draw routine (debugging use) */ 179 video_attach_drawfunc(sc->sc_chip); 180 tx_conf_register_video(tc, sc->sc_chip); 181 #endif 182 183 /* Attach frame buffer device */ 184 tx3912video_hpcfbinit(sc); 185 186 if (console && hpcfb_cnattach(&sc->sc_fbconf) != 0) { 187 panic("tx3912video_attach: can't init fb console"); 188 } 189 190 ha.ha_console = console; 191 ha.ha_accessops = &tx3912video_ha; 192 ha.ha_accessctx = sc; 193 ha.ha_curfbconf = 0; 194 ha.ha_nfbconf = 1; 195 ha.ha_fbconflist = &sc->sc_fbconf; 196 ha.ha_curdspconf = 0; 197 ha.ha_ndspconf = 1; 198 ha.ha_dspconflist = &sc->sc_dspconf; 199 200 config_found(self, &ha, hpcfbprint); 201 #if NBIVIDEO > 0 202 /* bivideo is no longer need */ 203 bivideo_dont_attach = 1; 204 #endif /* NBIVIDEO > 0 */ 205 } 206 207 int 208 tx3912video_power(void *ctx, int type, long id, void *msg) 209 { 210 struct tx3912video_softc *sc = ctx; 211 struct video_chip *chip = sc->sc_chip; 212 tx_chipset_tag_t tc = chip->vc_v; 213 int why = (int)msg; 214 txreg_t val; 215 216 switch (why) { 217 case PWR_RESUME: 218 if (!sc->sc_console) 219 return (0); /* serial console */ 220 221 DPRINTF(("%s: ON\n", sc->sc_dev.dv_xname)); 222 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 223 val |= (TX3912_VIDEOCTRL1_DISPON | TX3912_VIDEOCTRL1_ENVID); 224 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 225 break; 226 case PWR_SUSPEND: 227 /* FALLTHROUGH */ 228 case PWR_STANDBY: 229 DPRINTF(("%s: OFF\n", sc->sc_dev.dv_xname)); 230 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 231 val &= ~(TX3912_VIDEOCTRL1_DISPON | TX3912_VIDEOCTRL1_ENVID); 232 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 233 break; 234 } 235 236 return (0); 237 } 238 239 void 240 tx3912video_hpcfbinit(sc) 241 struct tx3912video_softc *sc; 242 { 243 struct video_chip *chip = sc->sc_chip; 244 struct hpcfb_fbconf *fb = &sc->sc_fbconf; 245 vaddr_t fbvaddr = (vaddr_t)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 246 247 memset(fb, 0, sizeof(struct hpcfb_fbconf)); 248 249 fb->hf_conf_index = 0; /* configuration index */ 250 fb->hf_nconfs = 1; /* how many configurations */ 251 strncpy(fb->hf_name, "TX3912 built-in video", HPCFB_MAXNAMELEN); 252 /* frame buffer name */ 253 strncpy(fb->hf_conf_name, "LCD", HPCFB_MAXNAMELEN); 254 /* configuration name */ 255 fb->hf_height = chip->vc_fbheight; 256 fb->hf_width = chip->vc_fbwidth; 257 fb->hf_baseaddr = (u_long)fbvaddr; 258 fb->hf_offset = (u_long)fbvaddr - 259 mips_ptob(mips_btop(fbvaddr)); 260 /* frame buffer start offset */ 261 fb->hf_bytes_per_line = (chip->vc_fbwidth * chip->vc_fbdepth) 262 / NBBY; 263 fb->hf_nplanes = 1; 264 fb->hf_bytes_per_plane = chip->vc_fbheight * fb->hf_bytes_per_line; 265 266 fb->hf_access_flags |= HPCFB_ACCESS_BYTE; 267 fb->hf_access_flags |= HPCFB_ACCESS_WORD; 268 fb->hf_access_flags |= HPCFB_ACCESS_DWORD; 269 if (video_reverse_color()) 270 fb->hf_access_flags |= HPCFB_ACCESS_REVERSE; 271 272 273 switch (chip->vc_fbdepth) { 274 default: 275 panic("tx3912video_hpcfbinit: not supported color depth"); 276 /* NOTREACHED */ 277 case 2: 278 fb->hf_class = HPCFB_CLASS_GRAYSCALE; 279 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 280 fb->hf_pack_width = 8; 281 fb->hf_pixels_per_pack = 4; 282 fb->hf_pixel_width = 2; 283 fb->hf_class_data_length = sizeof(struct hf_gray_tag); 284 /* reserved for future use */ 285 fb->hf_u.hf_gray.hf_flags = 0; 286 break; 287 case 8: 288 fb->hf_class = HPCFB_CLASS_INDEXCOLOR; 289 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 290 fb->hf_pack_width = 8; 291 fb->hf_pixels_per_pack = 1; 292 fb->hf_pixel_width = 8; 293 fb->hf_class_data_length = sizeof(struct hf_indexed_tag); 294 /* reserved for future use */ 295 fb->hf_u.hf_indexed.hf_flags = 0; 296 break; 297 } 298 } 299 300 int 301 tx3912video_init(paddr_t fb_start, paddr_t *fb_end) 302 { 303 struct video_chip *chip = &tx3912video_chip; 304 tx_chipset_tag_t tc; 305 txreg_t reg; 306 int fbdepth, reverse, error; 307 308 reverse = video_reverse_color(); 309 chip->vc_v = tc = tx_conf_get_tag(); 310 311 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 312 fbdepth = 1 << (TX3912_VIDEOCTRL1_BITSEL(reg)); 313 314 switch (fbdepth) { 315 case 2: 316 bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; 317 break; 318 case 4: 319 /* XXX should implement rasops4.c */ 320 fbdepth = 2; 321 bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; 322 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 323 TX3912_VIDEOCTRL1_BITSEL_CLR(reg); 324 reg = TX3912_VIDEOCTRL1_BITSEL_SET(reg, 325 TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE); 326 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 327 break; 328 case 8: 329 bootinfo->fb_type = reverse ? BIFB_D8_FF : BIFB_D8_00; 330 break; 331 } 332 333 chip->vc_fbdepth = fbdepth; 334 chip->vc_fbwidth = bootinfo->fb_width; 335 chip->vc_fbheight= bootinfo->fb_height; 336 337 /* Allocate framebuffer area */ 338 error = tx3912video_framebuffer_alloc(chip, fb_start, fb_end); 339 if (error != 0) 340 return (1); 341 342 #if notyet 343 tx3912video_resolution_init(chip); 344 #else 345 /* Use Windows CE setting. */ 346 #endif 347 /* Set DMA transfer address to VID module */ 348 tx3912video_framebuffer_init(chip); 349 350 /* Syncronize framebuffer addr to frame signal */ 351 tx3912video_reset(chip); 352 353 bootinfo->fb_line_bytes = (chip->vc_fbwidth * fbdepth) / NBBY; 354 bootinfo->fb_addr = (void *)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 355 356 return (0); 357 } 358 359 int 360 tx3912video_framebuffer_alloc(struct video_chip *chip, paddr_t fb_start, 361 paddr_t *fb_end /* buffer allocation hint */) 362 { 363 struct extent_fixed ex_fixed[10]; 364 struct extent *ex; 365 u_long addr, size; 366 int error; 367 368 /* calcurate frame buffer size */ 369 size = (chip->vc_fbwidth * chip->vc_fbheight * chip->vc_fbdepth) / 370 NBBY; 371 372 /* extent V-RAM region */ 373 ex = extent_create("Frame buffer address", fb_start, *fb_end, 374 0, (caddr_t)ex_fixed, sizeof ex_fixed, 375 EX_NOWAIT); 376 if (ex == 0) 377 return (1); 378 379 /* Allocate V-RAM area */ 380 error = extent_alloc_subregion(ex, fb_start, fb_start + size - 1, 381 size, TX3912_FRAMEBUFFER_ALIGNMENT, 382 TX3912_FRAMEBUFFER_BOUNDARY, EX_FAST|EX_NOWAIT, &addr); 383 extent_destroy(ex); 384 385 if (error != 0) 386 return (1); 387 388 chip->vc_fbpaddr = addr; 389 chip->vc_fbvaddr = MIPS_PHYS_TO_KSEG1(addr); 390 chip->vc_fbsize = size; 391 392 *fb_end = addr + size; 393 394 return (0); 395 } 396 397 void 398 tx3912video_framebuffer_init(struct video_chip *chip) 399 { 400 u_int32_t fb_addr, fb_size, vaddr, bank, base; 401 txreg_t reg; 402 tx_chipset_tag_t tc = chip->vc_v; 403 404 fb_addr = chip->vc_fbpaddr; 405 fb_size = chip->vc_fbsize; 406 407 /* XXX currently I don't set DFVAL, so force DF signal toggled on 408 * XXX each frame. */ 409 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 410 reg &= ~TX3912_VIDEOCTRL1_DFMODE; 411 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 412 413 /* Set DMA transfer start and end address */ 414 415 bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr); 416 base = TX3912_VIDEOCTRL3_VIDBASEHI(fb_addr); 417 reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank); 418 /* Upper address counter */ 419 reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base); 420 tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg); 421 422 /* Lower address counter */ 423 base = TX3912_VIDEOCTRL4_VIDBASELO(fb_addr + fb_size); 424 reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base); 425 426 /* Set DF-signal rate */ 427 reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/ 428 429 /* Set VIDDONE signal delay after FRAME signal */ 430 /* XXX not yet*/ 431 tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg); 432 433 /* Clear frame buffer */ 434 vaddr = MIPS_PHYS_TO_KSEG1(fb_addr); 435 memset((void*)vaddr, 0, fb_size); 436 } 437 438 void 439 tx3912video_resolution_init(struct video_chip *chip) 440 { 441 int h, v, split, bit8, horzval, lineval; 442 tx_chipset_tag_t tc = chip->vc_v; 443 txreg_t reg; 444 u_int32_t val; 445 446 h = chip->vc_fbwidth; 447 v = chip->vc_fbheight; 448 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 449 split = reg & TX3912_VIDEOCTRL1_DISPSPLIT; 450 bit8 = (TX3912_VIDEOCTRL1_BITSEL(reg) == 451 TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR); 452 val = TX3912_VIDEOCTRL1_BITSEL(reg); 453 454 if ((val == TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR) && !split) { 455 /* (LCD horizontal pixels / 8bit) * RGB - 1 */ 456 horzval = (h / 8) * 3 - 1; 457 } else { 458 horzval = h / 4 - 1; 459 } 460 lineval = (split ? v / 2 : v) - 1; 461 462 /* Video rate */ 463 /* XXX 464 * probably This value should be determined from DFINT and LCDINT 465 */ 466 reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1); 467 /* Horizontal size of LCD */ 468 reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval); 469 /* # of lines for the LCD */ 470 reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval); 471 472 tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg); 473 } 474 475 void 476 tx3912video_reset(struct video_chip *chip) 477 { 478 tx_chipset_tag_t tc = chip->vc_v; 479 txreg_t reg; 480 481 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 482 483 /* Disable video logic at end of this frame */ 484 reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME; 485 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 486 487 /* Wait for end of frame */ 488 delay(30 * 1000); 489 490 /* Make sure to disable video logic */ 491 reg &= ~TX3912_VIDEOCTRL1_ENVID; 492 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 493 494 delay(1000); 495 496 /* Enable video logic again */ 497 reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME; 498 reg |= TX3912_VIDEOCTRL1_ENVID; 499 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 500 501 delay(1000); 502 } 503 504 int 505 tx3912video_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 506 { 507 struct tx3912video_softc *sc = (struct tx3912video_softc *)v; 508 struct hpcfb_fbconf *fbconf; 509 struct hpcfb_dspconf *dspconf; 510 struct wsdisplay_cmap *cmap; 511 u_int8_t *r, *g, *b; 512 u_int32_t *rgb; 513 int idx, cnt, error; 514 515 switch (cmd) { 516 case WSDISPLAYIO_GETCMAP: 517 cmap = (struct wsdisplay_cmap*)data; 518 cnt = cmap->count; 519 idx = cmap->index; 520 521 if (sc->sc_fbconf.hf_class != HPCFB_CLASS_INDEXCOLOR || 522 sc->sc_fbconf.hf_pack_width != 8 || 523 !LEGAL_CLUT_INDEX(idx) || 524 !LEGAL_CLUT_INDEX(idx + cnt -1)) { 525 return (EINVAL); 526 } 527 528 if (!uvm_useracc(cmap->red, cnt, B_WRITE) || 529 !uvm_useracc(cmap->green, cnt, B_WRITE) || 530 !uvm_useracc(cmap->blue, cnt, B_WRITE)) { 531 return (EFAULT); 532 } 533 534 error = cmap_work_alloc(&r, &g, &b, &rgb, cnt); 535 if (error != 0) { 536 cmap_work_free(r, g, b, rgb); 537 return (ENOMEM); 538 } 539 tx3912video_clut_get(sc, rgb, idx, cnt); 540 rgb24_decompose(rgb, r, g, b, cnt); 541 542 copyout(r, cmap->red, cnt); 543 copyout(g, cmap->green,cnt); 544 copyout(b, cmap->blue, cnt); 545 546 cmap_work_free(r, g, b, rgb); 547 548 return (0); 549 550 case WSDISPLAYIO_PUTCMAP: 551 /* 552 * TX3912 can't change CLUT index. R:G:B = 3:3:2 553 */ 554 return (0); 555 556 case HPCFBIO_GCONF: 557 fbconf = (struct hpcfb_fbconf *)data; 558 if (fbconf->hf_conf_index != 0 && 559 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 560 return (EINVAL); 561 } 562 *fbconf = sc->sc_fbconf; /* structure assignment */ 563 return (0); 564 565 case HPCFBIO_SCONF: 566 fbconf = (struct hpcfb_fbconf *)data; 567 if (fbconf->hf_conf_index != 0 && 568 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 569 return (EINVAL); 570 } 571 /* 572 * nothing to do because we have only one configration 573 */ 574 return (0); 575 576 case HPCFBIO_GDSPCONF: 577 dspconf = (struct hpcfb_dspconf *)data; 578 if ((dspconf->hd_unit_index != 0 && 579 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 580 (dspconf->hd_conf_index != 0 && 581 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 582 return (EINVAL); 583 } 584 *dspconf = sc->sc_dspconf; /* structure assignment */ 585 return (0); 586 587 case HPCFBIO_SDSPCONF: 588 dspconf = (struct hpcfb_dspconf *)data; 589 if ((dspconf->hd_unit_index != 0 && 590 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 591 (dspconf->hd_conf_index != 0 && 592 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 593 return (EINVAL); 594 } 595 /* 596 * nothing to do 597 * because we have only one unit and one configration 598 */ 599 return (0); 600 601 case HPCFBIO_GOP: 602 case HPCFBIO_SOP: 603 /* XXX not implemented yet */ 604 return (EINVAL); 605 } 606 607 return (EPASSTHROUGH); 608 } 609 610 paddr_t 611 tx3912video_mmap(void *ctx, off_t offset, int prot) 612 { 613 struct tx3912video_softc *sc = (struct tx3912video_softc *)ctx; 614 615 if (offset < 0 || (sc->sc_fbconf.hf_bytes_per_plane + 616 sc->sc_fbconf.hf_offset) < offset) { 617 return (-1); 618 } 619 620 return (mips_btop(sc->sc_chip->vc_fbpaddr + offset)); 621 } 622 623 /* 624 * CLUT staff 625 */ 626 static const struct { 627 int mul, div; 628 } dither_list [] = { 629 [TX3912_VIDEO_DITHER_DUTYCYCLE_1] = { 1, 1 }, 630 [TX3912_VIDEO_DITHER_DUTYCYCLE_6_7] = { 6, 7 }, 631 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_5] = { 4, 5 }, 632 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_4] = { 3, 4 }, 633 [TX3912_VIDEO_DITHER_DUTYCYCLE_5_7] = { 5, 7 }, 634 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_3] = { 2, 3 }, 635 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_5] = { 3, 5 }, 636 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_7] = { 4, 7 }, 637 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_4] = { 2, 4 }, 638 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_7] = { 3, 7 }, 639 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_5] = { 2, 5 }, 640 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_3] = { 1, 3 }, 641 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_7] = { 2, 7 }, 642 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_5] = { 1, 5 }, 643 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_7] = { 1, 7 }, 644 [TX3912_VIDEO_DITHER_DUTYCYCLE_0] = { 0, 1 } 645 }, *dlp; 646 647 static const int dither_level8[8] = { 648 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 649 TX3912_VIDEO_DITHER_DUTYCYCLE_2_7, 650 TX3912_VIDEO_DITHER_DUTYCYCLE_2_5, 651 TX3912_VIDEO_DITHER_DUTYCYCLE_2_4, 652 TX3912_VIDEO_DITHER_DUTYCYCLE_3_5, 653 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 654 TX3912_VIDEO_DITHER_DUTYCYCLE_4_5, 655 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 656 }; 657 658 static const int dither_level4[4] = { 659 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 660 TX3912_VIDEO_DITHER_DUTYCYCLE_1_3, 661 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 662 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 663 }; 664 665 static int 666 __get_color8(int luti) 667 { 668 KASSERT(luti >=0 && luti < 8); 669 dlp = &dither_list[dither_level8[luti]]; 670 671 return ((0xff * dlp->mul) / dlp->div); 672 } 673 674 static int 675 __get_color4(int luti) 676 { 677 KASSERT(luti >=0 && luti < 4); 678 dlp = &dither_list[dither_level4[luti]]; 679 680 return ((0xff * dlp->mul) / dlp->div); 681 } 682 683 void 684 tx3912video_clut_get(struct tx3912video_softc *sc, u_int32_t *rgb, int beg, 685 int cnt) 686 { 687 int i; 688 689 KASSERT(rgb); 690 KASSERT(LEGAL_CLUT_INDEX(beg)); 691 KASSERT(LEGAL_CLUT_INDEX(beg + cnt - 1)); 692 693 for (i = beg; i < beg + cnt; i++) { 694 *rgb++ = RGB24(__get_color8((i >> 5) & 0x7), 695 __get_color8((i >> 2) & 0x7), 696 __get_color4(i & 0x3)); 697 } 698 } 699 700 void 701 tx3912video_clut_install(void *ctx, struct rasops_info *ri) 702 { 703 struct tx3912video_softc *sc = ctx; 704 static const int system_cmap[0x10] = { 705 TX3912VIDEO_BLACK, 706 TX3912VIDEO_RED, 707 TX3912VIDEO_GREEN, 708 TX3912VIDEO_YELLOW, 709 TX3912VIDEO_BLUE, 710 TX3912VIDEO_MAGENTA, 711 TX3912VIDEO_CYAN, 712 TX3912VIDEO_WHITE, 713 TX3912VIDEO_DARK_BLACK, 714 TX3912VIDEO_DARK_RED, 715 TX3912VIDEO_DARK_GREEN, 716 TX3912VIDEO_DARK_YELLOW, 717 TX3912VIDEO_DARK_BLUE, 718 TX3912VIDEO_DARK_MAGENTA, 719 TX3912VIDEO_DARK_CYAN, 720 TX3912VIDEO_DARK_WHITE, 721 }; 722 723 KASSERT(ri); 724 725 if (sc->sc_chip->vc_fbdepth == 8) { 726 /* XXX 2bit gray scale LUT not supported */ 727 memcpy(ri->ri_devcmap, system_cmap, sizeof system_cmap); 728 } 729 } 730 731 void 732 tx3912video_clut_init(struct tx3912video_softc *sc) 733 { 734 tx_chipset_tag_t tc = sc->sc_chip->vc_v; 735 736 if (sc->sc_chip->vc_fbdepth != 8) { 737 return; /* XXX 2bit gray scale LUT not supported */ 738 } 739 740 /* 741 * time-based dithering pattern (TOSHIBA recommended pattern) 742 */ 743 /* 2/3, 1/3 */ 744 tx_conf_write(tc, TX3912_VIDEOCTRL8_REG, 745 TX3912_VIDEOCTRL8_PAT2_3_DEFAULT); 746 /* 3/4, 2/4 */ 747 tx_conf_write(tc, TX3912_VIDEOCTRL9_REG, 748 (TX3912_VIDEOCTRL9_PAT3_4_DEFAULT << 16) | 749 TX3912_VIDEOCTRL9_PAT2_4_DEFAULT); 750 /* 4/5, 1/5 */ 751 tx_conf_write(tc, TX3912_VIDEOCTRL10_REG, 752 TX3912_VIDEOCTRL10_PAT4_5_DEFAULT); 753 /* 3/5, 2/5 */ 754 tx_conf_write(tc, TX3912_VIDEOCTRL11_REG, 755 TX3912_VIDEOCTRL11_PAT3_5_DEFAULT); 756 /* 6/7, 1/7 */ 757 tx_conf_write(tc, TX3912_VIDEOCTRL12_REG, 758 TX3912_VIDEOCTRL12_PAT6_7_DEFAULT); 759 /* 5/7, 2/7 */ 760 tx_conf_write(tc, TX3912_VIDEOCTRL13_REG, 761 TX3912_VIDEOCTRL13_PAT5_7_DEFAULT); 762 /* 4/7, 3/7 */ 763 tx_conf_write(tc, TX3912_VIDEOCTRL14_REG, 764 TX3912_VIDEOCTRL14_PAT4_7_DEFAULT); 765 766 /* 767 * dither-pattern look-up table. (selected by uch) 768 */ 769 /* red */ 770 tx_conf_write(tc, TX3912_VIDEOCTRL5_REG, 771 (dither_level8[7] << 28) | 772 (dither_level8[6] << 24) | 773 (dither_level8[5] << 20) | 774 (dither_level8[4] << 16) | 775 (dither_level8[3] << 12) | 776 (dither_level8[2] << 8) | 777 (dither_level8[1] << 4) | 778 (dither_level8[0] << 0)); 779 /* green */ 780 tx_conf_write(tc, TX3912_VIDEOCTRL6_REG, 781 (dither_level8[7] << 28) | 782 (dither_level8[6] << 24) | 783 (dither_level8[5] << 20) | 784 (dither_level8[4] << 16) | 785 (dither_level8[3] << 12) | 786 (dither_level8[2] << 8) | 787 (dither_level8[1] << 4) | 788 (dither_level8[0] << 0)); 789 /* blue (2bit gray scale also use this look-up table) */ 790 tx_conf_write(tc, TX3912_VIDEOCTRL7_REG, 791 (dither_level4[3] << 12) | 792 (dither_level4[2] << 8) | 793 (dither_level4[1] << 4) | 794 (dither_level4[0] << 0)); 795 796 tx3912video_reset(sc->sc_chip); 797 } 798
Indexes created Thu Nov 06 21:09:53 GMT 2025