tx3912video.c revision 1.3
1 /* $NetBSD: tx3912video.c,v 1.3 1999/12/12 17:04:55 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include "opt_tx39_debug.h" 29 #include "fb.h" 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/device.h> 34 #include <sys/extent.h> 35 36 #include <machine/bus.h> 37 #include <machine/bootinfo.h> /* bootinfo */ 38 39 #include <hpcmips/tx/tx39var.h> 40 #include <hpcmips/tx/tx3912videovar.h> 41 #include <hpcmips/tx/tx3912videoreg.h> 42 43 #if NFB > 0 44 #include <dev/rcons/raster.h> 45 #include <dev/wscons/wsdisplayvar.h> 46 #include <arch/hpcmips/dev/fbvar.h> 47 #endif 48 49 void tx3912video_framebuffer_init __P((tx_chipset_tag_t, u_int32_t, 50 u_int32_t)); 51 int tx3912video_framebuffer_alloc __P((tx_chipset_tag_t, u_int32_t, 52 int, int, int, u_int32_t*, 53 u_int32_t*)); 54 void tx3912video_reset __P((tx_chipset_tag_t)); 55 void tx3912video_resolution_init __P((tx_chipset_tag_t, int, int)); 56 int tx3912video_fbdepth __P((tx_chipset_tag_t, int)); 57 58 static u_int32_t framebuffer, framebuffersize; 59 60 int tx3912video_match __P((struct device*, struct cfdata*, void*)); 61 void tx3912video_attach __P((struct device*, struct device*, void*)); 62 int tx3912video_print __P((void*, const char*)); 63 64 struct tx3912video_softc { 65 struct device sc_dev; 66 u_int32_t sc_fbaddr; 67 u_int32_t sc_fbsize; 68 }; 69 70 struct fb_attach_args { 71 const char *fba_name; 72 }; 73 74 struct cfattach tx3912video_ca = { 75 sizeof(struct tx3912video_softc), tx3912video_match, 76 tx3912video_attach 77 }; 78 79 int 80 tx3912video_match(parent, cf, aux) 81 struct device *parent; 82 struct cfdata *cf; 83 void *aux; 84 { 85 return 1; 86 } 87 88 void 89 tx3912video_attach(parent, self, aux) 90 struct device *parent; 91 struct device *self; 92 void *aux; 93 { 94 struct txsim_attach_args *ta = aux; 95 struct tx3912video_softc *sc = (void*)self; 96 tx_chipset_tag_t tc = ta->ta_tc; 97 struct fb_attach_args fba; 98 99 printf("\n"); 100 sc->sc_fbaddr = framebuffer; 101 sc->sc_fbsize = framebuffersize; 102 printf("TMPR3912 video module ["); 103 tx3912video_fbdepth(tc, 1); 104 printf("] frame buffer: 0x%08x-0x%08x\n", sc->sc_fbaddr, 105 sc->sc_fbaddr + sc->sc_fbsize); 106 107 /* Attach frame buffer device */ 108 #if NFB > 0 109 if (!(bootinfo->bi_cnuse & BI_CNUSE_SERIAL)) { 110 if (fb_cnattach(0, 0, 0, 0)) { 111 panic("tx3912video_attach: can't init fb console"); 112 } 113 } 114 fba.fba_name = "fb"; 115 config_found(self, &fba, tx3912video_print); 116 #endif 117 } 118 119 int 120 tx3912video_print(aux, pnp) 121 void *aux; 122 const char *pnp; 123 { 124 return pnp ? QUIET : UNCONF; 125 } 126 127 int 128 tx3912video_init(tc, fb_start, fb_width, fb_height, fb_addr, fb_size, 129 fb_line_bytes) 130 tx_chipset_tag_t tc; 131 u_int32_t fb_start; /* Physical address */ 132 int fb_width, fb_height; 133 u_int32_t *fb_addr, *fb_size; 134 int *fb_line_bytes; 135 { 136 u_int32_t addr, size; 137 int fb_depth; 138 139 /* Inquire bit depth */ 140 fb_depth = tx3912video_fbdepth(tc, 0); 141 142 /* Allocate framebuffer area */ 143 if (tx3912video_framebuffer_alloc(tc, fb_start, fb_width, fb_height, 144 fb_depth, &addr, &size)) { 145 return 1; 146 } 147 #if notyet 148 tx3912video_resolution_init(tc, fb_width, fb_height); 149 #else 150 /* Use Windows CE setting. */ 151 #endif 152 /* Set DMA transfer address to VID module */ 153 tx3912video_framebuffer_init(tc, addr, size); 154 155 /* Syncronize framebuffer addr to frame signal */ 156 tx3912video_reset(tc); 157 158 *fb_line_bytes = (fb_width * fb_depth) / 8; 159 *fb_addr = addr; /* Phsical address */ 160 *fb_size = size; 161 162 return 0; 163 } 164 165 int 166 tx3912video_framebuffer_alloc(tc, start, h, v, depth, fb_addr, fb_size) 167 tx_chipset_tag_t tc; 168 u_int32_t start; 169 int h, v, depth; 170 u_int32_t *fb_addr, *fb_size; 171 { 172 struct extent_fixed ex_fixed[2]; 173 struct extent *ex; 174 u_long addr, size; 175 int err; 176 177 /* Calcurate frame buffer size */ 178 size = (h * v * depth) / 8; 179 180 /* Allocate V-RAM area */ 181 if (!(ex = extent_create("Frame buffer address", start, 182 start + TX3912_FRAMEBUFFER_MAX, 183 0, (caddr_t)ex_fixed, sizeof ex_fixed, 184 EX_NOWAIT))) { 185 return 1; 186 } 187 if((err = extent_alloc_subregion(ex, start, start + size, size, 188 TX3912_FRAMEBUFFER_ALIGNMENT, 189 TX3912_FRAMEBUFFER_BOUNDARY, 190 EX_FAST|EX_NOWAIT, &addr))) { 191 return 1; 192 } 193 framebuffer = addr; 194 framebuffersize = size; 195 *fb_addr = addr; 196 *fb_size = size; 197 198 return 0; 199 } 200 201 void 202 tx3912video_framebuffer_init(tc, fb_addr, fb_size) 203 tx_chipset_tag_t tc; 204 u_int32_t fb_addr, fb_size; 205 { 206 u_int32_t reg, vaddr, bank, base; 207 208 /* XXX currently I don't set DFVAL, so force DF signal toggled on 209 * XXX each frame. */ 210 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 211 reg &= ~TX3912_VIDEOCTRL1_DFMODE; 212 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 213 214 /* Set DMA transfer start and end address */ 215 216 bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr); 217 base = TX3912_VIDEOCTRL3_VIDBASEHI(fb_addr); 218 reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank); 219 /* Upper address counter */ 220 reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base); 221 tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg); 222 223 /* Lower address counter */ 224 base = TX3912_VIDEOCTRL4_VIDBASELO(fb_addr + fb_size); 225 reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base); 226 227 /* Set DF-signal rate */ 228 reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/ 229 230 /* Set VIDDONE signal delay after FRAME signal */ 231 /* XXX not yet*/ 232 tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg); 233 234 /* Clear frame buffer */ 235 vaddr = MIPS_PHYS_TO_KSEG1(fb_addr); 236 bzero((void*)vaddr, fb_size); 237 } 238 239 void 240 tx3912video_resolution_init(tc, h, v) 241 tx_chipset_tag_t tc; 242 int h; 243 int v; 244 { 245 u_int32_t reg, val; 246 int split, bit8, horzval, lineval; 247 248 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 249 split = reg & TX3912_VIDEOCTRL1_DISPSPLIT; 250 bit8 = (TX3912_VIDEOCTRL1_BITSEL(reg) == 251 TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR); 252 val = TX3912_VIDEOCTRL1_BITSEL(reg); 253 254 if ((val == TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR) && 255 !split) { 256 /* (LCD horizontal pixels / 8bit) * RGB - 1 */ 257 horzval = (h / 8) * 3 - 1; 258 } else { 259 horzval = h / 4 - 1; 260 } 261 lineval = (split ? v / 2 : v) - 1; 262 263 /* Video rate */ 264 /* XXX 265 * probably This value should be determined from DFINT and LCDINT 266 */ 267 reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1); 268 /* Horizontal size of LCD */ 269 reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval); 270 /* # of lines for the LCD */ 271 reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval); 272 273 tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg); 274 } 275 276 int 277 tx3912video_fbdepth(tc, verbose) 278 tx_chipset_tag_t tc; 279 int verbose; 280 { 281 u_int32_t reg, val; 282 283 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 284 val = TX3912_VIDEOCTRL1_BITSEL(reg); 285 switch (val) { 286 case TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR: 287 if (verbose) 288 printf("8bit color"); 289 return 8; 290 case TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE: 291 if (verbose) 292 printf("4bit greyscale"); 293 return 4; 294 case TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE: 295 if (verbose) 296 printf("2bit greyscale"); 297 return 2; 298 case TX3912_VIDEOCTRL1_BITSEL_MONOCHROME: 299 if (verbose) 300 printf("monochrome"); 301 return 1; 302 } 303 return 0; 304 } 305 306 void 307 tx3912video_reset(tc) 308 tx_chipset_tag_t tc; 309 { 310 u_int32_t reg; 311 312 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 313 314 /* Disable video logic at end of this frame */ 315 reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME; 316 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 317 318 /* Wait for end of frame */ 319 delay(300 * 1000); 320 321 /* Make sure to disable video logic */ 322 reg &= ~TX3912_VIDEOCTRL1_ENVID; 323 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 324 325 delay(1000); 326 327 /* Enable video logic again */ 328 reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME; 329 reg |= TX3912_VIDEOCTRL1_ENVID; 330 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 331 332 delay(1000); 333 } 334 335 336
Indexes created Fri Oct 31 11:10:07 GMT 2025