tx3912video.c revision 1.41.6.2
1 /* $NetBSD: tx3912video.c,v 1.41.6.2 2014/08/20 00:03:03 tls Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tx3912video.c,v 1.41.6.2 2014/08/20 00:03:03 tls Exp $"); 34 35 #define TX3912VIDEO_DEBUG 36 37 #include "hpcfb.h" 38 #include "bivideo.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/extent.h> 44 45 #include <sys/ioctl.h> 46 #include <sys/buf.h> 47 48 #include <uvm/uvm_extern.h> 49 50 #include <dev/cons.h> /* consdev */ 51 52 #include <machine/bus.h> 53 #include <machine/bootinfo.h> 54 #include <machine/config_hook.h> 55 56 #include <hpcmips/tx/tx39var.h> 57 #include <hpcmips/tx/tx3912videovar.h> 58 #include <hpcmips/tx/tx3912videoreg.h> 59 60 /* CLUT */ 61 #include <dev/wscons/wsdisplayvar.h> 62 #include <dev/rasops/rasops.h> 63 #include <dev/hpc/video_subr.h> 64 65 #include <dev/wscons/wsconsio.h> 66 #include <dev/hpc/hpcfbvar.h> 67 #include <dev/hpc/hpcfbio.h> 68 #if NBIVIDEO > 0 69 #include <dev/hpc/bivideovar.h> 70 #endif 71 72 #ifdef TX3912VIDEO_DEBUG 73 int tx3912video_debug = 1; 74 #define DPRINTF(arg) if (tx3912video_debug) printf arg; 75 #define DPRINTFN(n, arg) if (tx3912video_debug > (n)) printf arg; 76 #else 77 #define DPRINTF(arg) 78 #define DPRINTFN(n, arg) 79 #endif 80 81 struct tx3912video_softc { 82 device_t sc_dev; 83 void *sc_powerhook; /* power management hook */ 84 int sc_console; 85 struct hpcfb_fbconf sc_fbconf; 86 struct hpcfb_dspconf sc_dspconf; 87 struct video_chip *sc_chip; 88 }; 89 90 /* TX3912 built-in video chip itself */ 91 static struct video_chip tx3912video_chip; 92 93 int tx3912video_power(void *, int, long, void *); 94 void tx3912video_framebuffer_init(struct video_chip *); 95 int tx3912video_framebuffer_alloc(struct video_chip *, paddr_t, paddr_t *); 96 void tx3912video_reset(struct video_chip *); 97 void tx3912video_resolution_init(struct video_chip *); 98 int tx3912video_match(device_t, cfdata_t, void *); 99 void tx3912video_attach(device_t, device_t, void *); 100 int tx3912video_print(void *, const char *); 101 102 void tx3912video_hpcfbinit(struct tx3912video_softc *); 103 int tx3912video_ioctl(void *, u_long, void *, int, struct lwp *); 104 paddr_t tx3912video_mmap(void *, off_t, int); 105 106 void tx3912video_clut_init(struct tx3912video_softc *); 107 void tx3912video_clut_install(void *, struct rasops_info *); 108 void tx3912video_clut_get(struct tx3912video_softc *, u_int32_t *, int, 109 int); 110 111 static int __get_color8(int); 112 static int __get_color4(int); 113 114 CFATTACH_DECL_NEW(tx3912video, sizeof(struct tx3912video_softc), 115 tx3912video_match, tx3912video_attach, NULL, NULL); 116 117 struct hpcfb_accessops tx3912video_ha = { 118 tx3912video_ioctl, tx3912video_mmap, 0, 0, 0, 0, 119 tx3912video_clut_install 120 }; 121 122 int 123 tx3912video_match(device_t parent, cfdata_t cf, void *aux) 124 { 125 return (ATTACH_NORMAL); 126 } 127 128 void 129 tx3912video_attach(device_t parent, device_t self, void *aux) 130 { 131 struct tx3912video_softc *sc = device_private(self); 132 struct video_chip *chip; 133 static const char *const depth_print[] = { 134 [TX3912_VIDEOCTRL1_BITSEL_MONOCHROME] = "monochrome", 135 [TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE] = "2bit greyscale", 136 [TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE] = "4bit greyscale", 137 [TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR] = "8bit color" 138 }; 139 struct hpcfb_attach_args ha; 140 tx_chipset_tag_t tc; 141 txreg_t val; 142 int console; 143 144 sc->sc_dev = self; 145 sc->sc_console = console = cn_tab ? 0 : 1; 146 sc->sc_chip = chip = &tx3912video_chip; 147 148 /* print video module information */ 149 printf(": %s, frame buffer 0x%08x-0x%08x\n", 150 depth_print[(ffs(chip->vc_fbdepth) - 1) & 0x3], 151 (unsigned)chip->vc_fbpaddr, 152 (unsigned)(chip->vc_fbpaddr + chip->vc_fbsize)); 153 154 /* don't inverse VDAT[3:0] signal */ 155 tc = chip->vc_v; 156 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 157 val &= ~TX3912_VIDEOCTRL1_INVVID; 158 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 159 160 /* install default CLUT */ 161 tx3912video_clut_init(sc); 162 163 /* if serial console, power off video module */ 164 tx3912video_power(sc, 0, 0, (void *) 165 (console ? PWR_RESUME : PWR_SUSPEND)); 166 167 /* Add a hard power hook to power saving */ 168 sc->sc_powerhook = config_hook(CONFIG_HOOK_PMEVENT, 169 CONFIG_HOOK_PMEVENT_HARDPOWER, CONFIG_HOOK_SHARE, 170 tx3912video_power, sc); 171 if (sc->sc_powerhook == 0) 172 printf("WARNING unable to establish hard power hook"); 173 174 #ifdef TX3912VIDEO_DEBUG 175 /* attach debug draw routine (debugging use) */ 176 video_attach_drawfunc(sc->sc_chip); 177 tx_conf_register_video(tc, sc->sc_chip); 178 #endif 179 180 /* Attach frame buffer device */ 181 tx3912video_hpcfbinit(sc); 182 183 if (console && hpcfb_cnattach(&sc->sc_fbconf) != 0) { 184 panic("tx3912video_attach: can't init fb console"); 185 } 186 187 ha.ha_console = console; 188 ha.ha_accessops = &tx3912video_ha; 189 ha.ha_accessctx = sc; 190 ha.ha_curfbconf = 0; 191 ha.ha_nfbconf = 1; 192 ha.ha_fbconflist = &sc->sc_fbconf; 193 ha.ha_curdspconf = 0; 194 ha.ha_ndspconf = 1; 195 ha.ha_dspconflist = &sc->sc_dspconf; 196 197 config_found(self, &ha, hpcfbprint); 198 #if NBIVIDEO > 0 199 /* bivideo is no longer need */ 200 bivideo_dont_attach = 1; 201 #endif /* NBIVIDEO > 0 */ 202 } 203 204 int 205 tx3912video_power(void *ctx, int type, long id, void *msg) 206 { 207 struct tx3912video_softc *sc = ctx; 208 struct video_chip *chip = sc->sc_chip; 209 tx_chipset_tag_t tc = chip->vc_v; 210 int why = (int)msg; 211 txreg_t val; 212 213 switch (why) { 214 case PWR_RESUME: 215 if (!sc->sc_console) 216 return (0); /* serial console */ 217 218 DPRINTF(("%s: ON\n", device_xname(sc->sc_dev))); 219 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 220 val |= (TX3912_VIDEOCTRL1_DISPON | TX3912_VIDEOCTRL1_ENVID); 221 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 222 break; 223 case PWR_SUSPEND: 224 /* FALLTHROUGH */ 225 case PWR_STANDBY: 226 DPRINTF(("%s: OFF\n", device_xname(sc->sc_dev))); 227 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 228 val &= ~(TX3912_VIDEOCTRL1_DISPON | TX3912_VIDEOCTRL1_ENVID); 229 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 230 break; 231 } 232 233 return (0); 234 } 235 236 void 237 tx3912video_hpcfbinit(struct tx3912video_softc *sc) 238 { 239 struct video_chip *chip = sc->sc_chip; 240 struct hpcfb_fbconf *fb = &sc->sc_fbconf; 241 vaddr_t fbvaddr = (vaddr_t)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 242 243 memset(fb, 0, sizeof(struct hpcfb_fbconf)); 244 245 fb->hf_conf_index = 0; /* configuration index */ 246 fb->hf_nconfs = 1; /* how many configurations */ 247 strncpy(fb->hf_name, "TX3912 built-in video", HPCFB_MAXNAMELEN); 248 /* frame buffer name */ 249 strncpy(fb->hf_conf_name, "LCD", HPCFB_MAXNAMELEN); 250 /* configuration name */ 251 fb->hf_height = chip->vc_fbheight; 252 fb->hf_width = chip->vc_fbwidth; 253 fb->hf_baseaddr = (u_long)fbvaddr; 254 fb->hf_offset = (u_long)fbvaddr - 255 mips_ptob(mips_btop(fbvaddr)); 256 /* frame buffer start offset */ 257 fb->hf_bytes_per_line = (chip->vc_fbwidth * chip->vc_fbdepth) 258 / NBBY; 259 fb->hf_nplanes = 1; 260 fb->hf_bytes_per_plane = chip->vc_fbheight * fb->hf_bytes_per_line; 261 262 fb->hf_access_flags |= HPCFB_ACCESS_BYTE; 263 fb->hf_access_flags |= HPCFB_ACCESS_WORD; 264 fb->hf_access_flags |= HPCFB_ACCESS_DWORD; 265 if (video_reverse_color()) 266 fb->hf_access_flags |= HPCFB_ACCESS_REVERSE; 267 268 269 switch (chip->vc_fbdepth) { 270 default: 271 panic("tx3912video_hpcfbinit: not supported color depth"); 272 /* NOTREACHED */ 273 case 2: 274 fb->hf_class = HPCFB_CLASS_GRAYSCALE; 275 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 276 fb->hf_pack_width = 8; 277 fb->hf_pixels_per_pack = 4; 278 fb->hf_pixel_width = 2; 279 fb->hf_class_data_length = sizeof(struct hf_gray_tag); 280 /* reserved for future use */ 281 fb->hf_u.hf_gray.hf_flags = 0; 282 break; 283 case 8: 284 fb->hf_class = HPCFB_CLASS_INDEXCOLOR; 285 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 286 fb->hf_pack_width = 8; 287 fb->hf_pixels_per_pack = 1; 288 fb->hf_pixel_width = 8; 289 fb->hf_class_data_length = sizeof(struct hf_indexed_tag); 290 /* reserved for future use */ 291 fb->hf_u.hf_indexed.hf_flags = 0; 292 break; 293 } 294 } 295 296 int 297 tx3912video_init(paddr_t fb_start, paddr_t *fb_end) 298 { 299 struct video_chip *chip = &tx3912video_chip; 300 tx_chipset_tag_t tc; 301 txreg_t reg; 302 int fbdepth, reverse, error; 303 304 reverse = video_reverse_color(); 305 chip->vc_v = tc = tx_conf_get_tag(); 306 307 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 308 fbdepth = 1 << (TX3912_VIDEOCTRL1_BITSEL(reg)); 309 310 switch (fbdepth) { 311 case 2: 312 bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; 313 break; 314 case 4: 315 /* XXX should implement rasops4.c */ 316 fbdepth = 2; 317 bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; 318 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 319 TX3912_VIDEOCTRL1_BITSEL_CLR(reg); 320 reg = TX3912_VIDEOCTRL1_BITSEL_SET(reg, 321 TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE); 322 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 323 break; 324 case 8: 325 bootinfo->fb_type = reverse ? BIFB_D8_FF : BIFB_D8_00; 326 break; 327 } 328 329 chip->vc_fbdepth = fbdepth; 330 chip->vc_fbwidth = bootinfo->fb_width; 331 chip->vc_fbheight= bootinfo->fb_height; 332 333 /* Allocate framebuffer area */ 334 error = tx3912video_framebuffer_alloc(chip, fb_start, fb_end); 335 if (error != 0) 336 return (1); 337 338 #if notyet 339 tx3912video_resolution_init(chip); 340 #else 341 /* Use Windows CE setting. */ 342 #endif 343 /* Set DMA transfer address to VID module */ 344 tx3912video_framebuffer_init(chip); 345 346 /* Syncronize framebuffer addr to frame signal */ 347 tx3912video_reset(chip); 348 349 bootinfo->fb_line_bytes = (chip->vc_fbwidth * fbdepth) / NBBY; 350 bootinfo->fb_addr = (void *)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 351 352 return (0); 353 } 354 355 int 356 tx3912video_framebuffer_alloc(struct video_chip *chip, paddr_t fb_start, 357 paddr_t *fb_end /* buffer allocation hint */) 358 { 359 struct extent_fixed ex_fixed[10]; 360 struct extent *ex; 361 u_long addr, size; 362 int error; 363 364 /* calcurate frame buffer size */ 365 size = (chip->vc_fbwidth * chip->vc_fbheight * chip->vc_fbdepth) / 366 NBBY; 367 368 /* extent V-RAM region */ 369 ex = extent_create("Frame buffer address", fb_start, *fb_end, 370 (void *)ex_fixed, sizeof ex_fixed, 371 EX_NOWAIT); 372 if (ex == 0) 373 return (1); 374 375 /* Allocate V-RAM area */ 376 error = extent_alloc_subregion(ex, fb_start, fb_start + size - 1, 377 size, TX3912_FRAMEBUFFER_ALIGNMENT, 378 TX3912_FRAMEBUFFER_BOUNDARY, EX_FAST|EX_NOWAIT, &addr); 379 extent_destroy(ex); 380 381 if (error != 0) 382 return (1); 383 384 chip->vc_fbpaddr = addr; 385 chip->vc_fbvaddr = MIPS_PHYS_TO_KSEG1(addr); 386 chip->vc_fbsize = size; 387 388 *fb_end = addr + size; 389 390 return (0); 391 } 392 393 void 394 tx3912video_framebuffer_init(struct video_chip *chip) 395 { 396 u_int32_t fb_addr, fb_size, vaddr, bank, base; 397 txreg_t reg; 398 tx_chipset_tag_t tc = chip->vc_v; 399 400 fb_addr = chip->vc_fbpaddr; 401 fb_size = chip->vc_fbsize; 402 403 /* XXX currently I don't set DFVAL, so force DF signal toggled on 404 * XXX each frame. */ 405 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 406 reg &= ~TX3912_VIDEOCTRL1_DFMODE; 407 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 408 409 /* Set DMA transfer start and end address */ 410 411 bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr); 412 base = TX3912_VIDEOCTRL3_VIDBASEHI(fb_addr); 413 reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank); 414 /* Upper address counter */ 415 reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base); 416 tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg); 417 418 /* Lower address counter */ 419 base = TX3912_VIDEOCTRL4_VIDBASELO(fb_addr + fb_size); 420 reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base); 421 422 /* Set DF-signal rate */ 423 reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/ 424 425 /* Set VIDDONE signal delay after FRAME signal */ 426 /* XXX not yet*/ 427 tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg); 428 429 /* Clear frame buffer */ 430 vaddr = MIPS_PHYS_TO_KSEG1(fb_addr); 431 memset((void*)vaddr, 0, fb_size); 432 } 433 434 void 435 tx3912video_resolution_init(struct video_chip *chip) 436 { 437 int h, v, split, horzval, lineval; 438 tx_chipset_tag_t tc = chip->vc_v; 439 txreg_t reg; 440 u_int32_t val; 441 442 h = chip->vc_fbwidth; 443 v = chip->vc_fbheight; 444 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 445 split = reg & TX3912_VIDEOCTRL1_DISPSPLIT; 446 val = TX3912_VIDEOCTRL1_BITSEL(reg); 447 448 if ((val == TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR) && !split) { 449 /* (LCD horizontal pixels / 8bit) * RGB - 1 */ 450 horzval = (h / 8) * 3 - 1; 451 } else { 452 horzval = h / 4 - 1; 453 } 454 lineval = (split ? v / 2 : v) - 1; 455 456 /* Video rate */ 457 /* XXX 458 * probably This value should be determined from DFINT and LCDINT 459 */ 460 reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1); 461 /* Horizontal size of LCD */ 462 reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval); 463 /* # of lines for the LCD */ 464 reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval); 465 466 tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg); 467 } 468 469 void 470 tx3912video_reset(struct video_chip *chip) 471 { 472 tx_chipset_tag_t tc = chip->vc_v; 473 txreg_t reg; 474 475 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 476 477 /* Disable video logic at end of this frame */ 478 reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME; 479 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 480 481 /* Wait for end of frame */ 482 delay(30 * 1000); 483 484 /* Make sure to disable video logic */ 485 reg &= ~TX3912_VIDEOCTRL1_ENVID; 486 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 487 488 delay(1000); 489 490 /* Enable video logic again */ 491 reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME; 492 reg |= TX3912_VIDEOCTRL1_ENVID; 493 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 494 495 delay(1000); 496 } 497 498 int 499 tx3912video_ioctl(void *v, u_long cmd, void *data, int flag, struct lwp *l) 500 { 501 struct tx3912video_softc *sc = (struct tx3912video_softc *)v; 502 struct hpcfb_fbconf *fbconf; 503 struct hpcfb_dspconf *dspconf; 504 struct wsdisplay_cmap *cmap; 505 u_int8_t *r, *g, *b; 506 u_int32_t *rgb; 507 int idx, cnt, error; 508 509 switch (cmd) { 510 case WSDISPLAYIO_GETCMAP: 511 cmap = (struct wsdisplay_cmap *)data; 512 cnt = cmap->count; 513 idx = cmap->index; 514 515 if (sc->sc_fbconf.hf_class != HPCFB_CLASS_INDEXCOLOR || 516 sc->sc_fbconf.hf_pack_width != 8 || 517 !LEGAL_CLUT_INDEX(idx) || 518 !LEGAL_CLUT_INDEX(idx + cnt - 1)) { 519 return (EINVAL); 520 } 521 522 error = cmap_work_alloc(&r, &g, &b, &rgb, cnt); 523 if (error) 524 goto out; 525 tx3912video_clut_get(sc, rgb, idx, cnt); 526 rgb24_decompose(rgb, r, g, b, cnt); 527 528 error = copyout(r, cmap->red, cnt); 529 if (error) 530 goto out; 531 error = copyout(g, cmap->green,cnt); 532 if (error) 533 goto out; 534 error = copyout(b, cmap->blue, cnt); 535 536 out: 537 cmap_work_free(r, g, b, rgb); 538 return error; 539 540 case WSDISPLAYIO_PUTCMAP: 541 /* 542 * TX3912 can't change CLUT index. R:G:B = 3:3:2 543 */ 544 return (0); 545 546 case HPCFBIO_GCONF: 547 fbconf = (struct hpcfb_fbconf *)data; 548 if (fbconf->hf_conf_index != 0 && 549 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 550 return (EINVAL); 551 } 552 *fbconf = sc->sc_fbconf; /* structure assignment */ 553 return (0); 554 555 case HPCFBIO_SCONF: 556 fbconf = (struct hpcfb_fbconf *)data; 557 if (fbconf->hf_conf_index != 0 && 558 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 559 return (EINVAL); 560 } 561 /* 562 * nothing to do because we have only one configuration 563 */ 564 return (0); 565 566 case HPCFBIO_GDSPCONF: 567 dspconf = (struct hpcfb_dspconf *)data; 568 if ((dspconf->hd_unit_index != 0 && 569 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 570 (dspconf->hd_conf_index != 0 && 571 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 572 return (EINVAL); 573 } 574 *dspconf = sc->sc_dspconf; /* structure assignment */ 575 return (0); 576 577 case HPCFBIO_SDSPCONF: 578 dspconf = (struct hpcfb_dspconf *)data; 579 if ((dspconf->hd_unit_index != 0 && 580 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 581 (dspconf->hd_conf_index != 0 && 582 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 583 return (EINVAL); 584 } 585 /* 586 * nothing to do 587 * because we have only one unit and one configuration 588 */ 589 return (0); 590 591 case HPCFBIO_GOP: 592 case HPCFBIO_SOP: 593 /* XXX not implemented yet */ 594 return (EINVAL); 595 } 596 597 return (EPASSTHROUGH); 598 } 599 600 paddr_t 601 tx3912video_mmap(void *ctx, off_t offset, int prot) 602 { 603 struct tx3912video_softc *sc = (struct tx3912video_softc *)ctx; 604 605 if (offset < 0 || (sc->sc_fbconf.hf_bytes_per_plane + 606 sc->sc_fbconf.hf_offset) < offset) { 607 return (-1); 608 } 609 610 return (mips_btop(sc->sc_chip->vc_fbpaddr + offset)); 611 } 612 613 /* 614 * CLUT staff 615 */ 616 static const struct { 617 int mul, div; 618 } dither_list [] = { 619 [TX3912_VIDEO_DITHER_DUTYCYCLE_1] = { 1, 1 }, 620 [TX3912_VIDEO_DITHER_DUTYCYCLE_6_7] = { 6, 7 }, 621 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_5] = { 4, 5 }, 622 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_4] = { 3, 4 }, 623 [TX3912_VIDEO_DITHER_DUTYCYCLE_5_7] = { 5, 7 }, 624 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_3] = { 2, 3 }, 625 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_5] = { 3, 5 }, 626 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_7] = { 4, 7 }, 627 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_4] = { 2, 4 }, 628 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_7] = { 3, 7 }, 629 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_5] = { 2, 5 }, 630 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_3] = { 1, 3 }, 631 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_7] = { 2, 7 }, 632 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_5] = { 1, 5 }, 633 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_7] = { 1, 7 }, 634 [TX3912_VIDEO_DITHER_DUTYCYCLE_0] = { 0, 1 } 635 }, *dlp; 636 637 static const int dither_level8[8] = { 638 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 639 TX3912_VIDEO_DITHER_DUTYCYCLE_2_7, 640 TX3912_VIDEO_DITHER_DUTYCYCLE_2_5, 641 TX3912_VIDEO_DITHER_DUTYCYCLE_2_4, 642 TX3912_VIDEO_DITHER_DUTYCYCLE_3_5, 643 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 644 TX3912_VIDEO_DITHER_DUTYCYCLE_4_5, 645 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 646 }; 647 648 static const int dither_level4[4] = { 649 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 650 TX3912_VIDEO_DITHER_DUTYCYCLE_1_3, 651 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 652 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 653 }; 654 655 static int 656 __get_color8(int luti) 657 { 658 KASSERT(luti >=0 && luti < 8); 659 dlp = &dither_list[dither_level8[luti]]; 660 661 return ((0xff * dlp->mul) / dlp->div); 662 } 663 664 static int 665 __get_color4(int luti) 666 { 667 KASSERT(luti >=0 && luti < 4); 668 dlp = &dither_list[dither_level4[luti]]; 669 670 return ((0xff * dlp->mul) / dlp->div); 671 } 672 673 void 674 tx3912video_clut_get(struct tx3912video_softc *sc, u_int32_t *rgb, int beg, 675 int cnt) 676 { 677 int i; 678 679 KASSERT(rgb); 680 KASSERT(LEGAL_CLUT_INDEX(beg)); 681 KASSERT(LEGAL_CLUT_INDEX(beg + cnt - 1)); 682 683 for (i = beg; i < beg + cnt; i++) { 684 *rgb++ = RGB24(__get_color8((i >> 5) & 0x7), 685 __get_color8((i >> 2) & 0x7), 686 __get_color4(i & 0x3)); 687 } 688 } 689 690 void 691 tx3912video_clut_install(void *ctx, struct rasops_info *ri) 692 { 693 struct tx3912video_softc *sc = ctx; 694 static const int system_cmap[0x10] = { 695 TX3912VIDEO_BLACK, 696 TX3912VIDEO_RED, 697 TX3912VIDEO_GREEN, 698 TX3912VIDEO_YELLOW, 699 TX3912VIDEO_BLUE, 700 TX3912VIDEO_MAGENTA, 701 TX3912VIDEO_CYAN, 702 TX3912VIDEO_WHITE, 703 TX3912VIDEO_DARK_BLACK, 704 TX3912VIDEO_DARK_RED, 705 TX3912VIDEO_DARK_GREEN, 706 TX3912VIDEO_DARK_YELLOW, 707 TX3912VIDEO_DARK_BLUE, 708 TX3912VIDEO_DARK_MAGENTA, 709 TX3912VIDEO_DARK_CYAN, 710 TX3912VIDEO_DARK_WHITE, 711 }; 712 713 KASSERT(ri); 714 715 if (sc->sc_chip->vc_fbdepth == 8) { 716 /* XXX 2bit gray scale LUT not supported */ 717 memcpy(ri->ri_devcmap, system_cmap, sizeof system_cmap); 718 } 719 } 720 721 void 722 tx3912video_clut_init(struct tx3912video_softc *sc) 723 { 724 tx_chipset_tag_t tc = sc->sc_chip->vc_v; 725 726 if (sc->sc_chip->vc_fbdepth != 8) { 727 return; /* XXX 2bit gray scale LUT not supported */ 728 } 729 730 /* 731 * time-based dithering pattern (TOSHIBA recommended pattern) 732 */ 733 /* 2/3, 1/3 */ 734 tx_conf_write(tc, TX3912_VIDEOCTRL8_REG, 735 TX3912_VIDEOCTRL8_PAT2_3_DEFAULT); 736 /* 3/4, 2/4 */ 737 tx_conf_write(tc, TX3912_VIDEOCTRL9_REG, 738 (TX3912_VIDEOCTRL9_PAT3_4_DEFAULT << 16) | 739 TX3912_VIDEOCTRL9_PAT2_4_DEFAULT); 740 /* 4/5, 1/5 */ 741 tx_conf_write(tc, TX3912_VIDEOCTRL10_REG, 742 TX3912_VIDEOCTRL10_PAT4_5_DEFAULT); 743 /* 3/5, 2/5 */ 744 tx_conf_write(tc, TX3912_VIDEOCTRL11_REG, 745 TX3912_VIDEOCTRL11_PAT3_5_DEFAULT); 746 /* 6/7, 1/7 */ 747 tx_conf_write(tc, TX3912_VIDEOCTRL12_REG, 748 TX3912_VIDEOCTRL12_PAT6_7_DEFAULT); 749 /* 5/7, 2/7 */ 750 tx_conf_write(tc, TX3912_VIDEOCTRL13_REG, 751 TX3912_VIDEOCTRL13_PAT5_7_DEFAULT); 752 /* 4/7, 3/7 */ 753 tx_conf_write(tc, TX3912_VIDEOCTRL14_REG, 754 TX3912_VIDEOCTRL14_PAT4_7_DEFAULT); 755 756 /* 757 * dither-pattern look-up table. (selected by uch) 758 */ 759 /* red */ 760 tx_conf_write(tc, TX3912_VIDEOCTRL5_REG, 761 (dither_level8[7] << 28) | 762 (dither_level8[6] << 24) | 763 (dither_level8[5] << 20) | 764 (dither_level8[4] << 16) | 765 (dither_level8[3] << 12) | 766 (dither_level8[2] << 8) | 767 (dither_level8[1] << 4) | 768 (dither_level8[0] << 0)); 769 /* green */ 770 tx_conf_write(tc, TX3912_VIDEOCTRL6_REG, 771 (dither_level8[7] << 28) | 772 (dither_level8[6] << 24) | 773 (dither_level8[5] << 20) | 774 (dither_level8[4] << 16) | 775 (dither_level8[3] << 12) | 776 (dither_level8[2] << 8) | 777 (dither_level8[1] << 4) | 778 (dither_level8[0] << 0)); 779 /* blue (2bit gray scale also use this look-up table) */ 780 tx_conf_write(tc, TX3912_VIDEOCTRL7_REG, 781 (dither_level4[3] << 12) | 782 (dither_level4[2] << 8) | 783 (dither_level4[1] << 4) | 784 (dither_level4[0] << 0)); 785 786 tx3912video_reset(sc->sc_chip); 787 } 788
Indexes created Thu Nov 06 21:09:53 GMT 2025