tx3912video.c revision 1.43.4.1
1 /* $NetBSD: tx3912video.c,v 1.43.4.1 2016/07/09 20:24:52 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tx3912video.c,v 1.43.4.1 2016/07/09 20:24:52 skrll Exp $"); 34 35 #define TX3912VIDEO_DEBUG 36 37 #include "hpcfb.h" 38 #include "bivideo.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/buf.h> 43 #include <sys/device.h> 44 #include <sys/extent.h> 45 #include <sys/ioctl.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <dev/cons.h> /* consdev */ 50 51 #include <machine/bus.h> 52 #include <machine/bootinfo.h> 53 #include <machine/config_hook.h> 54 55 #include <hpcmips/tx/tx39var.h> 56 #include <hpcmips/tx/tx3912videovar.h> 57 #include <hpcmips/tx/tx3912videoreg.h> 58 59 /* CLUT */ 60 #include <dev/wscons/wsdisplayvar.h> 61 #include <dev/rasops/rasops.h> 62 #include <dev/hpc/video_subr.h> 63 64 #include <dev/wscons/wsconsio.h> 65 #include <dev/hpc/hpcfbvar.h> 66 #include <dev/hpc/hpcfbio.h> 67 #if NBIVIDEO > 0 68 #include <dev/hpc/bivideovar.h> 69 #endif 70 71 #ifdef TX3912VIDEO_DEBUG 72 int tx3912video_debug = 1; 73 #define DPRINTF(arg) if (tx3912video_debug) printf arg; 74 #define DPRINTFN(n, arg) if (tx3912video_debug > (n)) printf arg; 75 #else 76 #define DPRINTF(arg) 77 #define DPRINTFN(n, arg) 78 #endif 79 80 struct tx3912video_softc { 81 device_t sc_dev; 82 void *sc_powerhook; /* power management hook */ 83 int sc_console; 84 struct hpcfb_fbconf sc_fbconf; 85 struct hpcfb_dspconf sc_dspconf; 86 struct video_chip *sc_chip; 87 }; 88 89 /* TX3912 built-in video chip itself */ 90 static struct video_chip tx3912video_chip; 91 92 int tx3912video_power(void *, int, long, void *); 93 void tx3912video_framebuffer_init(struct video_chip *); 94 int tx3912video_framebuffer_alloc(struct video_chip *, paddr_t, paddr_t *); 95 void tx3912video_reset(struct video_chip *); 96 void tx3912video_resolution_init(struct video_chip *); 97 int tx3912video_match(device_t, cfdata_t, void *); 98 void tx3912video_attach(device_t, device_t, void *); 99 int tx3912video_print(void *, const char *); 100 101 void tx3912video_hpcfbinit(struct tx3912video_softc *); 102 int tx3912video_ioctl(void *, u_long, void *, int, struct lwp *); 103 paddr_t tx3912video_mmap(void *, off_t, int); 104 105 void tx3912video_clut_init(struct tx3912video_softc *); 106 void tx3912video_clut_install(void *, struct rasops_info *); 107 void tx3912video_clut_get(struct tx3912video_softc *, u_int32_t *, int, 108 int); 109 110 static int __get_color8(int); 111 static int __get_color4(int); 112 113 CFATTACH_DECL_NEW(tx3912video, sizeof(struct tx3912video_softc), 114 tx3912video_match, tx3912video_attach, NULL, NULL); 115 116 struct hpcfb_accessops tx3912video_ha = { 117 tx3912video_ioctl, tx3912video_mmap, 0, 0, 0, 0, 118 tx3912video_clut_install 119 }; 120 121 int 122 tx3912video_match(device_t parent, cfdata_t cf, void *aux) 123 { 124 return (ATTACH_NORMAL); 125 } 126 127 void 128 tx3912video_attach(device_t parent, device_t self, void *aux) 129 { 130 struct tx3912video_softc *sc = device_private(self); 131 struct video_chip *chip; 132 static const char *const depth_print[] = { 133 [TX3912_VIDEOCTRL1_BITSEL_MONOCHROME] = "monochrome", 134 [TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE] = "2bit greyscale", 135 [TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE] = "4bit greyscale", 136 [TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR] = "8bit color" 137 }; 138 struct hpcfb_attach_args ha; 139 tx_chipset_tag_t tc; 140 txreg_t val; 141 int console; 142 143 sc->sc_dev = self; 144 sc->sc_console = console = cn_tab ? 0 : 1; 145 sc->sc_chip = chip = &tx3912video_chip; 146 147 /* print video module information */ 148 printf(": %s, frame buffer 0x%08x-0x%08x\n", 149 depth_print[(ffs(chip->vc_fbdepth) - 1) & 0x3], 150 (unsigned)chip->vc_fbpaddr, 151 (unsigned)(chip->vc_fbpaddr + chip->vc_fbsize)); 152 153 /* don't inverse VDAT[3:0] signal */ 154 tc = chip->vc_v; 155 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 156 val &= ~TX3912_VIDEOCTRL1_INVVID; 157 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 158 159 /* install default CLUT */ 160 tx3912video_clut_init(sc); 161 162 /* if serial console, power off video module */ 163 tx3912video_power(sc, 0, 0, (void *) 164 (console ? PWR_RESUME : PWR_SUSPEND)); 165 166 /* Add a hard power hook to power saving */ 167 sc->sc_powerhook = config_hook(CONFIG_HOOK_PMEVENT, 168 CONFIG_HOOK_PMEVENT_HARDPOWER, CONFIG_HOOK_SHARE, 169 tx3912video_power, sc); 170 if (sc->sc_powerhook == 0) 171 printf("WARNING unable to establish hard power hook"); 172 173 #ifdef TX3912VIDEO_DEBUG 174 /* attach debug draw routine (debugging use) */ 175 video_attach_drawfunc(sc->sc_chip); 176 tx_conf_register_video(tc, sc->sc_chip); 177 #endif 178 179 /* Attach frame buffer device */ 180 tx3912video_hpcfbinit(sc); 181 182 if (console && hpcfb_cnattach(&sc->sc_fbconf) != 0) { 183 panic("tx3912video_attach: can't init fb console"); 184 } 185 186 ha.ha_console = console; 187 ha.ha_accessops = &tx3912video_ha; 188 ha.ha_accessctx = sc; 189 ha.ha_curfbconf = 0; 190 ha.ha_nfbconf = 1; 191 ha.ha_fbconflist = &sc->sc_fbconf; 192 ha.ha_curdspconf = 0; 193 ha.ha_ndspconf = 1; 194 ha.ha_dspconflist = &sc->sc_dspconf; 195 196 config_found(self, &ha, hpcfbprint); 197 #if NBIVIDEO > 0 198 /* bivideo is no longer need */ 199 bivideo_dont_attach = 1; 200 #endif /* NBIVIDEO > 0 */ 201 } 202 203 int 204 tx3912video_power(void *ctx, int type, long id, void *msg) 205 { 206 struct tx3912video_softc *sc = ctx; 207 struct video_chip *chip = sc->sc_chip; 208 tx_chipset_tag_t tc = chip->vc_v; 209 int why = (int)msg; 210 txreg_t val; 211 212 switch (why) { 213 case PWR_RESUME: 214 if (!sc->sc_console) 215 return (0); /* serial console */ 216 217 DPRINTF(("%s: ON\n", device_xname(sc->sc_dev))); 218 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 219 val |= (TX3912_VIDEOCTRL1_DISPON | TX3912_VIDEOCTRL1_ENVID); 220 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 221 break; 222 case PWR_SUSPEND: 223 /* FALLTHROUGH */ 224 case PWR_STANDBY: 225 DPRINTF(("%s: OFF\n", device_xname(sc->sc_dev))); 226 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 227 val &= ~(TX3912_VIDEOCTRL1_DISPON | TX3912_VIDEOCTRL1_ENVID); 228 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val); 229 break; 230 } 231 232 return (0); 233 } 234 235 void 236 tx3912video_hpcfbinit(struct tx3912video_softc *sc) 237 { 238 struct video_chip *chip = sc->sc_chip; 239 struct hpcfb_fbconf *fb = &sc->sc_fbconf; 240 vaddr_t fbvaddr = (vaddr_t)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 241 242 memset(fb, 0, sizeof(struct hpcfb_fbconf)); 243 244 fb->hf_conf_index = 0; /* configuration index */ 245 fb->hf_nconfs = 1; /* how many configurations */ 246 strncpy(fb->hf_name, "TX3912 built-in video", HPCFB_MAXNAMELEN); 247 /* frame buffer name */ 248 strncpy(fb->hf_conf_name, "LCD", HPCFB_MAXNAMELEN); 249 /* configuration name */ 250 fb->hf_height = chip->vc_fbheight; 251 fb->hf_width = chip->vc_fbwidth; 252 fb->hf_baseaddr = (u_long)fbvaddr; 253 fb->hf_offset = (u_long)fbvaddr - 254 mips_ptob(mips_btop(fbvaddr)); 255 /* frame buffer start offset */ 256 fb->hf_bytes_per_line = (chip->vc_fbwidth * chip->vc_fbdepth) 257 / NBBY; 258 fb->hf_nplanes = 1; 259 fb->hf_bytes_per_plane = chip->vc_fbheight * fb->hf_bytes_per_line; 260 261 fb->hf_access_flags |= HPCFB_ACCESS_BYTE; 262 fb->hf_access_flags |= HPCFB_ACCESS_WORD; 263 fb->hf_access_flags |= HPCFB_ACCESS_DWORD; 264 if (video_reverse_color()) 265 fb->hf_access_flags |= HPCFB_ACCESS_REVERSE; 266 267 268 switch (chip->vc_fbdepth) { 269 default: 270 panic("tx3912video_hpcfbinit: not supported color depth"); 271 /* NOTREACHED */ 272 case 2: 273 fb->hf_class = HPCFB_CLASS_GRAYSCALE; 274 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 275 fb->hf_pack_width = 8; 276 fb->hf_pixels_per_pack = 4; 277 fb->hf_pixel_width = 2; 278 fb->hf_class_data_length = sizeof(struct hf_gray_tag); 279 /* reserved for future use */ 280 fb->hf_u.hf_gray.hf_flags = 0; 281 break; 282 case 8: 283 fb->hf_class = HPCFB_CLASS_INDEXCOLOR; 284 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 285 fb->hf_pack_width = 8; 286 fb->hf_pixels_per_pack = 1; 287 fb->hf_pixel_width = 8; 288 fb->hf_class_data_length = sizeof(struct hf_indexed_tag); 289 /* reserved for future use */ 290 fb->hf_u.hf_indexed.hf_flags = 0; 291 break; 292 } 293 } 294 295 int 296 tx3912video_init(paddr_t fb_start, paddr_t *fb_end) 297 { 298 struct video_chip *chip = &tx3912video_chip; 299 tx_chipset_tag_t tc; 300 txreg_t reg; 301 int fbdepth, reverse, error; 302 303 reverse = video_reverse_color(); 304 chip->vc_v = tc = tx_conf_get_tag(); 305 306 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 307 fbdepth = 1 << (TX3912_VIDEOCTRL1_BITSEL(reg)); 308 309 switch (fbdepth) { 310 case 2: 311 bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; 312 break; 313 case 4: 314 /* XXX should implement rasops4.c */ 315 fbdepth = 2; 316 bootinfo->fb_type = reverse ? BIFB_D2_M2L_3 : BIFB_D2_M2L_0; 317 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 318 TX3912_VIDEOCTRL1_BITSEL_CLR(reg); 319 reg = TX3912_VIDEOCTRL1_BITSEL_SET(reg, 320 TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE); 321 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 322 break; 323 case 8: 324 bootinfo->fb_type = reverse ? BIFB_D8_FF : BIFB_D8_00; 325 break; 326 } 327 328 chip->vc_fbdepth = fbdepth; 329 chip->vc_fbwidth = bootinfo->fb_width; 330 chip->vc_fbheight= bootinfo->fb_height; 331 332 /* Allocate framebuffer area */ 333 error = tx3912video_framebuffer_alloc(chip, fb_start, fb_end); 334 if (error != 0) 335 return (1); 336 337 #if notyet 338 tx3912video_resolution_init(chip); 339 #else 340 /* Use Windows CE setting. */ 341 #endif 342 /* Set DMA transfer address to VID module */ 343 tx3912video_framebuffer_init(chip); 344 345 /* Syncronize framebuffer addr to frame signal */ 346 tx3912video_reset(chip); 347 348 bootinfo->fb_line_bytes = (chip->vc_fbwidth * fbdepth) / NBBY; 349 bootinfo->fb_addr = (void *)MIPS_PHYS_TO_KSEG1(chip->vc_fbpaddr); 350 351 return (0); 352 } 353 354 int 355 tx3912video_framebuffer_alloc(struct video_chip *chip, paddr_t fb_start, 356 paddr_t *fb_end /* buffer allocation hint */) 357 { 358 struct extent_fixed ex_fixed[10]; 359 struct extent *ex; 360 u_long addr, size; 361 int error; 362 363 /* calcurate frame buffer size */ 364 size = (chip->vc_fbwidth * chip->vc_fbheight * chip->vc_fbdepth) / 365 NBBY; 366 367 /* extent V-RAM region */ 368 ex = extent_create("Frame buffer address", fb_start, *fb_end, 369 (void *)ex_fixed, sizeof ex_fixed, 370 EX_NOWAIT); 371 if (ex == 0) 372 return (1); 373 374 /* Allocate V-RAM area */ 375 error = extent_alloc_subregion(ex, fb_start, fb_start + size - 1, 376 size, TX3912_FRAMEBUFFER_ALIGNMENT, 377 TX3912_FRAMEBUFFER_BOUNDARY, EX_FAST|EX_NOWAIT, &addr); 378 extent_destroy(ex); 379 380 if (error != 0) 381 return (1); 382 383 chip->vc_fbpaddr = addr; 384 chip->vc_fbvaddr = MIPS_PHYS_TO_KSEG1(addr); 385 chip->vc_fbsize = size; 386 387 *fb_end = addr + size; 388 389 return (0); 390 } 391 392 void 393 tx3912video_framebuffer_init(struct video_chip *chip) 394 { 395 u_int32_t fb_addr, fb_size, vaddr, bank, base; 396 txreg_t reg; 397 tx_chipset_tag_t tc = chip->vc_v; 398 399 fb_addr = chip->vc_fbpaddr; 400 fb_size = chip->vc_fbsize; 401 402 /* XXX currently I don't set DFVAL, so force DF signal toggled on 403 * XXX each frame. */ 404 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 405 reg &= ~TX3912_VIDEOCTRL1_DFMODE; 406 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 407 408 /* Set DMA transfer start and end address */ 409 410 bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr); 411 base = TX3912_VIDEOCTRL3_VIDBASEHI(fb_addr); 412 reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank); 413 /* Upper address counter */ 414 reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base); 415 tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg); 416 417 /* Lower address counter */ 418 base = TX3912_VIDEOCTRL4_VIDBASELO(fb_addr + fb_size); 419 reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base); 420 421 /* Set DF-signal rate */ 422 reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/ 423 424 /* Set VIDDONE signal delay after FRAME signal */ 425 /* XXX not yet*/ 426 tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg); 427 428 /* Clear frame buffer */ 429 vaddr = MIPS_PHYS_TO_KSEG1(fb_addr); 430 memset((void*)vaddr, 0, fb_size); 431 } 432 433 void 434 tx3912video_resolution_init(struct video_chip *chip) 435 { 436 int h, v, split, horzval, lineval; 437 tx_chipset_tag_t tc = chip->vc_v; 438 txreg_t reg; 439 u_int32_t val; 440 441 h = chip->vc_fbwidth; 442 v = chip->vc_fbheight; 443 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 444 split = reg & TX3912_VIDEOCTRL1_DISPSPLIT; 445 val = TX3912_VIDEOCTRL1_BITSEL(reg); 446 447 if ((val == TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR) && !split) { 448 /* (LCD horizontal pixels / 8bit) * RGB - 1 */ 449 horzval = (h / 8) * 3 - 1; 450 } else { 451 horzval = h / 4 - 1; 452 } 453 lineval = (split ? v / 2 : v) - 1; 454 455 /* Video rate */ 456 /* XXX 457 * probably This value should be determined from DFINT and LCDINT 458 */ 459 reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1); 460 /* Horizontal size of LCD */ 461 reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval); 462 /* # of lines for the LCD */ 463 reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval); 464 465 tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg); 466 } 467 468 void 469 tx3912video_reset(struct video_chip *chip) 470 { 471 tx_chipset_tag_t tc = chip->vc_v; 472 txreg_t reg; 473 474 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 475 476 /* Disable video logic at end of this frame */ 477 reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME; 478 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 479 480 /* Wait for end of frame */ 481 delay(30 * 1000); 482 483 /* Make sure to disable video logic */ 484 reg &= ~TX3912_VIDEOCTRL1_ENVID; 485 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 486 487 delay(1000); 488 489 /* Enable video logic again */ 490 reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME; 491 reg |= TX3912_VIDEOCTRL1_ENVID; 492 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 493 494 delay(1000); 495 } 496 497 int 498 tx3912video_ioctl(void *v, u_long cmd, void *data, int flag, struct lwp *l) 499 { 500 struct tx3912video_softc *sc = (struct tx3912video_softc *)v; 501 struct hpcfb_fbconf *fbconf; 502 struct hpcfb_dspconf *dspconf; 503 struct wsdisplay_cmap *cmap; 504 u_int8_t *r, *g, *b; 505 u_int32_t *rgb; 506 int idx, cnt, error; 507 508 switch (cmd) { 509 case WSDISPLAYIO_GETCMAP: 510 cmap = (struct wsdisplay_cmap *)data; 511 cnt = cmap->count; 512 idx = cmap->index; 513 514 if (sc->sc_fbconf.hf_class != HPCFB_CLASS_INDEXCOLOR || 515 sc->sc_fbconf.hf_pack_width != 8 || 516 !LEGAL_CLUT_INDEX(idx) || 517 !LEGAL_CLUT_INDEX(idx + cnt - 1)) { 518 return (EINVAL); 519 } 520 521 error = cmap_work_alloc(&r, &g, &b, &rgb, cnt); 522 if (error) 523 goto out; 524 tx3912video_clut_get(sc, rgb, idx, cnt); 525 rgb24_decompose(rgb, r, g, b, cnt); 526 527 error = copyout(r, cmap->red, cnt); 528 if (error) 529 goto out; 530 error = copyout(g, cmap->green,cnt); 531 if (error) 532 goto out; 533 error = copyout(b, cmap->blue, cnt); 534 535 out: 536 cmap_work_free(r, g, b, rgb); 537 return error; 538 539 case WSDISPLAYIO_PUTCMAP: 540 /* 541 * TX3912 can't change CLUT index. R:G:B = 3:3:2 542 */ 543 return (0); 544 545 case HPCFBIO_GCONF: 546 fbconf = (struct hpcfb_fbconf *)data; 547 if (fbconf->hf_conf_index != 0 && 548 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 549 return (EINVAL); 550 } 551 *fbconf = sc->sc_fbconf; /* structure assignment */ 552 return (0); 553 554 case HPCFBIO_SCONF: 555 fbconf = (struct hpcfb_fbconf *)data; 556 if (fbconf->hf_conf_index != 0 && 557 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 558 return (EINVAL); 559 } 560 /* 561 * nothing to do because we have only one configuration 562 */ 563 return (0); 564 565 case HPCFBIO_GDSPCONF: 566 dspconf = (struct hpcfb_dspconf *)data; 567 if ((dspconf->hd_unit_index != 0 && 568 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 569 (dspconf->hd_conf_index != 0 && 570 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 571 return (EINVAL); 572 } 573 *dspconf = sc->sc_dspconf; /* structure assignment */ 574 return (0); 575 576 case HPCFBIO_SDSPCONF: 577 dspconf = (struct hpcfb_dspconf *)data; 578 if ((dspconf->hd_unit_index != 0 && 579 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 580 (dspconf->hd_conf_index != 0 && 581 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 582 return (EINVAL); 583 } 584 /* 585 * nothing to do 586 * because we have only one unit and one configuration 587 */ 588 return (0); 589 590 case HPCFBIO_GOP: 591 case HPCFBIO_SOP: 592 /* XXX not implemented yet */ 593 return (EINVAL); 594 } 595 596 return (EPASSTHROUGH); 597 } 598 599 paddr_t 600 tx3912video_mmap(void *ctx, off_t offset, int prot) 601 { 602 struct tx3912video_softc *sc = (struct tx3912video_softc *)ctx; 603 604 if (offset < 0 || (sc->sc_fbconf.hf_bytes_per_plane + 605 sc->sc_fbconf.hf_offset) < offset) { 606 return (-1); 607 } 608 609 return (mips_btop(sc->sc_chip->vc_fbpaddr + offset)); 610 } 611 612 /* 613 * CLUT staff 614 */ 615 static const struct { 616 int mul, div; 617 } dither_list [] = { 618 [TX3912_VIDEO_DITHER_DUTYCYCLE_1] = { 1, 1 }, 619 [TX3912_VIDEO_DITHER_DUTYCYCLE_6_7] = { 6, 7 }, 620 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_5] = { 4, 5 }, 621 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_4] = { 3, 4 }, 622 [TX3912_VIDEO_DITHER_DUTYCYCLE_5_7] = { 5, 7 }, 623 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_3] = { 2, 3 }, 624 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_5] = { 3, 5 }, 625 [TX3912_VIDEO_DITHER_DUTYCYCLE_4_7] = { 4, 7 }, 626 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_4] = { 2, 4 }, 627 [TX3912_VIDEO_DITHER_DUTYCYCLE_3_7] = { 3, 7 }, 628 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_5] = { 2, 5 }, 629 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_3] = { 1, 3 }, 630 [TX3912_VIDEO_DITHER_DUTYCYCLE_2_7] = { 2, 7 }, 631 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_5] = { 1, 5 }, 632 [TX3912_VIDEO_DITHER_DUTYCYCLE_1_7] = { 1, 7 }, 633 [TX3912_VIDEO_DITHER_DUTYCYCLE_0] = { 0, 1 } 634 }, *dlp; 635 636 static const int dither_level8[8] = { 637 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 638 TX3912_VIDEO_DITHER_DUTYCYCLE_2_7, 639 TX3912_VIDEO_DITHER_DUTYCYCLE_2_5, 640 TX3912_VIDEO_DITHER_DUTYCYCLE_2_4, 641 TX3912_VIDEO_DITHER_DUTYCYCLE_3_5, 642 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 643 TX3912_VIDEO_DITHER_DUTYCYCLE_4_5, 644 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 645 }; 646 647 static const int dither_level4[4] = { 648 TX3912_VIDEO_DITHER_DUTYCYCLE_0, 649 TX3912_VIDEO_DITHER_DUTYCYCLE_1_3, 650 TX3912_VIDEO_DITHER_DUTYCYCLE_5_7, 651 TX3912_VIDEO_DITHER_DUTYCYCLE_1, 652 }; 653 654 static int 655 __get_color8(int luti) 656 { 657 KASSERT(luti >=0 && luti < 8); 658 dlp = &dither_list[dither_level8[luti]]; 659 660 return ((0xff * dlp->mul) / dlp->div); 661 } 662 663 static int 664 __get_color4(int luti) 665 { 666 KASSERT(luti >=0 && luti < 4); 667 dlp = &dither_list[dither_level4[luti]]; 668 669 return ((0xff * dlp->mul) / dlp->div); 670 } 671 672 void 673 tx3912video_clut_get(struct tx3912video_softc *sc, u_int32_t *rgb, int beg, 674 int cnt) 675 { 676 int i; 677 678 KASSERT(rgb); 679 KASSERT(LEGAL_CLUT_INDEX(beg)); 680 KASSERT(LEGAL_CLUT_INDEX(beg + cnt - 1)); 681 682 for (i = beg; i < beg + cnt; i++) { 683 *rgb++ = RGB24(__get_color8((i >> 5) & 0x7), 684 __get_color8((i >> 2) & 0x7), 685 __get_color4(i & 0x3)); 686 } 687 } 688 689 void 690 tx3912video_clut_install(void *ctx, struct rasops_info *ri) 691 { 692 struct tx3912video_softc *sc = ctx; 693 static const int system_cmap[0x10] = { 694 TX3912VIDEO_BLACK, 695 TX3912VIDEO_RED, 696 TX3912VIDEO_GREEN, 697 TX3912VIDEO_YELLOW, 698 TX3912VIDEO_BLUE, 699 TX3912VIDEO_MAGENTA, 700 TX3912VIDEO_CYAN, 701 TX3912VIDEO_WHITE, 702 TX3912VIDEO_DARK_BLACK, 703 TX3912VIDEO_DARK_RED, 704 TX3912VIDEO_DARK_GREEN, 705 TX3912VIDEO_DARK_YELLOW, 706 TX3912VIDEO_DARK_BLUE, 707 TX3912VIDEO_DARK_MAGENTA, 708 TX3912VIDEO_DARK_CYAN, 709 TX3912VIDEO_DARK_WHITE, 710 }; 711 712 KASSERT(ri); 713 714 if (sc->sc_chip->vc_fbdepth == 8) { 715 /* XXX 2bit gray scale LUT not supported */ 716 memcpy(ri->ri_devcmap, system_cmap, sizeof system_cmap); 717 } 718 } 719 720 void 721 tx3912video_clut_init(struct tx3912video_softc *sc) 722 { 723 tx_chipset_tag_t tc = sc->sc_chip->vc_v; 724 725 if (sc->sc_chip->vc_fbdepth != 8) { 726 return; /* XXX 2bit gray scale LUT not supported */ 727 } 728 729 /* 730 * time-based dithering pattern (TOSHIBA recommended pattern) 731 */ 732 /* 2/3, 1/3 */ 733 tx_conf_write(tc, TX3912_VIDEOCTRL8_REG, 734 TX3912_VIDEOCTRL8_PAT2_3_DEFAULT); 735 /* 3/4, 2/4 */ 736 tx_conf_write(tc, TX3912_VIDEOCTRL9_REG, 737 (TX3912_VIDEOCTRL9_PAT3_4_DEFAULT << 16) | 738 TX3912_VIDEOCTRL9_PAT2_4_DEFAULT); 739 /* 4/5, 1/5 */ 740 tx_conf_write(tc, TX3912_VIDEOCTRL10_REG, 741 TX3912_VIDEOCTRL10_PAT4_5_DEFAULT); 742 /* 3/5, 2/5 */ 743 tx_conf_write(tc, TX3912_VIDEOCTRL11_REG, 744 TX3912_VIDEOCTRL11_PAT3_5_DEFAULT); 745 /* 6/7, 1/7 */ 746 tx_conf_write(tc, TX3912_VIDEOCTRL12_REG, 747 TX3912_VIDEOCTRL12_PAT6_7_DEFAULT); 748 /* 5/7, 2/7 */ 749 tx_conf_write(tc, TX3912_VIDEOCTRL13_REG, 750 TX3912_VIDEOCTRL13_PAT5_7_DEFAULT); 751 /* 4/7, 3/7 */ 752 tx_conf_write(tc, TX3912_VIDEOCTRL14_REG, 753 TX3912_VIDEOCTRL14_PAT4_7_DEFAULT); 754 755 /* 756 * dither-pattern look-up table. (selected by uch) 757 */ 758 /* red */ 759 tx_conf_write(tc, TX3912_VIDEOCTRL5_REG, 760 (dither_level8[7] << 28) | 761 (dither_level8[6] << 24) | 762 (dither_level8[5] << 20) | 763 (dither_level8[4] << 16) | 764 (dither_level8[3] << 12) | 765 (dither_level8[2] << 8) | 766 (dither_level8[1] << 4) | 767 (dither_level8[0] << 0)); 768 /* green */ 769 tx_conf_write(tc, TX3912_VIDEOCTRL6_REG, 770 (dither_level8[7] << 28) | 771 (dither_level8[6] << 24) | 772 (dither_level8[5] << 20) | 773 (dither_level8[4] << 16) | 774 (dither_level8[3] << 12) | 775 (dither_level8[2] << 8) | 776 (dither_level8[1] << 4) | 777 (dither_level8[0] << 0)); 778 /* blue (2bit gray scale also use this look-up table) */ 779 tx_conf_write(tc, TX3912_VIDEOCTRL7_REG, 780 (dither_level4[3] << 12) | 781 (dither_level4[2] << 8) | 782 (dither_level4[1] << 4) | 783 (dither_level4[0] << 0)); 784 785 tx3912video_reset(sc->sc_chip); 786 } 787
Indexes created Thu Nov 06 21:09:53 GMT 2025