tx3912video.c revision 1.5
1 /* $NetBSD: tx3912video.c,v 1.5 2000/01/03 18:29:04 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include "opt_tx39_debug.h" 29 #include "fb.h" 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/device.h> 34 #include <sys/extent.h> 35 36 #include <machine/bus.h> 37 #include <machine/bootinfo.h> /* bootinfo */ 38 39 #include <hpcmips/tx/tx39var.h> 40 #include <hpcmips/tx/tx3912videovar.h> 41 #include <hpcmips/tx/tx3912videoreg.h> 42 43 #if NFB > 0 44 #include <dev/rcons/raster.h> 45 #include <dev/wscons/wsdisplayvar.h> 46 #include <arch/hpcmips/dev/fbvar.h> 47 #endif 48 49 void tx3912video_framebuffer_init __P((tx_chipset_tag_t, u_int32_t, 50 u_int32_t)); 51 int tx3912video_framebuffer_alloc __P((tx_chipset_tag_t, u_int32_t, 52 int, int, int, u_int32_t*, 53 u_int32_t*)); 54 void tx3912video_reset __P((tx_chipset_tag_t)); 55 void tx3912video_resolution_init __P((tx_chipset_tag_t, int, int)); 56 int tx3912video_fbdepth __P((tx_chipset_tag_t, int)); 57 58 static u_int32_t framebuffer, framebuffersize; 59 60 int tx3912video_match __P((struct device*, struct cfdata*, void*)); 61 void tx3912video_attach __P((struct device*, struct device*, void*)); 62 int tx3912video_print __P((void*, const char*)); 63 64 struct tx3912video_softc { 65 struct device sc_dev; 66 u_int32_t sc_fbaddr; 67 u_int32_t sc_fbsize; 68 }; 69 70 struct fb_attach_args { 71 const char *fba_name; 72 }; 73 74 struct cfattach tx3912video_ca = { 75 sizeof(struct tx3912video_softc), tx3912video_match, 76 tx3912video_attach 77 }; 78 79 int 80 tx3912video_match(parent, cf, aux) 81 struct device *parent; 82 struct cfdata *cf; 83 void *aux; 84 { 85 return 1; 86 } 87 88 void 89 tx3912video_attach(parent, self, aux) 90 struct device *parent; 91 struct device *self; 92 void *aux; 93 { 94 struct txsim_attach_args *ta = aux; 95 struct tx3912video_softc *sc = (void*)self; 96 tx_chipset_tag_t tc = ta->ta_tc; 97 struct fb_attach_args fba; 98 txreg_t reg; 99 100 sc->sc_fbaddr = framebuffer; 101 sc->sc_fbsize = framebuffersize; 102 103 printf(": "); 104 tx3912video_fbdepth(tc, 1); 105 printf(", frame buffer 0x%08x-0x%08x", sc->sc_fbaddr, 106 sc->sc_fbaddr + sc->sc_fbsize); 107 108 printf("\n"); 109 110 if (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) { 111 printf("%s: power off\n", sc->sc_dev.dv_xname); 112 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 113 reg &= ~(TX3912_VIDEOCTRL1_DISPON | 114 TX3912_VIDEOCTRL1_ENVID); 115 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 116 } 117 118 /* Attach frame buffer device */ 119 #if NFB > 0 120 if (!(bootinfo->bi_cnuse & BI_CNUSE_SERIAL)) { 121 if (fb_cnattach(0, 0, 0, 0)) { 122 panic("tx3912video_attach: can't init fb console"); 123 } 124 } 125 fba.fba_name = "fb"; 126 config_found(self, &fba, tx3912video_print); 127 #endif 128 } 129 130 int 131 tx3912video_print(aux, pnp) 132 void *aux; 133 const char *pnp; 134 { 135 return pnp ? QUIET : UNCONF; 136 } 137 138 int 139 tx3912video_init(tc, fb_start, fb_width, fb_height, fb_addr, fb_size, 140 fb_line_bytes) 141 tx_chipset_tag_t tc; 142 u_int32_t fb_start; /* Physical address */ 143 int fb_width, fb_height; 144 u_int32_t *fb_addr, *fb_size; 145 int *fb_line_bytes; 146 { 147 u_int32_t addr, size; 148 int fb_depth; 149 150 /* Inquire bit depth */ 151 fb_depth = tx3912video_fbdepth(tc, 0); 152 153 /* Allocate framebuffer area */ 154 if (tx3912video_framebuffer_alloc(tc, fb_start, fb_width, fb_height, 155 fb_depth, &addr, &size)) { 156 return 1; 157 } 158 #if notyet 159 tx3912video_resolution_init(tc, fb_width, fb_height); 160 #else 161 /* Use Windows CE setting. */ 162 #endif 163 /* Set DMA transfer address to VID module */ 164 tx3912video_framebuffer_init(tc, addr, size); 165 166 /* Syncronize framebuffer addr to frame signal */ 167 tx3912video_reset(tc); 168 169 *fb_line_bytes = (fb_width * fb_depth) / 8; 170 *fb_addr = addr; /* Phsical address */ 171 *fb_size = size; 172 173 return 0; 174 } 175 176 int 177 tx3912video_framebuffer_alloc(tc, start, h, v, depth, fb_addr, fb_size) 178 tx_chipset_tag_t tc; 179 u_int32_t start; 180 int h, v, depth; 181 u_int32_t *fb_addr, *fb_size; 182 { 183 struct extent_fixed ex_fixed[2]; 184 struct extent *ex; 185 u_long addr, size; 186 int err; 187 188 /* Calcurate frame buffer size */ 189 size = (h * v * depth) / 8; 190 191 /* Allocate V-RAM area */ 192 if (!(ex = extent_create("Frame buffer address", start, 193 start + TX3912_FRAMEBUFFER_MAX, 194 0, (caddr_t)ex_fixed, sizeof ex_fixed, 195 EX_NOWAIT))) { 196 return 1; 197 } 198 if((err = extent_alloc_subregion(ex, start, start + size, size, 199 TX3912_FRAMEBUFFER_ALIGNMENT, 200 TX3912_FRAMEBUFFER_BOUNDARY, 201 EX_FAST|EX_NOWAIT, &addr))) { 202 return 1; 203 } 204 framebuffer = addr; 205 framebuffersize = size; 206 *fb_addr = addr; 207 *fb_size = size; 208 209 return 0; 210 } 211 212 void 213 tx3912video_framebuffer_init(tc, fb_addr, fb_size) 214 tx_chipset_tag_t tc; 215 u_int32_t fb_addr, fb_size; 216 { 217 u_int32_t reg, vaddr, bank, base; 218 219 /* XXX currently I don't set DFVAL, so force DF signal toggled on 220 * XXX each frame. */ 221 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 222 reg &= ~TX3912_VIDEOCTRL1_DFMODE; 223 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 224 225 /* Set DMA transfer start and end address */ 226 227 bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr); 228 base = TX3912_VIDEOCTRL3_VIDBASEHI(fb_addr); 229 reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank); 230 /* Upper address counter */ 231 reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base); 232 tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg); 233 234 /* Lower address counter */ 235 base = TX3912_VIDEOCTRL4_VIDBASELO(fb_addr + fb_size); 236 reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base); 237 238 /* Set DF-signal rate */ 239 reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/ 240 241 /* Set VIDDONE signal delay after FRAME signal */ 242 /* XXX not yet*/ 243 tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg); 244 245 /* Clear frame buffer */ 246 vaddr = MIPS_PHYS_TO_KSEG1(fb_addr); 247 bzero((void*)vaddr, fb_size); 248 } 249 250 void 251 tx3912video_resolution_init(tc, h, v) 252 tx_chipset_tag_t tc; 253 int h; 254 int v; 255 { 256 u_int32_t reg, val; 257 int split, bit8, horzval, lineval; 258 259 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 260 split = reg & TX3912_VIDEOCTRL1_DISPSPLIT; 261 bit8 = (TX3912_VIDEOCTRL1_BITSEL(reg) == 262 TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR); 263 val = TX3912_VIDEOCTRL1_BITSEL(reg); 264 265 if ((val == TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR) && 266 !split) { 267 /* (LCD horizontal pixels / 8bit) * RGB - 1 */ 268 horzval = (h / 8) * 3 - 1; 269 } else { 270 horzval = h / 4 - 1; 271 } 272 lineval = (split ? v / 2 : v) - 1; 273 274 /* Video rate */ 275 /* XXX 276 * probably This value should be determined from DFINT and LCDINT 277 */ 278 reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1); 279 /* Horizontal size of LCD */ 280 reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval); 281 /* # of lines for the LCD */ 282 reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval); 283 284 tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg); 285 } 286 287 int 288 tx3912video_fbdepth(tc, verbose) 289 tx_chipset_tag_t tc; 290 int verbose; 291 { 292 u_int32_t reg, val; 293 294 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 295 val = TX3912_VIDEOCTRL1_BITSEL(reg); 296 switch (val) { 297 case TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR: 298 if (verbose) 299 printf("8bit color"); 300 return 8; 301 case TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE: 302 if (verbose) 303 printf("4bit greyscale"); 304 return 4; 305 case TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE: 306 if (verbose) 307 printf("2bit greyscale"); 308 return 2; 309 case TX3912_VIDEOCTRL1_BITSEL_MONOCHROME: 310 if (verbose) 311 printf("monochrome"); 312 return 1; 313 } 314 return 0; 315 } 316 317 void 318 tx3912video_reset(tc) 319 tx_chipset_tag_t tc; 320 { 321 u_int32_t reg; 322 323 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 324 325 /* Disable video logic at end of this frame */ 326 reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME; 327 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 328 329 /* Wait for end of frame */ 330 delay(300 * 1000); 331 332 /* Make sure to disable video logic */ 333 reg &= ~TX3912_VIDEOCTRL1_ENVID; 334 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 335 336 delay(1000); 337 338 /* Enable video logic again */ 339 reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME; 340 reg |= TX3912_VIDEOCTRL1_ENVID; 341 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg); 342 343 delay(1000); 344 } 345 346 347
Indexes created Fri Oct 31 11:10:07 GMT 2025