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tx3912video.c revision 1.8 
      1 /*	$NetBSD: tx3912video.c,v 1.8 2000/03/13 18:49:17 uch Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1999, 2000, by UCHIYAMA Yasushi
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. The name of the developer may NOT be used to endorse or promote products
     13  *    derived from this software without specific prior written permission.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     25  * SUCH DAMAGE.
     26  *
     27  */
     28 #include "opt_tx39_debug.h"
     29 #include "hpcfb.h"
     30 
     31 #include <sys/param.h>
     32 #include <sys/systm.h>
     33 #include <sys/device.h>
     34 #include <sys/extent.h>
     35 
     36 #include <machine/bus.h>
     37 #include <machine/bootinfo.h> /* bootinfo */
     38 
     39 #include <hpcmips/tx/tx39var.h>
     40 #include <hpcmips/tx/tx3912videovar.h>
     41 #include <hpcmips/tx/tx3912videoreg.h>
     42 
     43 #if NHPCFB > 0
     44 #include <arch/hpcmips/dev/hpcfbvar.h>
     45 #include <arch/hpcmips/dev/hpcfbio.h>
     46 #include <arch/hpcmips/dev/bivideovar.h>
     47 #endif
     48 #include <machine/autoconf.h> /* XXX */
     49 
     50 #undef TX3912VIDEO_DEBUG
     51 
     52 void tx3912video_framebuffer_init __P((tx_chipset_tag_t, u_int32_t,
     53 				       u_int32_t));
     54 int  tx3912video_framebuffer_alloc __P((tx_chipset_tag_t, u_int32_t,
     55 					int, int, int, u_int32_t*,
     56 					u_int32_t*));
     57 void tx3912video_reset __P((tx_chipset_tag_t));
     58 void tx3912video_resolution_init __P((tx_chipset_tag_t, int, int));
     59 int  tx3912video_fbdepth __P((tx_chipset_tag_t, int));
     60 
     61 int	tx3912video_match __P((struct device*, struct cfdata*, void*));
     62 void	tx3912video_attach __P((struct device*, struct device*, void*));
     63 int	tx3912video_print __P((void*, const char*));
     64 
     65 struct tx3912video_chip {
     66 	u_int32_t vc_fbaddr;
     67 	u_int32_t vc_fbsize;
     68 	int	vc_fbdepth;
     69 	int	vc_fbwidth;
     70 	int	vc_fbheight;
     71 
     72 	void (*vc_drawline) __P((int, int, int, int));
     73 	void (*vc_drawdot) __P((int, int));
     74 };
     75 
     76 struct tx3912video_softc {
     77 	struct device sc_dev;
     78 
     79 	struct tx3912video_chip *sc_chip;
     80 };
     81 
     82 struct fb_attach_args {
     83 	const char *fba_name;
     84 };
     85 
     86 struct cfattach tx3912video_ca = {
     87 	sizeof(struct tx3912video_softc), tx3912video_match,
     88 	tx3912video_attach
     89 };
     90 
     91 /* console */
     92 struct tx3912video_chip tx3912video_chip;
     93 
     94 void	tx3912video_attach_drawfunc __P((struct tx3912video_chip*));
     95 
     96 int
     97 tx3912video_match(parent, cf, aux)
     98 	struct device *parent;
     99 	struct cfdata *cf;
    100 	void *aux;
    101 {
    102 	return 1;
    103 }
    104 
    105 void
    106 tx3912video_attach(parent, self, aux)
    107 	struct device *parent;
    108 	struct device *self;
    109 	void *aux;
    110 {
    111 	struct txsim_attach_args *ta = aux;
    112 	struct tx3912video_softc *sc = (void*)self;
    113 	tx_chipset_tag_t tc = ta->ta_tc;
    114 	struct mainbus_attach_args ma; /* XXX */
    115 	txreg_t reg;
    116 
    117 	sc->sc_chip = &tx3912video_chip;
    118 
    119 	printf(": ");
    120 	tx3912video_fbdepth(tc, 1);
    121 	printf(", frame buffer 0x%08x-0x%08x", sc->sc_chip->vc_fbaddr,
    122 	       sc->sc_chip->vc_fbaddr + sc->sc_chip->vc_fbsize);
    123 
    124 	printf("\n");
    125 
    126 #ifndef TX3912VIDEO_DEBUG
    127 	if (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) {
    128 		printf("%s: power off\n", sc->sc_dev.dv_xname);
    129 		reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
    130 		reg &= ~(TX3912_VIDEOCTRL1_DISPON |
    131 			 TX3912_VIDEOCTRL1_ENVID);
    132 		tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
    133 	}
    134 #endif /* TX3912VIDEO_DEBUG */
    135 
    136 	/* attach debug draw routine */
    137 	tx3912video_attach_drawfunc(sc->sc_chip);
    138 
    139 	/* Attach frame buffer device */
    140 #if NHPCFB > 0
    141 	if (!(bootinfo->bi_cnuse & BI_CNUSE_SERIAL)) {
    142 		if (hpcfb_cnattach(0, 0, 0, 0)) {
    143 			panic("tx3912video_attach: can't init fb console");
    144 		}
    145 	}
    146 	ma.ma_name = "bivideo"; /* XXX */
    147 	config_found(self, &ma, tx3912video_print);
    148 #endif
    149 }
    150 
    151 int
    152 tx3912video_print(aux, pnp)
    153 	void *aux;
    154 	const char *pnp;
    155 {
    156 	return pnp ? QUIET : UNCONF;
    157 }
    158 
    159 int
    160 tx3912video_init(tc, fb_start, fb_width, fb_height, fb_addr, fb_size,
    161 		fb_line_bytes)
    162 	tx_chipset_tag_t tc;
    163 	u_int32_t fb_start; /* Physical address */
    164 	int fb_width, fb_height;
    165 	u_int32_t *fb_addr, *fb_size;
    166 	int *fb_line_bytes;
    167 {
    168  	u_int32_t addr, size;
    169 	int fb_depth;
    170 	txreg_t reg;
    171 
    172 	/* Inquire bit depth */
    173 	fb_depth = tx3912video_fbdepth(tc, 0);
    174 
    175 	switch (fb_depth) {
    176 	case 2:
    177 		bootinfo->fb_type = BIFB_D2_M2L_0;
    178 		break;
    179 	case 4:
    180 		/* XXX should implement rasops4.c */
    181 		fb_depth = 2;
    182 		bootinfo->fb_type = BIFB_D2_M2L_0;
    183 		reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
    184 		TX3912_VIDEOCTRL1_BITSEL_CLR(reg);
    185 		reg = TX3912_VIDEOCTRL1_BITSEL_SET(
    186 			reg, TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE);
    187 		tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
    188 		break;
    189 	case 8:
    190 		bootinfo->fb_type = BIFB_D8_FF;
    191 		break;
    192 	}
    193 
    194 	tx3912video_chip.vc_fbdepth = fb_depth;
    195 	tx3912video_chip.vc_fbwidth = fb_width;
    196 	tx3912video_chip.vc_fbheight= fb_height;
    197 
    198 
    199 	/* Allocate framebuffer area */
    200 	if (tx3912video_framebuffer_alloc(tc, fb_start, fb_width, fb_height,
    201 					 fb_depth, &addr, &size)) {
    202 		return 1;
    203 	}
    204 #if notyet
    205 	tx3912video_resolution_init(tc, fb_width, fb_height);
    206 #else
    207 	/* Use Windows CE setting. */
    208 #endif
    209 	/* Set DMA transfer address to VID module */
    210 	tx3912video_framebuffer_init(tc, addr, size);
    211 
    212 	/* Syncronize framebuffer addr to frame signal */
    213 	tx3912video_reset(tc);
    214 
    215 	*fb_line_bytes = (fb_width * fb_depth) / 8;
    216 	*fb_addr = addr; /* Phsical address */
    217 	*fb_size = size;
    218 
    219 	return 0;
    220 }
    221 
    222  int
    223 tx3912video_framebuffer_alloc(tc, start, h, v, depth, fb_addr, fb_size)
    224 	tx_chipset_tag_t tc;
    225 	u_int32_t start;
    226 	int h, v, depth;
    227 	u_int32_t *fb_addr, *fb_size;
    228 {
    229 	struct extent_fixed ex_fixed[2];
    230 	struct extent *ex;
    231 	u_long addr, size;
    232 	int err;
    233 
    234 	/* Calcurate frame buffer size */
    235 	size = (h * v * depth) / 8;
    236 
    237 	/* Allocate V-RAM area */
    238 	if (!(ex = extent_create("Frame buffer address", start,
    239 				 start + TX3912_FRAMEBUFFER_MAX,
    240 				 0, (caddr_t)ex_fixed, sizeof ex_fixed,
    241  				 EX_NOWAIT))) {
    242 		return 1;
    243 	}
    244 	if((err = extent_alloc_subregion(ex, start, start + size, size,
    245 					 TX3912_FRAMEBUFFER_ALIGNMENT,
    246 					 TX3912_FRAMEBUFFER_BOUNDARY,
    247 					 EX_FAST|EX_NOWAIT, &addr))) {
    248 		return 1;
    249 	}
    250 	tx3912video_chip.vc_fbaddr = addr;
    251 	tx3912video_chip.vc_fbsize = size;
    252 
    253 	*fb_addr = addr;
    254 	*fb_size = size;
    255 
    256 	return 0;
    257 }
    258 
    259  void
    260 tx3912video_framebuffer_init(tc, fb_addr, fb_size)
    261 	tx_chipset_tag_t tc;
    262 	u_int32_t fb_addr, fb_size;
    263 {
    264 	u_int32_t reg, vaddr, bank, base;
    265 
    266 	/*  XXX currently I don't set DFVAL, so force DF signal toggled on
    267          *  XXX each frame. */
    268 	reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
    269 	reg &= ~TX3912_VIDEOCTRL1_DFMODE;
    270 	tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
    271 
    272 	/* Set DMA transfer start and end address */
    273 
    274 	bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr);
    275 	base = TX3912_VIDEOCTRL3_VIDBASEHI(fb_addr);
    276 	reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank);
    277 	/* Upper address counter */
    278 	reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base);
    279 	tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg);
    280 
    281 	/* Lower address counter  */
    282 	base = TX3912_VIDEOCTRL4_VIDBASELO(fb_addr + fb_size);
    283 	reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base);
    284 
    285 	/* Set DF-signal rate */
    286 	reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/
    287 
    288 	/* Set VIDDONE signal delay after FRAME signal */
    289 	/* XXX not yet*/
    290 	tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg);
    291 
    292 	/* Clear frame buffer */
    293 	vaddr = MIPS_PHYS_TO_KSEG1(fb_addr);
    294 	bzero((void*)vaddr, fb_size);
    295 }
    296 
    297  void
    298 tx3912video_resolution_init(tc, h, v)
    299 	tx_chipset_tag_t tc;
    300 	int h;
    301 	int v;
    302 {
    303 	u_int32_t reg, val;
    304 	int split, bit8, horzval, lineval;
    305 
    306 	reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
    307 	split = reg & TX3912_VIDEOCTRL1_DISPSPLIT;
    308 	bit8  = (TX3912_VIDEOCTRL1_BITSEL(reg) ==
    309 		 TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR);
    310 	val = TX3912_VIDEOCTRL1_BITSEL(reg);
    311 
    312 	if ((val == TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR) &&
    313 	    !split) {
    314 		/* (LCD horizontal pixels / 8bit) * RGB - 1 */
    315 		horzval = (h / 8) * 3 - 1;
    316 	} else {
    317 		horzval = h / 4 - 1;
    318 	}
    319 	lineval = (split ? v / 2 : v) - 1;
    320 
    321 	/* Video rate */
    322 	/* XXX
    323 	 *  probably This value should be determined from DFINT and LCDINT
    324 	 */
    325 	reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1);
    326 	/* Horizontal size of LCD */
    327 	reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval);
    328 	/* # of lines for the LCD */
    329 	reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval);
    330 
    331 	tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg);
    332 }
    333 
    334 int
    335 tx3912video_fbdepth(tc, verbose)
    336 	tx_chipset_tag_t tc;
    337 	int verbose;
    338 {
    339 	u_int32_t reg, val;
    340 
    341 	reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
    342 	val = TX3912_VIDEOCTRL1_BITSEL(reg);
    343 	switch (val) {
    344 	case TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR:
    345 		if (verbose)
    346 			printf("8bit color");
    347 		return 8;
    348 	case TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE:
    349 		if (verbose)
    350 			printf("4bit greyscale");
    351 		return 4;
    352 	case TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE:
    353 		if (verbose)
    354 			printf("2bit greyscale");
    355 		return 2;
    356 	case TX3912_VIDEOCTRL1_BITSEL_MONOCHROME:
    357 		if (verbose)
    358 			printf("monochrome");
    359 		return 1;
    360 	}
    361 	return 0;
    362 }
    363 
    364 void
    365 tx3912video_reset(tc)
    366 	tx_chipset_tag_t tc;
    367 {
    368 	u_int32_t reg;
    369 
    370 	reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
    371 
    372 	/* Disable video logic at end of this frame */
    373 	reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME;
    374 	tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
    375 
    376 	/* Wait for end of frame */
    377 	delay(300 * 1000);
    378 
    379 	/* Make sure to disable video logic */
    380 	reg &= ~TX3912_VIDEOCTRL1_ENVID;
    381 	tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
    382 
    383 	delay(1000);
    384 
    385 	/* Enable video logic again */
    386 	reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME;
    387 	reg |= TX3912_VIDEOCTRL1_ENVID;
    388 	tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
    389 
    390 	delay(1000);
    391 }
    392 
    393 /*
    394  * Debug routines.
    395  */
    396 
    397 void
    398 tx3912video_calibration_pattern()
    399 {
    400 	struct tx3912video_chip *vc = &tx3912video_chip;
    401 	int x, y;
    402 
    403 	x = vc->vc_fbwidth - 40;
    404 	y = vc->vc_fbheight - 40;
    405 	tx3912video_line(40, 40, x , 40);
    406 	tx3912video_line(x , 40, x , y );
    407 	tx3912video_line(x , y , 40, y );
    408 	tx3912video_line(40, y , 40, 40);
    409 	tx3912video_line(40, 40, x , y );
    410 	tx3912video_line(x,  40, 40, y );
    411 }
    412 
    413 #define BPP2 ({ \
    414 	u_int8_t bitmap; \
    415 	bitmap = *(volatile u_int8_t*)MIPS_PHYS_TO_KSEG1(addr); \
    416 	*(volatile u_int8_t*)MIPS_PHYS_TO_KSEG1(addr) = \
    417 		(bitmap & ~(0x3 << ((3 - (x % 4)) * 2))); \
    418 })
    419 
    420 #define BPP4 ({ \
    421 	u_int8_t bitmap; \
    422 	bitmap = *(volatile u_int8_t*)MIPS_PHYS_TO_KSEG1(addr); \
    423 	*(volatile u_int8_t*)MIPS_PHYS_TO_KSEG1(addr) = \
    424 		(bitmap & ~(0xf << ((1 - (x % 2)) * 4))); \
    425 })
    426 
    427 #define BPP8 ({ \
    428 	*(volatile u_int8_t*)MIPS_PHYS_TO_KSEG1(addr) = 0xff; \
    429 })
    430 
    431 #define BRESENHAM(a, b, c, d, func) ({ \
    432 	u_int32_t fbaddr = vc->vc_fbaddr; \
    433 	u_int32_t fbwidth = vc->vc_fbwidth; \
    434 	u_int32_t fbdepth = vc->vc_fbdepth; \
    435 	len = a, step = b -1; \
    436 	if (step == 0) \
    437 		return; \
    438 	kstep = len == 0 ? 0 : 1; \
    439 	for (i = k = 0, j = step / 2; i <= step; i++) { \
    440 		x = xbase c; \
    441 		y = ybase d; \
    442 		addr = fbaddr + (((y * fbwidth + x) * fbdepth) >> 3); \
    443 		func; \
    444 		j -= len; \
    445 		while (j < 0) { \
    446 			j += step; \
    447 			k += kstep; \
    448 		} \
    449 	} \
    450 })
    451 
    452 #define DRAWLINE(func) ({ \
    453 	if (x < 0) { \
    454 		if (y < 0) { \
    455 			if (_y < _x) { \
    456 				BRESENHAM(_y, _x, -i, -k, func); \
    457 			} else { \
    458 				BRESENHAM(_x, _y, -k, -i, func); \
    459 			} \
    460 		} else { \
    461 			if (_y < _x) { \
    462 				BRESENHAM(_y, _x, -i, +k, func); \
    463 			} else { \
    464 				BRESENHAM(_x, _y, -k, +i, func); \
    465 			} \
    466 		} \
    467 	} else { \
    468 		if (y < 0) { \
    469 			if (_y < _x) { \
    470 				BRESENHAM(_y, _x, +i, -k, func); \
    471 			} else { \
    472 				BRESENHAM(_x, _y, +k, -i, func); \
    473 			} \
    474 		} else { \
    475 			if (_y < _x) { \
    476 				BRESENHAM(_y, _x, +i, +k, func); \
    477 			} else { \
    478 				BRESENHAM(_x, _y, +k, +i, func); \
    479 			} \
    480 		} \
    481 	} \
    482 })
    483 
    484 #define LINEFUNC(b) \
    485 static void linebpp##b __P((int, int, int, int)); \
    486 static void \
    487 linebpp##b##(x0, y0, x1, y1) \
    488 	int x0, y0, x1, y1; \
    489 { \
    490 	struct tx3912video_chip *vc = &tx3912video_chip; \
    491 	u_int32_t addr; \
    492 	int i, j, k, len, step, kstep; \
    493 	int x, _x, y, _y; \
    494 	int xbase, ybase; \
    495 	x = x1 - x0; \
    496 	y = y1 - y0; \
    497 	_x = abs(x); \
    498 	_y = abs(y); \
    499 	xbase = x0; \
    500 	ybase = y0; \
    501 	DRAWLINE(BPP##b##); \
    502 }
    503 
    504 #define DOTFUNC(b) \
    505 static void dotbpp##b __P((int, int)); \
    506 static void \
    507 dotbpp##b##(x, y) \
    508 	int x, y; \
    509 { \
    510 	struct tx3912video_chip *vc = &tx3912video_chip; \
    511 	u_int32_t addr; \
    512 	addr = vc->vc_fbaddr + (((y * vc->vc_fbwidth + x) * \
    513 				 vc->vc_fbdepth) >> 3); \
    514 	BPP##b; \
    515 }
    516 
    517 static void linebpp_unimpl __P((int, int, int, int));
    518 static void dotbpp_unimpl __P((int, int));
    519 static
    520 void linebpp_unimpl(x0, y0, x1, y1)
    521 	int x0, y0, x1, y1;
    522 {
    523 	return;
    524 }
    525 static
    526 void dotbpp_unimpl(x, y)
    527 	int x, y;
    528 {
    529 	return;
    530 }
    531 
    532 LINEFUNC(2)
    533 LINEFUNC(4)
    534 LINEFUNC(8)
    535 DOTFUNC(2)
    536 DOTFUNC(4)
    537 DOTFUNC(8)
    538 
    539 void
    540 tx3912video_attach_drawfunc(vc)
    541 	struct tx3912video_chip *vc;
    542 {
    543 	switch (vc->vc_fbdepth) {
    544 	default:
    545 		vc->vc_drawline = linebpp_unimpl;
    546 		vc->vc_drawdot = dotbpp_unimpl;
    547 		break;
    548 	case 8:
    549 		vc->vc_drawline = linebpp8;
    550 		vc->vc_drawdot = dotbpp8;
    551 		break;
    552 	case 4:
    553 		vc->vc_drawline = linebpp4;
    554 		vc->vc_drawdot = dotbpp4;
    555 		break;
    556 	case 2:
    557 		vc->vc_drawline = linebpp2;
    558 		vc->vc_drawdot = dotbpp2;
    559 		break;
    560 	}
    561 }
    562 
    563 void
    564 tx3912video_line(x0, y0, x1, y1)
    565 	int x0, y0, x1, y1;
    566 {
    567 	struct tx3912video_chip *vc = &tx3912video_chip;
    568 	vc->vc_drawline(x0, y0, x1, y1);
    569 }
    570 
    571 void
    572 tx3912video_dot(x, y)
    573 	int x, y;
    574 {
    575 	struct tx3912video_chip *vc = &tx3912video_chip;
    576 	vc->vc_drawdot(x, y);
    577 }
    578