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tx3912video.c revision 1.9 
      1 /*	$NetBSD: tx3912video.c,v 1.9 2000/04/03 03:35:38 sato Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1999, 2000, by UCHIYAMA Yasushi
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. The name of the developer may NOT be used to endorse or promote products
     13  *    derived from this software without specific prior written permission.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     25  * SUCH DAMAGE.
     26  *
     27  */
     28 #include "opt_tx39_debug.h"
     29 #include "hpcfb.h"
     30 
     31 #include <sys/param.h>
     32 #include <sys/systm.h>
     33 #include <sys/device.h>
     34 #include <sys/extent.h>
     35 
     36 #include <machine/bus.h>
     37 #include <machine/bootinfo.h> /* bootinfo */
     38 
     39 #include <hpcmips/tx/tx39var.h>
     40 #include <hpcmips/tx/tx3912videovar.h>
     41 #include <hpcmips/tx/tx3912videoreg.h>
     42 
     43 #if NHPCFB > 0
     44 #include <dev/wscons/wsconsio.h>
     45 #include <arch/hpcmips/dev/hpcfbvar.h>
     46 #include <arch/hpcmips/dev/hpcfbio.h>
     47 #include <arch/hpcmips/dev/bivideovar.h>
     48 #endif
     49 #include <machine/autoconf.h> /* XXX */
     50 
     51 #undef TX3912VIDEO_DEBUG
     52 
     53 void tx3912video_framebuffer_init __P((tx_chipset_tag_t, u_int32_t,
     54 				       u_int32_t));
     55 int  tx3912video_framebuffer_alloc __P((tx_chipset_tag_t, u_int32_t,
     56 					int, int, int, u_int32_t*,
     57 					u_int32_t*));
     58 void tx3912video_reset __P((tx_chipset_tag_t));
     59 void tx3912video_resolution_init __P((tx_chipset_tag_t, int, int));
     60 int  tx3912video_fbdepth __P((tx_chipset_tag_t, int));
     61 
     62 int	tx3912video_match __P((struct device*, struct cfdata*, void*));
     63 void	tx3912video_attach __P((struct device*, struct device*, void*));
     64 int	tx3912video_print __P((void*, const char*));
     65 
     66 struct tx3912video_chip {
     67 	u_int32_t vc_fbaddr;
     68 	u_int32_t vc_fbsize;
     69 	int	vc_fbdepth;
     70 	int	vc_fbwidth;
     71 	int	vc_fbheight;
     72 
     73 	void (*vc_drawline) __P((int, int, int, int));
     74 	void (*vc_drawdot) __P((int, int));
     75 };
     76 
     77 struct tx3912video_softc {
     78 	struct device sc_dev;
     79 
     80 	struct tx3912video_chip *sc_chip;
     81 };
     82 
     83 struct fb_attach_args {
     84 	const char *fba_name;
     85 };
     86 
     87 struct cfattach tx3912video_ca = {
     88 	sizeof(struct tx3912video_softc), tx3912video_match,
     89 	tx3912video_attach
     90 };
     91 
     92 /* console */
     93 struct tx3912video_chip tx3912video_chip;
     94 
     95 void	tx3912video_attach_drawfunc __P((struct tx3912video_chip*));
     96 
     97 int
     98 tx3912video_match(parent, cf, aux)
     99 	struct device *parent;
    100 	struct cfdata *cf;
    101 	void *aux;
    102 {
    103 	return 1;
    104 }
    105 
    106 void
    107 tx3912video_attach(parent, self, aux)
    108 	struct device *parent;
    109 	struct device *self;
    110 	void *aux;
    111 {
    112 	struct txsim_attach_args *ta = aux;
    113 	struct tx3912video_softc *sc = (void*)self;
    114 	tx_chipset_tag_t tc = ta->ta_tc;
    115 	struct mainbus_attach_args ma; /* XXX */
    116 	txreg_t reg;
    117 
    118 	sc->sc_chip = &tx3912video_chip;
    119 
    120 	printf(": ");
    121 	tx3912video_fbdepth(tc, 1);
    122 	printf(", frame buffer 0x%08x-0x%08x", sc->sc_chip->vc_fbaddr,
    123 	       sc->sc_chip->vc_fbaddr + sc->sc_chip->vc_fbsize);
    124 
    125 	printf("\n");
    126 
    127 #ifndef TX3912VIDEO_DEBUG
    128 	if (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) {
    129 		printf("%s: power off\n", sc->sc_dev.dv_xname);
    130 		reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
    131 		reg &= ~(TX3912_VIDEOCTRL1_DISPON |
    132 			 TX3912_VIDEOCTRL1_ENVID);
    133 		tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
    134 	}
    135 #endif /* TX3912VIDEO_DEBUG */
    136 
    137 	/* attach debug draw routine */
    138 	tx3912video_attach_drawfunc(sc->sc_chip);
    139 
    140 	/* Attach frame buffer device */
    141 #if NHPCFB > 0
    142 	if (!(bootinfo->bi_cnuse & BI_CNUSE_SERIAL)) {
    143 		if (hpcfb_cnattach(0, 0, 0, 0)) {
    144 			panic("tx3912video_attach: can't init fb console");
    145 		}
    146 	}
    147 	ma.ma_name = "bivideo"; /* XXX */
    148 	config_found(self, &ma, tx3912video_print);
    149 #endif
    150 }
    151 
    152 int
    153 tx3912video_print(aux, pnp)
    154 	void *aux;
    155 	const char *pnp;
    156 {
    157 	return pnp ? QUIET : UNCONF;
    158 }
    159 
    160 int
    161 tx3912video_init(tc, fb_start, fb_width, fb_height, fb_addr, fb_size,
    162 		fb_line_bytes)
    163 	tx_chipset_tag_t tc;
    164 	u_int32_t fb_start; /* Physical address */
    165 	int fb_width, fb_height;
    166 	u_int32_t *fb_addr, *fb_size;
    167 	int *fb_line_bytes;
    168 {
    169  	u_int32_t addr, size;
    170 	int fb_depth;
    171 	txreg_t reg;
    172 
    173 	/* Inquire bit depth */
    174 	fb_depth = tx3912video_fbdepth(tc, 0);
    175 
    176 	switch (fb_depth) {
    177 	case 2:
    178 		bootinfo->fb_type = BIFB_D2_M2L_0;
    179 		break;
    180 	case 4:
    181 		/* XXX should implement rasops4.c */
    182 		fb_depth = 2;
    183 		bootinfo->fb_type = BIFB_D2_M2L_0;
    184 		reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
    185 		TX3912_VIDEOCTRL1_BITSEL_CLR(reg);
    186 		reg = TX3912_VIDEOCTRL1_BITSEL_SET(
    187 			reg, TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE);
    188 		tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
    189 		break;
    190 	case 8:
    191 		bootinfo->fb_type = BIFB_D8_FF;
    192 		break;
    193 	}
    194 
    195 	tx3912video_chip.vc_fbdepth = fb_depth;
    196 	tx3912video_chip.vc_fbwidth = fb_width;
    197 	tx3912video_chip.vc_fbheight= fb_height;
    198 
    199 
    200 	/* Allocate framebuffer area */
    201 	if (tx3912video_framebuffer_alloc(tc, fb_start, fb_width, fb_height,
    202 					 fb_depth, &addr, &size)) {
    203 		return 1;
    204 	}
    205 #if notyet
    206 	tx3912video_resolution_init(tc, fb_width, fb_height);
    207 #else
    208 	/* Use Windows CE setting. */
    209 #endif
    210 	/* Set DMA transfer address to VID module */
    211 	tx3912video_framebuffer_init(tc, addr, size);
    212 
    213 	/* Syncronize framebuffer addr to frame signal */
    214 	tx3912video_reset(tc);
    215 
    216 	*fb_line_bytes = (fb_width * fb_depth) / 8;
    217 	*fb_addr = addr; /* Phsical address */
    218 	*fb_size = size;
    219 
    220 	return 0;
    221 }
    222 
    223  int
    224 tx3912video_framebuffer_alloc(tc, start, h, v, depth, fb_addr, fb_size)
    225 	tx_chipset_tag_t tc;
    226 	u_int32_t start;
    227 	int h, v, depth;
    228 	u_int32_t *fb_addr, *fb_size;
    229 {
    230 	struct extent_fixed ex_fixed[2];
    231 	struct extent *ex;
    232 	u_long addr, size;
    233 	int err;
    234 
    235 	/* Calcurate frame buffer size */
    236 	size = (h * v * depth) / 8;
    237 
    238 	/* Allocate V-RAM area */
    239 	if (!(ex = extent_create("Frame buffer address", start,
    240 				 start + TX3912_FRAMEBUFFER_MAX,
    241 				 0, (caddr_t)ex_fixed, sizeof ex_fixed,
    242  				 EX_NOWAIT))) {
    243 		return 1;
    244 	}
    245 	if((err = extent_alloc_subregion(ex, start, start + size, size,
    246 					 TX3912_FRAMEBUFFER_ALIGNMENT,
    247 					 TX3912_FRAMEBUFFER_BOUNDARY,
    248 					 EX_FAST|EX_NOWAIT, &addr))) {
    249 		return 1;
    250 	}
    251 	tx3912video_chip.vc_fbaddr = addr;
    252 	tx3912video_chip.vc_fbsize = size;
    253 
    254 	*fb_addr = addr;
    255 	*fb_size = size;
    256 
    257 	return 0;
    258 }
    259 
    260  void
    261 tx3912video_framebuffer_init(tc, fb_addr, fb_size)
    262 	tx_chipset_tag_t tc;
    263 	u_int32_t fb_addr, fb_size;
    264 {
    265 	u_int32_t reg, vaddr, bank, base;
    266 
    267 	/*  XXX currently I don't set DFVAL, so force DF signal toggled on
    268          *  XXX each frame. */
    269 	reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
    270 	reg &= ~TX3912_VIDEOCTRL1_DFMODE;
    271 	tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
    272 
    273 	/* Set DMA transfer start and end address */
    274 
    275 	bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr);
    276 	base = TX3912_VIDEOCTRL3_VIDBASEHI(fb_addr);
    277 	reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank);
    278 	/* Upper address counter */
    279 	reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base);
    280 	tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg);
    281 
    282 	/* Lower address counter  */
    283 	base = TX3912_VIDEOCTRL4_VIDBASELO(fb_addr + fb_size);
    284 	reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base);
    285 
    286 	/* Set DF-signal rate */
    287 	reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/
    288 
    289 	/* Set VIDDONE signal delay after FRAME signal */
    290 	/* XXX not yet*/
    291 	tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg);
    292 
    293 	/* Clear frame buffer */
    294 	vaddr = MIPS_PHYS_TO_KSEG1(fb_addr);
    295 	bzero((void*)vaddr, fb_size);
    296 }
    297 
    298  void
    299 tx3912video_resolution_init(tc, h, v)
    300 	tx_chipset_tag_t tc;
    301 	int h;
    302 	int v;
    303 {
    304 	u_int32_t reg, val;
    305 	int split, bit8, horzval, lineval;
    306 
    307 	reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
    308 	split = reg & TX3912_VIDEOCTRL1_DISPSPLIT;
    309 	bit8  = (TX3912_VIDEOCTRL1_BITSEL(reg) ==
    310 		 TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR);
    311 	val = TX3912_VIDEOCTRL1_BITSEL(reg);
    312 
    313 	if ((val == TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR) &&
    314 	    !split) {
    315 		/* (LCD horizontal pixels / 8bit) * RGB - 1 */
    316 		horzval = (h / 8) * 3 - 1;
    317 	} else {
    318 		horzval = h / 4 - 1;
    319 	}
    320 	lineval = (split ? v / 2 : v) - 1;
    321 
    322 	/* Video rate */
    323 	/* XXX
    324 	 *  probably This value should be determined from DFINT and LCDINT
    325 	 */
    326 	reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1);
    327 	/* Horizontal size of LCD */
    328 	reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval);
    329 	/* # of lines for the LCD */
    330 	reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval);
    331 
    332 	tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg);
    333 }
    334 
    335 int
    336 tx3912video_fbdepth(tc, verbose)
    337 	tx_chipset_tag_t tc;
    338 	int verbose;
    339 {
    340 	u_int32_t reg, val;
    341 
    342 	reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
    343 	val = TX3912_VIDEOCTRL1_BITSEL(reg);
    344 	switch (val) {
    345 	case TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR:
    346 		if (verbose)
    347 			printf("8bit color");
    348 		return 8;
    349 	case TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE:
    350 		if (verbose)
    351 			printf("4bit greyscale");
    352 		return 4;
    353 	case TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE:
    354 		if (verbose)
    355 			printf("2bit greyscale");
    356 		return 2;
    357 	case TX3912_VIDEOCTRL1_BITSEL_MONOCHROME:
    358 		if (verbose)
    359 			printf("monochrome");
    360 		return 1;
    361 	}
    362 	return 0;
    363 }
    364 
    365 void
    366 tx3912video_reset(tc)
    367 	tx_chipset_tag_t tc;
    368 {
    369 	u_int32_t reg;
    370 
    371 	reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
    372 
    373 	/* Disable video logic at end of this frame */
    374 	reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME;
    375 	tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
    376 
    377 	/* Wait for end of frame */
    378 	delay(300 * 1000);
    379 
    380 	/* Make sure to disable video logic */
    381 	reg &= ~TX3912_VIDEOCTRL1_ENVID;
    382 	tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
    383 
    384 	delay(1000);
    385 
    386 	/* Enable video logic again */
    387 	reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME;
    388 	reg |= TX3912_VIDEOCTRL1_ENVID;
    389 	tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
    390 
    391 	delay(1000);
    392 }
    393 
    394 /*
    395  * Debug routines.
    396  */
    397 
    398 void
    399 tx3912video_calibration_pattern()
    400 {
    401 	struct tx3912video_chip *vc = &tx3912video_chip;
    402 	int x, y;
    403 
    404 	x = vc->vc_fbwidth - 40;
    405 	y = vc->vc_fbheight - 40;
    406 	tx3912video_line(40, 40, x , 40);
    407 	tx3912video_line(x , 40, x , y );
    408 	tx3912video_line(x , y , 40, y );
    409 	tx3912video_line(40, y , 40, 40);
    410 	tx3912video_line(40, 40, x , y );
    411 	tx3912video_line(x,  40, 40, y );
    412 }
    413 
    414 #define BPP2 ({ \
    415 	u_int8_t bitmap; \
    416 	bitmap = *(volatile u_int8_t*)MIPS_PHYS_TO_KSEG1(addr); \
    417 	*(volatile u_int8_t*)MIPS_PHYS_TO_KSEG1(addr) = \
    418 		(bitmap & ~(0x3 << ((3 - (x % 4)) * 2))); \
    419 })
    420 
    421 #define BPP4 ({ \
    422 	u_int8_t bitmap; \
    423 	bitmap = *(volatile u_int8_t*)MIPS_PHYS_TO_KSEG1(addr); \
    424 	*(volatile u_int8_t*)MIPS_PHYS_TO_KSEG1(addr) = \
    425 		(bitmap & ~(0xf << ((1 - (x % 2)) * 4))); \
    426 })
    427 
    428 #define BPP8 ({ \
    429 	*(volatile u_int8_t*)MIPS_PHYS_TO_KSEG1(addr) = 0xff; \
    430 })
    431 
    432 #define BRESENHAM(a, b, c, d, func) ({ \
    433 	u_int32_t fbaddr = vc->vc_fbaddr; \
    434 	u_int32_t fbwidth = vc->vc_fbwidth; \
    435 	u_int32_t fbdepth = vc->vc_fbdepth; \
    436 	len = a, step = b -1; \
    437 	if (step == 0) \
    438 		return; \
    439 	kstep = len == 0 ? 0 : 1; \
    440 	for (i = k = 0, j = step / 2; i <= step; i++) { \
    441 		x = xbase c; \
    442 		y = ybase d; \
    443 		addr = fbaddr + (((y * fbwidth + x) * fbdepth) >> 3); \
    444 		func; \
    445 		j -= len; \
    446 		while (j < 0) { \
    447 			j += step; \
    448 			k += kstep; \
    449 		} \
    450 	} \
    451 })
    452 
    453 #define DRAWLINE(func) ({ \
    454 	if (x < 0) { \
    455 		if (y < 0) { \
    456 			if (_y < _x) { \
    457 				BRESENHAM(_y, _x, -i, -k, func); \
    458 			} else { \
    459 				BRESENHAM(_x, _y, -k, -i, func); \
    460 			} \
    461 		} else { \
    462 			if (_y < _x) { \
    463 				BRESENHAM(_y, _x, -i, +k, func); \
    464 			} else { \
    465 				BRESENHAM(_x, _y, -k, +i, func); \
    466 			} \
    467 		} \
    468 	} else { \
    469 		if (y < 0) { \
    470 			if (_y < _x) { \
    471 				BRESENHAM(_y, _x, +i, -k, func); \
    472 			} else { \
    473 				BRESENHAM(_x, _y, +k, -i, func); \
    474 			} \
    475 		} else { \
    476 			if (_y < _x) { \
    477 				BRESENHAM(_y, _x, +i, +k, func); \
    478 			} else { \
    479 				BRESENHAM(_x, _y, +k, +i, func); \
    480 			} \
    481 		} \
    482 	} \
    483 })
    484 
    485 #define LINEFUNC(b) \
    486 static void linebpp##b __P((int, int, int, int)); \
    487 static void \
    488 linebpp##b##(x0, y0, x1, y1) \
    489 	int x0, y0, x1, y1; \
    490 { \
    491 	struct tx3912video_chip *vc = &tx3912video_chip; \
    492 	u_int32_t addr; \
    493 	int i, j, k, len, step, kstep; \
    494 	int x, _x, y, _y; \
    495 	int xbase, ybase; \
    496 	x = x1 - x0; \
    497 	y = y1 - y0; \
    498 	_x = abs(x); \
    499 	_y = abs(y); \
    500 	xbase = x0; \
    501 	ybase = y0; \
    502 	DRAWLINE(BPP##b##); \
    503 }
    504 
    505 #define DOTFUNC(b) \
    506 static void dotbpp##b __P((int, int)); \
    507 static void \
    508 dotbpp##b##(x, y) \
    509 	int x, y; \
    510 { \
    511 	struct tx3912video_chip *vc = &tx3912video_chip; \
    512 	u_int32_t addr; \
    513 	addr = vc->vc_fbaddr + (((y * vc->vc_fbwidth + x) * \
    514 				 vc->vc_fbdepth) >> 3); \
    515 	BPP##b; \
    516 }
    517 
    518 static void linebpp_unimpl __P((int, int, int, int));
    519 static void dotbpp_unimpl __P((int, int));
    520 static
    521 void linebpp_unimpl(x0, y0, x1, y1)
    522 	int x0, y0, x1, y1;
    523 {
    524 	return;
    525 }
    526 static
    527 void dotbpp_unimpl(x, y)
    528 	int x, y;
    529 {
    530 	return;
    531 }
    532 
    533 LINEFUNC(2)
    534 LINEFUNC(4)
    535 LINEFUNC(8)
    536 DOTFUNC(2)
    537 DOTFUNC(4)
    538 DOTFUNC(8)
    539 
    540 void
    541 tx3912video_attach_drawfunc(vc)
    542 	struct tx3912video_chip *vc;
    543 {
    544 	switch (vc->vc_fbdepth) {
    545 	default:
    546 		vc->vc_drawline = linebpp_unimpl;
    547 		vc->vc_drawdot = dotbpp_unimpl;
    548 		break;
    549 	case 8:
    550 		vc->vc_drawline = linebpp8;
    551 		vc->vc_drawdot = dotbpp8;
    552 		break;
    553 	case 4:
    554 		vc->vc_drawline = linebpp4;
    555 		vc->vc_drawdot = dotbpp4;
    556 		break;
    557 	case 2:
    558 		vc->vc_drawline = linebpp2;
    559 		vc->vc_drawdot = dotbpp2;
    560 		break;
    561 	}
    562 }
    563 
    564 void
    565 tx3912video_line(x0, y0, x1, y1)
    566 	int x0, y0, x1, y1;
    567 {
    568 	struct tx3912video_chip *vc = &tx3912video_chip;
    569 	vc->vc_drawline(x0, y0, x1, y1);
    570 }
    571 
    572 void
    573 tx3912video_dot(x, y)
    574 	int x, y;
    575 {
    576 	struct tx3912video_chip *vc = &tx3912video_chip;
    577 	vc->vc_drawdot(x, y);
    578 }
    579