tx39biu.c revision 1.14
1 /* $NetBSD: tx39biu.c,v 1.14 2009/03/14 15:36:07 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tx39biu.c,v 1.14 2009/03/14 15:36:07 dsl Exp $"); 34 35 #include "opt_tx39_watchdogtimer.h" 36 #include "opt_tx39biu_debug.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 42 #include <machine/bus.h> 43 #include <machine/debug.h> 44 45 #include <hpcmips/tx/tx39var.h> 46 #include <hpcmips/tx/tx39biureg.h> 47 #include <hpcmips/tx/txcsbusvar.h> 48 49 #ifdef TX39BIU_DEBUG 50 #define DPRINTF_ENABLE 51 #define DPRINTF_DEBUG tx39biu_debug 52 #endif 53 54 #define ISSETPRINT(r, s, m) dbg_bitmask_print((u_int32_t)(r), \ 55 TX39_MEMCONFIG ## s ## _ ##m, #m) 56 57 int tx39biu_match(struct device *, struct cfdata *, void *); 58 void tx39biu_attach(struct device *, struct device *, void *); 59 void tx39biu_callback(struct device *); 60 int tx39biu_print(void *, const char *); 61 int tx39biu_intr(void *); 62 63 static void *__sc; /* XXX */ 64 #ifdef TX39BIU_DEBUG 65 void tx39biu_dump(tx_chipset_tag_t); 66 #endif 67 68 struct tx39biu_softc { 69 struct device sc_dev; 70 tx_chipset_tag_t sc_tc; 71 }; 72 73 CFATTACH_DECL(tx39biu, sizeof(struct tx39biu_softc), 74 tx39biu_match, tx39biu_attach, NULL, NULL); 75 76 int 77 tx39biu_match(struct device *parent, struct cfdata *cf, void *aux) 78 { 79 return (ATTACH_NORMAL); 80 } 81 82 void 83 tx39biu_attach(struct device *parent, struct device *self, void *aux) 84 { 85 struct txsim_attach_args *ta = aux; 86 struct tx39biu_softc *sc = (void*)self; 87 tx_chipset_tag_t tc; 88 #ifdef TX39_WATCHDOGTIMER 89 txreg_t reg; 90 #endif 91 92 sc->sc_tc = tc = ta->ta_tc; 93 printf("\n"); 94 #ifdef TX39BIU_DEBUG 95 tx39biu_dump(tc); 96 #endif 97 98 #ifdef TX39_WATCHDOGTIMER 99 /* 100 * CLRWRBUSERRINT Bus error connected CPU HwInt0 101 */ 102 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 103 reg |= TX39_MEMCONFIG4_ENWATCH; 104 reg = TX39_MEMCONFIG4_WATCHTIMEVAL_SET(reg, 0xf); 105 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg); 106 107 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 108 if (reg & TX39_MEMCONFIG4_ENWATCH) { 109 int i; 110 i = TX39_MEMCONFIG4_WATCHTIMEVAL(reg); 111 i = (1000 * (i + 1) * 64) / 36864; 112 printf("WatchDogTimerRate: %dus\n", i); 113 } 114 #endif 115 __sc = sc; 116 117 /* Clear watch dog timer interrupt */ 118 tx39biu_intr(sc); 119 120 /* 121 * Chip select virtual bridge 122 */ 123 config_defer(self, tx39biu_callback); 124 } 125 126 void 127 tx39biu_callback(struct device *self) 128 { 129 struct tx39biu_softc *sc = (void*)self; 130 struct csbus_attach_args cba; 131 132 cba.cba_busname = "txcsbus"; 133 cba.cba_tc = sc->sc_tc; 134 config_found(self, &cba, tx39biu_print); 135 } 136 137 int 138 tx39biu_print(void *aux, const char *pnp) 139 { 140 return (pnp ? QUIET : UNCONF); 141 } 142 143 int 144 tx39biu_intr(void *arg) 145 { 146 struct tx39biu_softc *sc = __sc; 147 tx_chipset_tag_t tc; 148 txreg_t reg; 149 150 if (!sc) { 151 return (0); 152 } 153 tc = sc->sc_tc; 154 /* Clear interrupt */ 155 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 156 reg |= TX39_MEMCONFIG4_CLRWRBUSERRINT; 157 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg); 158 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 159 reg &= ~TX39_MEMCONFIG4_CLRWRBUSERRINT; 160 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg); 161 162 return (0); 163 } 164 165 #ifdef TX39BIU_DEBUG 166 void 167 tx39biu_dump(tc) 168 tx_chipset_tag_t tc; 169 { 170 char *rowsel[] = {"18,17:9", "22,18,20,19,17:9", "20,22,21,19,17:9", 171 "22,23,21,19,17:9"}; 172 char *colsel[] = {"22,20,18,8:1", "19,18,8:2", "21,20,18,8:2", 173 "23,22,20,18,8:2", "24,22,20,18,8:2", 174 "18,p,X,8:0","22,p,X,21,8:0", "18,p,X,21,8:1", 175 "22,p,X,23,21,8:1", "24,23,21,8:2"}; 176 txreg_t reg; 177 int i; 178 /* 179 * Memory config 0 register 180 */ 181 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 182 printf(" config0:"); 183 ISSETPRINT(reg, 0, ENDCLKOUTTRI); 184 ISSETPRINT(reg, 0, DISDQMINIT); 185 ISSETPRINT(reg, 0, ENSDRAMPD); 186 ISSETPRINT(reg, 0, SHOWDINO); 187 ISSETPRINT(reg, 0, ENRMAP2); 188 ISSETPRINT(reg, 0, ENRMAP1); 189 ISSETPRINT(reg, 0, ENWRINPAGE); 190 ISSETPRINT(reg, 0, ENCS3USER); 191 ISSETPRINT(reg, 0, ENCS2USER); 192 ISSETPRINT(reg, 0, ENCS1USER); 193 ISSETPRINT(reg, 0, ENCS1DRAM); 194 ISSETPRINT(reg, 0, CS3SIZE); 195 ISSETPRINT(reg, 0, CS2SIZE); 196 ISSETPRINT(reg, 0, CS1SIZE); 197 ISSETPRINT(reg, 0, CS0SIZE); 198 printf("\n"); 199 for (i = 0; i < 2; i++) { 200 int r, c; 201 printf(" BANK%d: ", i); 202 switch (i ? TX39_MEMCONFIG0_BANK1CONF(reg) 203 : TX39_MEMCONFIG0_BANK0CONF(reg)) { 204 case TX39_MEMCONFIG0_BANKCONF_16BITSDRAM: 205 printf("16bit SDRAM"); 206 break; 207 case TX39_MEMCONFIG0_BANKCONF_8BITSDRAM: 208 printf("8bit SDRAM"); 209 break; 210 case TX39_MEMCONFIG0_BANKCONF_32BITSDHDRAM: 211 printf("32bit DRAM/HDRAM"); 212 break; 213 case TX39_MEMCONFIG0_BANKCONF_16BITSDHDRAM: 214 printf("16bit DRAM/HDRAM"); 215 break; 216 } 217 if (i == 1) { 218 r = TX39_MEMCONFIG0_ROWSEL1(reg); 219 c = TX39_MEMCONFIG0_COLSEL1(reg); 220 } else { 221 r = TX39_MEMCONFIG0_ROWSEL0(reg); 222 c = TX39_MEMCONFIG0_COLSEL0(reg); 223 } 224 printf(" ROW %s COL %s\n", rowsel[r], colsel[c]); 225 } 226 227 /* 228 * Memory config 3 register 229 */ 230 printf(" config3:"); 231 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 232 #ifdef TX391X 233 ISSETPRINT(reg, 3, ENMCS3PAGE); 234 ISSETPRINT(reg, 3, ENMCS2PAGE); 235 ISSETPRINT(reg, 3, ENMCS1PAGE); 236 ISSETPRINT(reg, 3, ENMCS0PAGE); 237 #endif /* TX391X */ 238 ISSETPRINT(reg, 3, ENCS3PAGE); 239 ISSETPRINT(reg, 3, ENCS2PAGE); 240 ISSETPRINT(reg, 3, ENCS1PAGE); 241 ISSETPRINT(reg, 3, ENCS0PAGE); 242 ISSETPRINT(reg, 3, CARD2WAITEN); 243 ISSETPRINT(reg, 3, CARD1WAITEN); 244 ISSETPRINT(reg, 3, CARD2IOEN); 245 ISSETPRINT(reg, 3, CARD1IOEN); 246 #ifdef TX391X 247 ISSETPRINT(reg, 3, PORT8SEL); 248 #endif /* TX391X */ 249 #ifdef TX392X 250 ISSETPRINT(reg, 3, CARD2_8SEL); 251 ISSETPRINT(reg, 3, CARD1_8SEL); 252 #endif /* TX392X */ 253 254 printf("\n"); 255 256 /* 257 * Memory config 4 register 258 */ 259 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 260 printf(" config4:"); 261 ISSETPRINT(reg, 4, ENBANK1HDRAM); 262 ISSETPRINT(reg, 4, ENBANK0HDRAM); 263 ISSETPRINT(reg, 4, ENARB); 264 ISSETPRINT(reg, 4, DISSNOOP); 265 ISSETPRINT(reg, 4, CLRWRBUSERRINT); 266 ISSETPRINT(reg, 4, ENBANK1OPT); 267 ISSETPRINT(reg, 4, ENBANK0OPT); 268 ISSETPRINT(reg, 4, ENWATCH); 269 ISSETPRINT(reg, 4, MEMPOWERDOWN); 270 ISSETPRINT(reg, 4, ENRFSH1); 271 ISSETPRINT(reg, 4, ENRFSH0); 272 if (reg & TX39_MEMCONFIG4_ENWATCH) { 273 i = TX39_MEMCONFIG4_WATCHTIMEVAL(reg); 274 i = (1000 * (i + 1) * 64) / 36864; 275 printf("WatchDogTimerRate: %dus", i); 276 } 277 printf("\n"); 278 } 279 #endif /* TX39BIU_DEBUG */ 280
Indexes created Fri Oct 31 11:10:07 GMT 2025