tx39biu.c revision 1.2
1 /* $NetBSD: tx39biu.c,v 1.2 1999/12/12 17:05:38 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include "opt_tx39_debug.h" 29 #include "opt_tx39_watchdogtimer.h" 30 #include "opt_tx39biudebug.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 36 #include <machine/bus.h> 37 38 #include <hpcmips/tx/tx39var.h> 39 #include <hpcmips/tx/tx39biureg.h> 40 41 #include <hpcmips/tx/txcsbusvar.h> 42 43 #define ISSET(x, s) ((x) & (1 << (s))) 44 #define ISSETPRINT(r, s, m) __is_set_print((u_int32_t)(r), \ 45 TX39_MEMCONFIG##s##_##m, #m) 46 47 int tx39biu_match __P((struct device*, struct cfdata*, void*)); 48 void tx39biu_attach __P((struct device*, struct device*, void*)); 49 void tx39biu_callback __P((struct device*)); 50 int tx39biu_print __P((void*, const char*)); 51 int tx39biu_intr __P((void*)); 52 53 static void *__sc; /* XXX */ 54 55 void tx39biu_dump __P((tx_chipset_tag_t)); 56 57 struct tx39biu_softc { 58 struct device sc_dev; 59 tx_chipset_tag_t sc_tc; 60 }; 61 62 struct cfattach tx39biu_ca = { 63 sizeof(struct tx39biu_softc), tx39biu_match, tx39biu_attach 64 }; 65 66 int 67 tx39biu_match(parent, cf, aux) 68 struct device *parent; 69 struct cfdata *cf; 70 void *aux; 71 { 72 return 1; 73 } 74 75 void 76 tx39biu_attach(parent, self, aux) 77 struct device *parent; 78 struct device *self; 79 void *aux; 80 { 81 struct txsim_attach_args *ta = aux; 82 struct tx39biu_softc *sc = (void*)self; 83 tx_chipset_tag_t tc; 84 #ifdef TX39_WATCHDOGTIMER 85 txreg_t reg; 86 #endif 87 88 sc->sc_tc = tc = ta->ta_tc; 89 printf("\n"); 90 #ifdef TX39BIUDEBUG 91 tx39biu_dump(tc); 92 #endif 93 94 #ifdef TX39_WATCHDOGTIMER 95 /* 96 * CLRWRBUSERRINT Bus error connected CPU HwInt0 97 */ 98 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 99 reg |= TX39_MEMCONFIG4_ENWATCH; 100 reg = TX39_MEMCONFIG4_WATCHTIMEVAL_SET(reg, 0xf); 101 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg); 102 103 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 104 if (reg & TX39_MEMCONFIG4_ENWATCH) { 105 int i; 106 i = TX39_MEMCONFIG4_WATCHTIMEVAL(reg); 107 i = (1000 * (i + 1) * 64) / 36864; 108 printf("WatchDogTimerRate: %dus\n", i); 109 } 110 #endif 111 __sc = sc; 112 113 /* Clear watch dog timer interrupt */ 114 tx39biu_intr(sc); 115 116 /* 117 * Chip select virtual bridge 118 */ 119 config_defer(self, tx39biu_callback); 120 } 121 122 void 123 tx39biu_callback(self) 124 struct device *self; 125 { 126 struct tx39biu_softc *sc = (void*)self; 127 struct csbus_attach_args cba; 128 129 cba.cba_busname = "txcsbus"; 130 cba.cba_tc = sc->sc_tc; 131 config_found(self, &cba, tx39biu_print); 132 } 133 134 int 135 tx39biu_print(aux, pnp) 136 void *aux; 137 const char *pnp; 138 { 139 return pnp ? QUIET : UNCONF; 140 } 141 142 int 143 tx39biu_intr(arg) 144 void *arg; 145 { 146 struct tx39biu_softc *sc = __sc; 147 tx_chipset_tag_t tc; 148 txreg_t reg; 149 150 if (!sc) { 151 return 0; 152 } 153 tc = sc->sc_tc; 154 /* Clear interrupt */ 155 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 156 reg |= TX39_MEMCONFIG4_CLRWRBUSERRINT; 157 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg); 158 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 159 reg &= ~TX39_MEMCONFIG4_CLRWRBUSERRINT; 160 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg); 161 162 return 0; 163 } 164 165 void 166 tx39biu_dump(tc) 167 tx_chipset_tag_t tc; 168 { 169 char *rowsel[] = {"18,17:9", "22,18,20,19,17:9", "20,22,21,19,17:9", "22,23,21,19,17:9"}; 170 char *colsel[] = {"22,20,18,8:1", "19,18,8:2", "21,20,18,8:2", "23,22,20,18,8:2", 171 "24,22,20,18,8:2", "18,p,X,8:0","22,p,X,21,8:0", "18,p,X,21,8:1", 172 "22,p,X,23,21,8:1", "24,23,21,8:2"}; 173 txreg_t reg; 174 int i; 175 /* 176 * Memory config 0 register 177 */ 178 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 179 printf(" config0:"); 180 ISSETPRINT(reg, 0, ENDCLKOUTTRI); 181 ISSETPRINT(reg, 0, DISDQMINIT); 182 ISSETPRINT(reg, 0, ENSDRAMPD); 183 ISSETPRINT(reg, 0, SHOWDINO); 184 ISSETPRINT(reg, 0, ENRMAP2); 185 ISSETPRINT(reg, 0, ENRMAP1); 186 ISSETPRINT(reg, 0, ENWRINPAGE); 187 ISSETPRINT(reg, 0, ENCS3USER); 188 ISSETPRINT(reg, 0, ENCS2USER); 189 ISSETPRINT(reg, 0, ENCS1USER); 190 ISSETPRINT(reg, 0, ENCS1DRAM); 191 ISSETPRINT(reg, 0, CS3SIZE); 192 ISSETPRINT(reg, 0, CS2SIZE); 193 ISSETPRINT(reg, 0, CS1SIZE); 194 ISSETPRINT(reg, 0, CS0SIZE); 195 printf("\n"); 196 for (i = 0; i < 2; i++) { 197 int r, c; 198 printf(" BANK%d: ", i); 199 switch (i ? TX39_MEMCONFIG0_BANK1CONF(reg) 200 : TX39_MEMCONFIG0_BANK0CONF(reg)) { 201 case TX39_MEMCONFIG0_BANKCONF_16BITSDRAM: 202 printf("16bit SDRAM"); 203 break; 204 case TX39_MEMCONFIG0_BANKCONF_8BITSDRAM: 205 printf("8bit SDRAM"); 206 break; 207 case TX39_MEMCONFIG0_BANKCONF_32BITSDHDRAM: 208 printf("32bit DRAM/HDRAM"); 209 break; 210 case TX39_MEMCONFIG0_BANKCONF_16BITSDHDRAM: 211 printf("16bit DRAM/HDRAM"); 212 break; 213 } 214 if (i == 1) { 215 r = TX39_MEMCONFIG0_ROWSEL1(reg); 216 c = TX39_MEMCONFIG0_COLSEL1(reg); 217 } else { 218 r = TX39_MEMCONFIG0_ROWSEL0(reg); 219 c = TX39_MEMCONFIG0_COLSEL0(reg); 220 } 221 printf(" ROW %s COL %s\n", rowsel[r], colsel[c]); 222 } 223 224 /* 225 * Memory config 3 register 226 */ 227 printf(" config3:"); 228 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 229 #ifdef TX391X 230 ISSETPRINT(reg, 3, ENMCS3PAGE); 231 ISSETPRINT(reg, 3, ENMCS2PAGE); 232 ISSETPRINT(reg, 3, ENMCS1PAGE); 233 ISSETPRINT(reg, 3, ENMCS0PAGE); 234 #endif /* TX391X */ 235 ISSETPRINT(reg, 3, ENCS3PAGE); 236 ISSETPRINT(reg, 3, ENCS2PAGE); 237 ISSETPRINT(reg, 3, ENCS1PAGE); 238 ISSETPRINT(reg, 3, ENCS0PAGE); 239 ISSETPRINT(reg, 3, CARD2WAITEN); 240 ISSETPRINT(reg, 3, CARD1WAITEN); 241 ISSETPRINT(reg, 3, CARD2IOEN); 242 ISSETPRINT(reg, 3, CARD1IOEN); 243 #ifdef TX391X 244 ISSETPRINT(reg, 3, PORT8SEL); 245 #endif /* TX391X */ 246 #ifdef TX392X 247 ISSETPRINT(reg, 3, CARD2_8SEL); 248 ISSETPRINT(reg, 3, CARD1_8SEL); 249 #endif /* TX392X */ 250 251 printf("\n"); 252 253 /* 254 * Memory config 4 register 255 */ 256 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 257 printf(" config4:"); 258 ISSETPRINT(reg, 4, ENBANK1HDRAM); 259 ISSETPRINT(reg, 4, ENBANK0HDRAM); 260 ISSETPRINT(reg, 4, ENARB); 261 ISSETPRINT(reg, 4, DISSNOOP); 262 ISSETPRINT(reg, 4, CLRWRBUSERRINT); 263 ISSETPRINT(reg, 4, ENBANK1OPT); 264 ISSETPRINT(reg, 4, ENBANK0OPT); 265 ISSETPRINT(reg, 4, ENWATCH); 266 ISSETPRINT(reg, 4, MEMPOWERDOWN); 267 ISSETPRINT(reg, 4, ENRFSH1); 268 ISSETPRINT(reg, 4, ENRFSH0); 269 if (reg & TX39_MEMCONFIG4_ENWATCH) { 270 i = TX39_MEMCONFIG4_WATCHTIMEVAL(reg); 271 i = (1000 * (i + 1) * 64) / 36864; 272 printf("WatchDogTimerRate: %dus", i); 273 } 274 printf("\n"); 275 } 276 277
Indexes created Sat Nov 01 19:09:55 GMT 2025