tx39biureg.h revision 1.2.6.2
1 1.2.6.2 bouyer /* $NetBSD: tx39biureg.h,v 1.2.6.2 2000/11/20 20:47:15 bouyer Exp $ */ 2 1.2.6.2 bouyer 3 1.2.6.2 bouyer /* 4 1.2.6.2 bouyer * Copyright (c) 1999, 2000, by UCHIYAMA Yasushi 5 1.2.6.2 bouyer * All rights reserved. 6 1.2.6.2 bouyer * 7 1.2.6.2 bouyer * Redistribution and use in source and binary forms, with or without 8 1.2.6.2 bouyer * modification, are permitted provided that the following conditions 9 1.2.6.2 bouyer * are met: 10 1.2.6.2 bouyer * 1. Redistributions of source code must retain the above copyright 11 1.2.6.2 bouyer * notice, this list of conditions and the following disclaimer. 12 1.2.6.2 bouyer * 2. The name of the developer may NOT be used to endorse or promote products 13 1.2.6.2 bouyer * derived from this software without specific prior written permission. 14 1.2.6.2 bouyer * 15 1.2.6.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 1.2.6.2 bouyer * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 1.2.6.2 bouyer * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 1.2.6.2 bouyer * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 1.2.6.2 bouyer * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 1.2.6.2 bouyer * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 1.2.6.2 bouyer * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 1.2.6.2 bouyer * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 1.2.6.2 bouyer * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 1.2.6.2 bouyer * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 1.2.6.2 bouyer * SUCH DAMAGE. 26 1.2.6.2 bouyer * 27 1.2.6.2 bouyer */ 28 1.2.6.2 bouyer /* 29 1.2.6.2 bouyer * Toshiba TX3912/3922 BIU module (Bus Interface Unit) 30 1.2.6.2 bouyer */ 31 1.2.6.2 bouyer 32 1.2.6.2 bouyer /* 33 1.2.6.2 bouyer * System Address Map 34 1.2.6.2 bouyer */ 35 1.2.6.2 bouyer #define TX39_SYSADDR_DRAMBANK0CS1 0x00000000 36 1.2.6.2 bouyer #define TX39_SYSADDR_DRAMBANK1CS1 0x02000000 37 1.2.6.2 bouyer #define TX39_SYSADDR_DRAMBANK0 0x04000000 38 1.2.6.2 bouyer #define TX39_SYSADDR_DRAMBANK1 0x06000000 39 1.2.6.2 bouyer #define TX39_SYSADDR_DRAMBANK_LEN 0x02000000 40 1.2.6.2 bouyer 41 1.2.6.2 bouyer #define TX39_SYSADDR_CARD1 0x08000000 42 1.2.6.2 bouyer #define TX39_SYSADDR_CARD2 0x0C000000 43 1.2.6.2 bouyer /* 64MByte */ 44 1.2.6.2 bouyer #define TX39_SYSADDR_CARD_SIZE 0x04000000 45 1.2.6.2 bouyer 46 1.2.6.2 bouyer #define TX39_SYSADDR_CS1 0x10000000 47 1.2.6.2 bouyer #define TX39_SYSADDR_CS2 0x10400000 48 1.2.6.2 bouyer #define TX39_SYSADDR_CS3 0x10800000 49 1.2.6.2 bouyer /* 4MByte */ 50 1.2.6.2 bouyer #define TX39_SYSADDR_CS_SIZE 0x00400000 51 1.2.6.2 bouyer 52 1.2.6.2 bouyer #define TX39_SYSADDR_CONFIG_REG 0x10c00000 53 1.2.6.2 bouyer #define TX39_SYSADDR_CONFIG_REG_LEN 0x00200000 54 1.2.6.2 bouyer 55 1.2.6.2 bouyer #define TX39_SYSADDR_SDRAMBANK0MODE_REG 0x10e00000 56 1.2.6.2 bouyer #define TX39_SYSADDR_SDRAMBANK1MODE_REG 0x10f00000 57 1.2.6.2 bouyer #define TX39_SYSADDR_CS0 0x11000000 58 1.2.6.2 bouyer #define TX39_SYSADDR_KUSEG_DRAMBANK0CS1 0x40000000 59 1.2.6.2 bouyer #define TX39_SYSADDR_KUSEG_DRAMBANK1CS1 0x42000000 60 1.2.6.2 bouyer #define TX39_SYSADDR_KUSEG_DRAMBANK0 0x44000000 61 1.2.6.2 bouyer #define TX39_SYSADDR_KUSEG_DRAMBANK1 0x46000000 62 1.2.6.2 bouyer #define TX39_SYSADDR_KUSEG_CS0 0x50000000 63 1.2.6.2 bouyer #define TX39_SYSADDR_KUSEG_CS1 0x58000000 64 1.2.6.2 bouyer #define TX39_SYSADDR_KUSEG_CS2 0x5c000000 65 1.2.6.2 bouyer #define TX39_SYSADDR_KUSEG_CS3 0x60000000 66 1.2.6.2 bouyer #define TX39_SYSADDR_CARD1MEM 0x64000000 67 1.2.6.2 bouyer #define TX39_SYSADDR_CARD2MEM 0x68000000 68 1.2.6.2 bouyer #define TX39_SYSADDR_MCS0 0x6c000000 69 1.2.6.2 bouyer #define TX39_SYSADDR_MCS1 0x70000000 70 1.2.6.2 bouyer #ifdef TX391X 71 1.2.6.2 bouyer #define TX39_SYSADDR_MCS2 0x74000000 72 1.2.6.2 bouyer #define TX39_SYSADDR_MCS3 0x78000000 73 1.2.6.2 bouyer #endif /* TX391X */ 74 1.2.6.2 bouyer /* 64MByte */ 75 1.2.6.2 bouyer #define TX39_SYSADDR_MCS_SIZE 0x04000000 76 1.2.6.2 bouyer 77 1.2.6.2 bouyer /* 78 1.2.6.2 bouyer * BIU module registers. 79 1.2.6.2 bouyer */ 80 1.2.6.2 bouyer #define TX39_MEMCONFIG0_REG 0x00 81 1.2.6.2 bouyer #define TX39_MEMCONFIG1_REG 0x04 82 1.2.6.2 bouyer #define TX39_MEMCONFIG2_REG 0x08 83 1.2.6.2 bouyer #define TX39_MEMCONFIG3_REG 0x0C 84 1.2.6.2 bouyer #define TX39_MEMCONFIG4_REG 0x10 85 1.2.6.2 bouyer #define TX39_MEMCONFIG5_REG 0x14 86 1.2.6.2 bouyer #define TX39_MEMCONFIG6_REG 0x18 87 1.2.6.2 bouyer #define TX39_MEMCONFIG7_REG 0x1C 88 1.2.6.2 bouyer #define TX39_MEMCONFIG8_REG 0x20 89 1.2.6.2 bouyer 90 1.2.6.2 bouyer /* 91 1.2.6.2 bouyer * Memory Configuration 0 Register 92 1.2.6.2 bouyer */ 93 1.2.6.2 bouyer /* R/W */ 94 1.2.6.2 bouyer #define TX39_MEMCONFIG0_ENDCLKOUTTRI 0x40000000 95 1.2.6.2 bouyer #define TX39_MEMCONFIG0_DISDQMINIT 0x20000000 96 1.2.6.2 bouyer #define TX39_MEMCONFIG0_ENSDRAMPD 0x10000000 97 1.2.6.2 bouyer #define TX39_MEMCONFIG0_SHOWDINO 0x08000000 98 1.2.6.2 bouyer #define TX39_MEMCONFIG0_ENRMAP2 0x04000000 99 1.2.6.2 bouyer #define TX39_MEMCONFIG0_ENRMAP1 0x02000000 100 1.2.6.2 bouyer #define TX39_MEMCONFIG0_ENWRINPAGE 0x01000000 101 1.2.6.2 bouyer #define TX39_MEMCONFIG0_ENCS3USER 0x00800000 102 1.2.6.2 bouyer #define TX39_MEMCONFIG0_ENCS2USER 0x00400000 103 1.2.6.2 bouyer #define TX39_MEMCONFIG0_ENCS1USER 0x00200000 104 1.2.6.2 bouyer #define TX39_MEMCONFIG0_ENCS1DRAM 0x00100000 105 1.2.6.2 bouyer 106 1.2.6.2 bouyer #define TX39_MEMCONFIG0_BANK1CONF_SHIFT 18 107 1.2.6.2 bouyer #define TX39_MEMCONFIG0_BANK1CONF_MASK 0x3 108 1.2.6.2 bouyer #define TX39_MEMCONFIG0_BANK1CONF(cr) \ 109 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG0_BANK1CONF_SHIFT) & \ 110 1.2.6.2 bouyer TX39_MEMCONFIG0_BANK1CONF_MASK) 111 1.2.6.2 bouyer #define TX39_MEMCONFIG0_BANK1CONF_SET(cr, val) \ 112 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG0_BANK1CONF_SHIFT) & \ 113 1.2.6.2 bouyer (TX39_MEMCONFIG0_BANK1CONF_MASK << TX39_MEMCONFIG0_BANK1CONF_SHIFT))) 114 1.2.6.2 bouyer #define TX39_MEMCONFIG0_BANK0CONF_SHIFT 16 115 1.2.6.2 bouyer #define TX39_MEMCONFIG0_BANK0CONF_MASK 0x3 116 1.2.6.2 bouyer #define TX39_MEMCONFIG0_BANK0CONF(cr) \ 117 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG0_BANK0CONF_SHIFT) & \ 118 1.2.6.2 bouyer TX39_MEMCONFIG0_BANK0CONF_MASK) 119 1.2.6.2 bouyer #define TX39_MEMCONFIG0_BANK0CONF_SET(cr, val) \ 120 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG0_BANK0CONF_SHIFT) & \ 121 1.2.6.2 bouyer (TX39_MEMCONFIG0_BANK0CONF_MASK << TX39_MEMCONFIG0_BANK0CONF_SHIFT))) 122 1.2.6.2 bouyer #define TX39_MEMCONFIG0_BANKCONF_16BITSDRAM 0x3 123 1.2.6.2 bouyer #define TX39_MEMCONFIG0_BANKCONF_8BITSDRAM 0x2 124 1.2.6.2 bouyer #define TX39_MEMCONFIG0_BANKCONF_32BITSDHDRAM 0x1 125 1.2.6.2 bouyer #define TX39_MEMCONFIG0_BANKCONF_16BITSDHDRAM 0x0 126 1.2.6.2 bouyer 127 1.2.6.2 bouyer #define TX39_MEMCONFIG0_ROWSEL1_SHIFT 14 128 1.2.6.2 bouyer #define TX39_MEMCONFIG0_ROWSEL1_MASK 0x3 129 1.2.6.2 bouyer #define TX39_MEMCONFIG0_ROWSEL1(cr) \ 130 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG0_ROWSEL1_SHIFT) & \ 131 1.2.6.2 bouyer TX39_MEMCONFIG0_ROWSEL1_MASK) 132 1.2.6.2 bouyer #define TX39_MEMCONFIG0_ROWSEL1_SET(cr, val) \ 133 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG0_ROWSEL1_SHIFT) & \ 134 1.2.6.2 bouyer (TX39_MEMCONFIG0_ROWSEL1_MASK << TX39_MEMCONFIG0_ROWSEL1_SHIFT))) 135 1.2.6.2 bouyer #define TX39_MEMCONFIG0_ROWSEL0_SHIFT 12 136 1.2.6.2 bouyer #define TX39_MEMCONFIG0_ROWSEL0_MASK 0x3 137 1.2.6.2 bouyer #define TX39_MEMCONFIG0_ROWSEL0(cr) \ 138 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG0_ROWSEL0_SHIFT) & \ 139 1.2.6.2 bouyer TX39_MEMCONFIG0_ROWSEL0_MASK) 140 1.2.6.2 bouyer #define TX39_MEMCONFIG0_ROWSEL0_SET(cr, val) \ 141 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG0_ROWSEL0_SHIFT) & \ 142 1.2.6.2 bouyer (TX39_MEMCONFIG0_ROWSEL0_MASK << TX39_MEMCONFIG0_ROWSEL0_SHIFT))) 143 1.2.6.2 bouyer 144 1.2.6.2 bouyer #define TX39_MEMCONFIG0_COLSEL1_SHIFT 8 145 1.2.6.2 bouyer #define TX39_MEMCONFIG0_COLSEL1_MASK 0xf 146 1.2.6.2 bouyer #define TX39_MEMCONFIG0_COLSEL1(cr) \ 147 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG0_COLSEL1_SHIFT) & \ 148 1.2.6.2 bouyer TX39_MEMCONFIG0_COLSEL1_MASK) 149 1.2.6.2 bouyer #define TX39_MEMCONFIG0_COLSEL1_SET(cr, val) \ 150 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG0_COLSEL1_SHIFT) & \ 151 1.2.6.2 bouyer (TX39_MEMCONFIG0_COLSEL1_MASK << TX39_MEMCONFIG0_COLSEL1_SHIFT))) 152 1.2.6.2 bouyer #define TX39_MEMCONFIG0_COLSEL0_SHIFT 4 153 1.2.6.2 bouyer #define TX39_MEMCONFIG0_COLSEL0_MASK 0xf 154 1.2.6.2 bouyer #define TX39_MEMCONFIG0_COLSEL0(cr) \ 155 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG0_COLSEL0_SHIFT) & \ 156 1.2.6.2 bouyer TX39_MEMCONFIG0_COLSEL0_MASK) 157 1.2.6.2 bouyer #define TX39_MEMCONFIG0_COLSEL0_SET(cr, val) \ 158 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG0_COLSEL0_SHIFT) & \ 159 1.2.6.2 bouyer (TX39_MEMCONFIG0_COLSEL0_MASK << TX39_MEMCONFIG0_COLSEL0_SHIFT))) 160 1.2.6.2 bouyer 161 1.2.6.2 bouyer #define TX39_MEMCONFIG0_CS3SIZE 0x00000008 162 1.2.6.2 bouyer #define TX39_MEMCONFIG0_CS2SIZE 0x00000004 163 1.2.6.2 bouyer #define TX39_MEMCONFIG0_CS1SIZE 0x00000002 164 1.2.6.2 bouyer #define TX39_MEMCONFIG0_CS0SIZE 0x00000001 165 1.2.6.2 bouyer 166 1.2.6.2 bouyer /* 167 1.2.6.2 bouyer * Memory Configuration 1 Register 168 1.2.6.2 bouyer */ 169 1.2.6.2 bouyer #ifdef TX391X 170 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT 28 171 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS3ACCVAL1_MASK 0xf 172 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS3ACCVAL1(cr) \ 173 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT) & \ 174 1.2.6.2 bouyer TX39_MEMCONFIG1_MCS3ACCVAL1_MASK) 175 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS3ACCVAL1_SET(cr, val) \ 176 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT) & \ 177 1.2.6.2 bouyer (TX39_MEMCONFIG1_MCS3ACCVAL1_MASK << TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT))) 178 1.2.6.2 bouyer 179 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT 24 180 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS3ACCVAL2_MASK 0xf 181 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS3ACCVAL2(cr) \ 182 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT) & \ 183 1.2.6.2 bouyer TX39_MEMCONFIG1_MCS3ACCVAL2_MASK) 184 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS3ACCVAL2_SET(cr, val) \ 185 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT) & \ 186 1.2.6.2 bouyer (TX39_MEMCONFIG1_MCS3ACCVAL2_MASK << TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT))) 187 1.2.6.2 bouyer 188 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT 20 189 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS2ACCVAL1_MASK 0xf 190 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS2ACCVAL1(cr) \ 191 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT) & \ 192 1.2.6.2 bouyer TX39_MEMCONFIG1_MCS2ACCVAL1_MASK) 193 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS2ACCVAL1_SET(cr, val) \ 194 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT) & \ 195 1.2.6.2 bouyer (TX39_MEMCONFIG1_MCS2ACCVAL1_MASK << TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT))) 196 1.2.6.2 bouyer 197 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT 16 198 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS2ACCVAL2_MASK 0xf 199 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS2ACCVAL2(cr) \ 200 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT) & \ 201 1.2.6.2 bouyer TX39_MEMCONFIG1_MCS2ACCVAL2_MASK) 202 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS2ACCVAL2_SET(cr, val) \ 203 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT) & \ 204 1.2.6.2 bouyer (TX39_MEMCONFIG1_MCS2ACCVAL2_MASK << TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT))) 205 1.2.6.2 bouyer #endif /* TX391X */ 206 1.2.6.2 bouyer #ifdef TX392X 207 1.2.6.2 bouyer #define TX39_MEMCONFIG1_C48MPLLON 0x40000000 208 1.2.6.2 bouyer #define TX39_MEMCONFIG1_ENMCS1BE 0x20000000 209 1.2.6.2 bouyer #define TX39_MEMCONFIG1_ENMCS0BE 0x10000000 210 1.2.6.2 bouyer #define TX39_MEMCONFIG1_ENMCS1ACC 0x08000000 211 1.2.6.2 bouyer #define TX39_MEMCONFIG1_ENMCS0ACC 0x04000000 212 1.2.6.2 bouyer #define TX39_MEMCONFIG1_BCLKDIV_SHIFT 23 213 1.2.6.2 bouyer #define TX39_MEMCONFIG1_BCLKDIV_MASK 0x7 214 1.2.6.2 bouyer #define TX39_MEMCONFIG1_BCLKDIV(cr) \ 215 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG1_BCLKDIV_SHIFT) & \ 216 1.2.6.2 bouyer TX39_MEMCONFIG1_BCLKDIV_MASK) 217 1.2.6.2 bouyer #define TX39_MEMCONFIG1_BCLKDIV_SET(cr, val) \ 218 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG1_BCLKDIV_SHIFT) & \ 219 1.2.6.2 bouyer (TX39_MEMCONFIG1_BCLKDIV_MASK << TX39_MEMCONFIG1_BCLKDIV_SHIFT))) 220 1.2.6.2 bouyer #define TX39_MEMCONFIG1_ENBCLK 0x00400000 221 1.2.6.2 bouyer #define TX39_MEMCONFIG1_ENMCS1PAGE 0x00200000 222 1.2.6.2 bouyer #define TX39_MEMCONFIG1_ENMCS0PAGE 0x00100000 223 1.2.6.2 bouyer #define TX39_MEMCONFIG1_ENMCS1WAIT 0x00080000 224 1.2.6.2 bouyer #define TX39_MEMCONFIG1_ENMCS0WAIT 0x00040000 225 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS1_32 0x00020000 226 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS0_32 0x00010000 227 1.2.6.2 bouyer #endif /* TX392X */ 228 1.2.6.2 bouyer 229 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT 12 230 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS1ACCVAL1_MASK 0xf 231 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS1ACCVAL1(cr) \ 232 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT) & \ 233 1.2.6.2 bouyer TX39_MEMCONFIG1_MCS1ACCVAL1_MASK) 234 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS1ACCVAL1_SET(cr, val) \ 235 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT) & \ 236 1.2.6.2 bouyer (TX39_MEMCONFIG1_MCS1ACCVAL1_MASK << TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT))) 237 1.2.6.2 bouyer 238 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT 8 239 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS1ACCVAL2_MASK 0xf 240 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS1ACCVAL2(cr) \ 241 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT) & \ 242 1.2.6.2 bouyer TX39_MEMCONFIG1_MCS1ACCVAL2_MASK) 243 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS1ACCVAL2_SET(cr, val) \ 244 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT) & \ 245 1.2.6.2 bouyer (TX39_MEMCONFIG1_MCS1ACCVAL2_MASK << TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT))) 246 1.2.6.2 bouyer 247 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT 4 248 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS0ACCVAL1_MASK 0xf 249 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS0ACCVAL1(cr) \ 250 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT) & \ 251 1.2.6.2 bouyer TX39_MEMCONFIG1_MCS0ACCVAL1_MASK) 252 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS0ACCVAL1_SET(cr, val) \ 253 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT) & \ 254 1.2.6.2 bouyer (TX39_MEMCONFIG1_MCS0ACCVAL1_MASK << TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT))) 255 1.2.6.2 bouyer 256 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT 0 257 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS0ACCVAL2_MASK 0xf 258 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS0ACCVAL2(cr) \ 259 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT) & \ 260 1.2.6.2 bouyer TX39_MEMCONFIG1_MCS0ACCVAL2_MASK) 261 1.2.6.2 bouyer #define TX39_MEMCONFIG1_MCS0ACCVAL2_SET(cr, val) \ 262 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT) & \ 263 1.2.6.2 bouyer (TX39_MEMCONFIG1_MCS0ACCVAL2_MASK << TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT))) 264 1.2.6.2 bouyer 265 1.2.6.2 bouyer /* 266 1.2.6.2 bouyer * Memory Configuration 2 Register 267 1.2.6.2 bouyer */ 268 1.2.6.2 bouyer /* Define access timing. not required yet */ 269 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT 28 270 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS3ACCVAL1_MASK 0xf 271 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS3ACCVAL1(cr) \ 272 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT) & \ 273 1.2.6.2 bouyer TX39_MEMCONFIG2_CS3ACCVAL1_MASK) 274 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS3ACCVAL1_SET(cr, val) \ 275 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT) & \ 276 1.2.6.2 bouyer (TX39_MEMCONFIG2_CS3ACCVAL1_MASK << TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT))) 277 1.2.6.2 bouyer 278 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT 24 279 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS3ACCVAL2_MASK 0xf 280 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS3ACCVAL2(cr) \ 281 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT) & \ 282 1.2.6.2 bouyer TX39_MEMCONFIG2_CS3ACCVAL2_MASK) 283 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS3ACCVAL2_SET(cr, val) \ 284 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT) & \ 285 1.2.6.2 bouyer (TX39_MEMCONFIG2_CS3ACCVAL2_MASK << TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT))) 286 1.2.6.2 bouyer 287 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT 20 288 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS2ACCVAL1_MASK 0xf 289 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS2ACCVAL1(cr) \ 290 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT) & \ 291 1.2.6.2 bouyer TX39_MEMCONFIG2_CS2ACCVAL1_MASK) 292 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS2ACCVAL1_SET(cr, val) \ 293 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT) & \ 294 1.2.6.2 bouyer (TX39_MEMCONFIG2_CS2ACCVAL1_MASK << TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT))) 295 1.2.6.2 bouyer 296 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT 16 297 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS2ACCVAL2_MASK 0xf 298 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS2ACCVAL2(cr) \ 299 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT) & \ 300 1.2.6.2 bouyer TX39_MEMCONFIG2_CS2ACCVAL2_MASK) 301 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS2ACCVAL2_SET(cr, val) \ 302 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT) & \ 303 1.2.6.2 bouyer (TX39_MEMCONFIG2_CS2ACCVAL2_MASK << TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT))) 304 1.2.6.2 bouyer 305 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT 12 306 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS1ACCVAL1_MASK 0xf 307 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS1ACCVAL1(cr) \ 308 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT) & \ 309 1.2.6.2 bouyer TX39_MEMCONFIG2_CS1ACCVAL1_MASK) 310 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS1ACCVAL1_SET(cr, val) \ 311 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT) & \ 312 1.2.6.2 bouyer (TX39_MEMCONFIG2_CS1ACCVAL1_MASK << TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT))) 313 1.2.6.2 bouyer 314 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT 8 315 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS1ACCVAL2_MASK 0xf 316 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS1ACCVAL2(cr) \ 317 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT) & \ 318 1.2.6.2 bouyer TX39_MEMCONFIG2_CS1ACCVAL2_MASK) 319 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS1ACCVAL2_SET(cr, val) \ 320 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT) & \ 321 1.2.6.2 bouyer (TX39_MEMCONFIG2_CS1ACCVAL2_MASK << TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT))) 322 1.2.6.2 bouyer 323 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT 4 324 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS0ACCVAL1_MASK 0xf 325 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS0ACCVAL1(cr) \ 326 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT) & \ 327 1.2.6.2 bouyer TX39_MEMCONFIG2_CS0ACCVAL1_MASK) 328 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS0ACCVAL1_SET(cr, val) \ 329 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT) & \ 330 1.2.6.2 bouyer (TX39_MEMCONFIG2_CS0ACCVAL1_MASK << TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT))) 331 1.2.6.2 bouyer 332 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT 0 333 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS0ACCVAL2_MASK 0xf 334 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS0ACCVAL2(cr) \ 335 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT) & \ 336 1.2.6.2 bouyer TX39_MEMCONFIG2_CS0ACCVAL2_MASK) 337 1.2.6.2 bouyer #define TX39_MEMCONFIG2_CS0ACCVAL2_SET(cr, val) \ 338 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT) & \ 339 1.2.6.2 bouyer (TX39_MEMCONFIG2_CS0ACCVAL2_MASK << TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT))) 340 1.2.6.2 bouyer 341 1.2.6.2 bouyer /* 342 1.2.6.2 bouyer * Memory Configuration 3 Register 343 1.2.6.2 bouyer */ 344 1.2.6.2 bouyer /* Define access timing, enable read page mode, PC-Card. */ 345 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT 28 346 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD2ACCVAL_MASK 0xf 347 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD2ACCVAL(cr) \ 348 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT) & \ 349 1.2.6.2 bouyer TX39_MEMCONFIG3_CARD2ACCVAL_MASK) 350 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD2ACCVAL_SET(cr, val) \ 351 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT) & \ 352 1.2.6.2 bouyer (TX39_MEMCONFIG3_CARD2ACCVAL_MASK << TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT))) 353 1.2.6.2 bouyer 354 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT 24 355 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD1ACCVAL_MASK 0xf 356 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD1ACCVAL(cr) \ 357 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT) & \ 358 1.2.6.2 bouyer TX39_MEMCONFIG3_CARD1ACCVAL_MASK) 359 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD1ACCVAL_SET(cr, val) \ 360 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT) & \ 361 1.2.6.2 bouyer (TX39_MEMCONFIG3_CARD1ACCVAL_MASK << TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT))) 362 1.2.6.2 bouyer 363 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT 20 364 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD2IOACCVAL_MASK 0xf 365 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD2IOACCVAL(cr) \ 366 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT) & \ 367 1.2.6.2 bouyer TX39_MEMCONFIG3_CARD2IOACCVAL_MASK) 368 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD2IOACCVAL_SET(cr, val) \ 369 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT) & \ 370 1.2.6.2 bouyer (TX39_MEMCONFIG3_CARD2IOACCVAL_MASK << TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT))) 371 1.2.6.2 bouyer 372 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT 16 373 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD1IOACCVAL_MASK 0xf 374 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD1IOACCVAL(cr) \ 375 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT) & \ 376 1.2.6.2 bouyer TX39_MEMCONFIG3_CARD1IOACCVAL_MASK) 377 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD1IOACCVAL_SET(cr, val) \ 378 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT) & \ 379 1.2.6.2 bouyer (TX39_MEMCONFIG3_CARD1IOACCVAL_MASK << TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT))) 380 1.2.6.2 bouyer #ifdef TX391X 381 1.2.6.2 bouyer #define TX39_MEMCONFIG3_ENMCS3PAGE 0x00008000 382 1.2.6.2 bouyer #define TX39_MEMCONFIG3_ENMCS2PAGE 0x00004000 383 1.2.6.2 bouyer #define TX39_MEMCONFIG3_ENMCS1PAGE 0x00002000 384 1.2.6.2 bouyer #define TX39_MEMCONFIG3_ENMCS0PAGE 0x00001000 385 1.2.6.2 bouyer #endif /* TX391X */ 386 1.2.6.2 bouyer #define TX39_MEMCONFIG3_ENCS3PAGE 0x00000800 387 1.2.6.2 bouyer #define TX39_MEMCONFIG3_ENCS2PAGE 0x00000400 388 1.2.6.2 bouyer #define TX39_MEMCONFIG3_ENCS1PAGE 0x00000200 389 1.2.6.2 bouyer #define TX39_MEMCONFIG3_ENCS0PAGE 0x00000100 390 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD2WAITEN 0x00000080 391 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD1WAITEN 0x00000040 392 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD2IOEN 0x00000020 393 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD1IOEN 0x00000010 394 1.2.6.2 bouyer #ifdef TX391X 395 1.2.6.2 bouyer #define TX39_MEMCONFIG3_PORT8SEL 0x00000008 396 1.2.6.2 bouyer #endif /* TX391X */ 397 1.2.6.2 bouyer #ifdef TX392X 398 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD2_8SEL 0x00000008 399 1.2.6.2 bouyer #define TX39_MEMCONFIG3_CARD1_8SEL 0x00000004 400 1.2.6.2 bouyer #endif /* TX392X */ 401 1.2.6.2 bouyer /* 402 1.2.6.2 bouyer * Memory Configuration 4 Register 403 1.2.6.2 bouyer */ 404 1.2.6.2 bouyer /* DMA */ 405 1.2.6.2 bouyer #define TX39_MEMCONFIG4_ENBANK1HDRAM 0x80000000 406 1.2.6.2 bouyer #define TX39_MEMCONFIG4_ENBANK0HDRAM 0x40000000 407 1.2.6.2 bouyer #define TX39_MEMCONFIG4_ENARB 0x20000000 408 1.2.6.2 bouyer #define TX39_MEMCONFIG4_DISSNOOP 0x10000000 409 1.2.6.2 bouyer #define TX39_MEMCONFIG4_CLRWRBUSERRINT 0x08000000 410 1.2.6.2 bouyer #define TX39_MEMCONFIG4_ENBANK1OPT 0x04000000 411 1.2.6.2 bouyer #define TX39_MEMCONFIG4_ENBANK0OPT 0x02000000 412 1.2.6.2 bouyer #define TX39_MEMCONFIG4_ENWATCH 0x01000000 413 1.2.6.2 bouyer 414 1.2.6.2 bouyer /* 415 1.2.6.2 bouyer * WatchDogTimerRate = (WATCHTIME[3:0] + 1) * 64 / 36.864MHz 416 1.2.6.2 bouyer */ 417 1.2.6.2 bouyer #define TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT 20 418 1.2.6.2 bouyer #define TX39_MEMCONFIG4_WATCHTIMEVAL_MASK 0xf 419 1.2.6.2 bouyer #define TX39_MEMCONFIG4_WATCHTIMEVAL(cr) \ 420 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT) & \ 421 1.2.6.2 bouyer TX39_MEMCONFIG4_WATCHTIMEVAL_MASK) 422 1.2.6.2 bouyer #define TX39_MEMCONFIG4_WATCHTIMEVAL_SET(cr, val) \ 423 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT) & \ 424 1.2.6.2 bouyer (TX39_MEMCONFIG4_WATCHTIMEVAL_MASK << TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT))) 425 1.2.6.2 bouyer 426 1.2.6.2 bouyer 427 1.2.6.2 bouyer #define TX39_MEMCONFIG4_MEMPOWERDOWN 0x00010000 428 1.2.6.2 bouyer #define TX39_MEMCONFIG4_ENRFSH1 0x00008000 429 1.2.6.2 bouyer #define TX39_MEMCONFIG4_ENRFSH0 0x00004000 430 1.2.6.2 bouyer 431 1.2.6.2 bouyer #define TX39_MEMCONFIG4_RFSHVAL1_SHIFT 8 432 1.2.6.2 bouyer #define TX39_MEMCONFIG4_RFSHVAL1_MASK 0x3f 433 1.2.6.2 bouyer #define TX39_MEMCONFIG4_RFSHVAL1(cr) \ 434 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG4_RFSHVAL1_SHIFT) & \ 435 1.2.6.2 bouyer TX39_MEMCONFIG4_RFSHVAL1_MASK) 436 1.2.6.2 bouyer #define TX39_MEMCONFIG4_RFSHVAL1_SET(cr, val) \ 437 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG4_RFSHVAL1_SHIFT) & \ 438 1.2.6.2 bouyer (TX39_MEMCONFIG4_RFSHVAL1_MASK << TX39_MEMCONFIG4_RFSHVAL1_SHIFT))) 439 1.2.6.2 bouyer 440 1.2.6.2 bouyer #define TX39_MEMCONFIG4_RFSHVAL0_SHIFT 0 441 1.2.6.2 bouyer #define TX39_MEMCONFIG4_RFSHVAL0_MASK 0x3f 442 1.2.6.2 bouyer #define TX39_MEMCONFIG4_RFSHVAL0(cr) \ 443 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG4_RFSHVAL0_SHIFT) & \ 444 1.2.6.2 bouyer TX39_MEMCONFIG4_RFSHVAL0_MASK) 445 1.2.6.2 bouyer #define TX39_MEMCONFIG4_RFSHVAL0_SET(cr, val) \ 446 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG4_RFSHVAL0_SHIFT) & \ 447 1.2.6.2 bouyer (TX39_MEMCONFIG4_RFSHVAL0_MASK << TX39_MEMCONFIG4_RFSHVAL0_SHIFT))) 448 1.2.6.2 bouyer 449 1.2.6.2 bouyer /* 450 1.2.6.2 bouyer * Memory Configuration 5 Register 451 1.2.6.2 bouyer */ 452 1.2.6.2 bouyer /* Address remap region 2 */ 453 1.2.6.2 bouyer #define TX39_MEMCONFIG5_STARTVAL2_SHIFT 9 454 1.2.6.2 bouyer #define TX39_MEMCONFIG5_STARTVAL2_MASK 0x007fffff 455 1.2.6.2 bouyer #define TX39_MEMCONFIG5_STARTVAL2(cr) \ 456 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG5_STARTVAL2_SHIFT) & \ 457 1.2.6.2 bouyer TX39_MEMCONFIG5_STARTVAL2_MASK) 458 1.2.6.2 bouyer #define TX39_MEMCONFIG5_STARTVAL2_SET(cr, val) \ 459 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG5_STARTVAL2_SHIFT) & \ 460 1.2.6.2 bouyer (TX39_MEMCONFIG5_STARTVAL2_MASK << TX39_MEMCONFIG5_STARTVAL2_SHIFT))) 461 1.2.6.2 bouyer 462 1.2.6.2 bouyer #define TX39_MEMCONFIG5_MASK2_SHIFT 0 463 1.2.6.2 bouyer #define TX39_MEMCONFIG5_MASK2_MASK 0xf 464 1.2.6.2 bouyer #define TX39_MEMCONFIG5_MASK2(cr) \ 465 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG5_MASK2_SHIFT) & \ 466 1.2.6.2 bouyer TX39_MEMCONFIG5_MASK2_MASK) 467 1.2.6.2 bouyer #define TX39_MEMCONFIG5_MASK2_SET(cr, val) \ 468 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG5_MASK2_SHIFT) & \ 469 1.2.6.2 bouyer (TX39_MEMCONFIG5_MASK2_MASK << TX39_MEMCONFIG5_MASK2_SHIFT))) 470 1.2.6.2 bouyer 471 1.2.6.2 bouyer /* 472 1.2.6.2 bouyer * Memory Configuration 6 Register 473 1.2.6.2 bouyer */ 474 1.2.6.2 bouyer /* Address remap region 1 */ 475 1.2.6.2 bouyer #define TX39_MEMCONFIG6_STARTVAL1_SHIFT 9 476 1.2.6.2 bouyer #define TX39_MEMCONFIG6_STARTVAL1_MASK 0x007fffff 477 1.2.6.2 bouyer #define TX39_MEMCONFIG6_STARTVAL1(cr) \ 478 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG6_STARTVAL1_SHIFT) & \ 479 1.2.6.2 bouyer TX39_MEMCONFIG6_STARTVAL1_MASK) 480 1.2.6.2 bouyer #define TX39_MEMCONFIG6_STARTVAL1_SET(cr, val) \ 481 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG6_STARTVAL1_SHIFT) & \ 482 1.2.6.2 bouyer (TX39_MEMCONFIG6_STARTVAL1_MASK << TX39_MEMCONFIG6_STARTVAL1_SHIFT))) 483 1.2.6.2 bouyer 484 1.2.6.2 bouyer #define TX39_MEMCONFIG6_MASK1_SHIFT 0 485 1.2.6.2 bouyer #define TX39_MEMCONFIG6_MASK1_MASK 0xf 486 1.2.6.2 bouyer #define TX39_MEMCONFIG6_MASK1(cr) \ 487 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG6_MASK1_SHIFT) & \ 488 1.2.6.2 bouyer TX39_MEMCONFIG6_MASK1_MASK) 489 1.2.6.2 bouyer #define TX39_MEMCONFIG6_MASK1_SET(cr, val) \ 490 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG6_MASK1_SHIFT) & \ 491 1.2.6.2 bouyer (TX39_MEMCONFIG6_MASK1_MASK << TX39_MEMCONFIG6_MASK1_SHIFT))) 492 1.2.6.2 bouyer 493 1.2.6.2 bouyer /* 494 1.2.6.2 bouyer * Memory Configuration 7 Register 495 1.2.6.2 bouyer */ 496 1.2.6.2 bouyer /* Address remap region 2 */ 497 1.2.6.2 bouyer #define TX39_MEMCONFIG7_RMAPADD2_SHIFT 9 498 1.2.6.2 bouyer #define TX39_MEMCONFIG7_RMAPADD2_MASK 0x007fffff 499 1.2.6.2 bouyer #define TX39_MEMCONFIG7_RMAPADD2(cr) \ 500 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG7_RMAPADD2_SHIFT) & \ 501 1.2.6.2 bouyer TX39_MEMCONFIG7_RMAPADD2_MASK) 502 1.2.6.2 bouyer #define TX39_MEMCONFIG7_RMAPADD2_SET(cr, val) \ 503 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG7_RMAPADD2_SHIFT) & \ 504 1.2.6.2 bouyer (TX39_MEMCONFIG7_RMAPADD2_MASK << TX39_MEMCONFIG7_RMAPADD2_SHIFT))) 505 1.2.6.2 bouyer 506 1.2.6.2 bouyer /* 507 1.2.6.2 bouyer * Memory Configuration 8 Register 508 1.2.6.2 bouyer */ 509 1.2.6.2 bouyer /* Address remap region 1 */ 510 1.2.6.2 bouyer #define TX39_MEMCONFIG8_RMAPADD1_SHIFT 9 511 1.2.6.2 bouyer #define TX39_MEMCONFIG8_RMAPADD1_MASK 0x007fffff 512 1.2.6.2 bouyer #define TX39_MEMCONFIG8_RMAPADD1(cr) \ 513 1.2.6.2 bouyer (((cr) >> TX39_MEMCONFIG8_RMAPADD1_SHIFT) & \ 514 1.2.6.2 bouyer TX39_MEMCONFIG8_RMAPADD1_MASK) 515 1.2.6.2 bouyer #define TX39_MEMCONFIG8_RMAPADD1_SET(cr, val) \ 516 1.2.6.2 bouyer ((cr) | (((val) << TX39_MEMCONFIG8_RMAPADD1_SHIFT) & \ 517 1.2.6.2 bouyer (TX39_MEMCONFIG8_RMAPADD1_MASK << TX39_MEMCONFIG8_RMAPADD1_SHIFT))) 518
Indexes created Wed Nov 05 19:10:08 GMT 2025