tx39biureg.h revision 1.1.2.1
1 /* $NetBSD: tx39biureg.h,v 1.1.2.1 1999/12/27 18:32:11 wrstuden Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 /* 29 * Toshiba TX3912/3922 BIU module (Bus Interface Unit) 30 */ 31 32 /* 33 * System Address Map 34 */ 35 #define TX39_SYSADDR_DRAMBANK0CS1 0x00000000 36 #define TX39_SYSADDR_DRAMBANK1CS1 0x02000000 37 #define TX39_SYSADDR_DRAMBANK0 0x04000000 38 #define TX39_SYSADDR_DRAMBANK1 0x06000000 39 #define TX39_SYSADDR_DRAMBANK_LEN 0x02000000 40 41 #define TX39_SYSADDR_CARD1 0x08000000 42 #define TX39_SYSADDR_CARD2 0x0C000000 43 /* 64MByte */ 44 #define TX39_SYSADDR_CARD_SIZE 0x04000000 45 46 #define TX39_SYSADDR_CS1 0x10000000 47 #define TX39_SYSADDR_CS2 0x10400000 48 #define TX39_SYSADDR_CS3 0x10800000 49 /* 4MByte */ 50 #define TX39_SYSADDR_CS_SIZE 0x00400000 51 52 #define TX39_SYSADDR_CONFIG_REG 0x10c00000 53 #define TX39_SYSADDR_CONFIG_REG_LEN 0x00200000 54 55 #define TX39_SYSADDR_SDRAMBANK0MODE_REG 0x10e00000 56 #define TX39_SYSADDR_SDRAMBANK1MODE_REG 0x10f00000 57 #define TX39_SYSADDR_CS0 0x11000000 58 #define TX39_SYSADDR_KUSEG_DRAMBANK0CS1 0x40000000 59 #define TX39_SYSADDR_KUSEG_DRAMBANK1CS1 0x42000000 60 #define TX39_SYSADDR_KUSEG_DRAMBANK0 0x44000000 61 #define TX39_SYSADDR_KUSEG_DRAMBANK1 0x46000000 62 #define TX39_SYSADDR_KUSEG_CS0 0x50000000 63 #define TX39_SYSADDR_KUSEG_CS1 0x58000000 64 #define TX39_SYSADDR_KUSEG_CS2 0x5c000000 65 #define TX39_SYSADDR_KUSEG_CS3 0x60000000 66 #define TX39_SYSADDR_CARD1MEM 0x64000000 67 #define TX39_SYSADDR_CARD2MEM 0x68000000 68 #define TX39_SYSADDR_MCS0 0x6c000000 69 #define TX39_SYSADDR_MCS1 0x70000000 70 #ifdef TX391X 71 #define TX39_SYSADDR_MCS2 0x74000000 72 #define TX39_SYSADDR_MCS3 0x7c000000 73 #endif /* TX391X */ 74 /* 64MByte */ 75 #define TX39_SYSADDR_MCS_SIZE 0x04000000 76 77 /* 78 * BIU module registers. 79 */ 80 #define TX39_MEMCONFIG0_REG 0x00 81 #define TX39_MEMCONFIG1_REG 0x04 82 #define TX39_MEMCONFIG2_REG 0x08 83 #define TX39_MEMCONFIG3_REG 0x0C 84 #define TX39_MEMCONFIG4_REG 0x10 85 #define TX39_MEMCONFIG5_REG 0x14 86 #define TX39_MEMCONFIG6_REG 0x18 87 #define TX39_MEMCONFIG7_REG 0x1C 88 #define TX39_MEMCONFIG8_REG 0x20 89 90 /* 91 * Memory Configuration 0 Register 92 */ 93 /* R/W */ 94 #define TX39_MEMCONFIG0_ENDCLKOUTTRI 0x40000000 95 #define TX39_MEMCONFIG0_DISDQMINIT 0x20000000 96 #define TX39_MEMCONFIG0_ENSDRAMPD 0x10000000 97 #define TX39_MEMCONFIG0_SHOWDINO 0x08000000 98 #define TX39_MEMCONFIG0_ENRMAP2 0x04000000 99 #define TX39_MEMCONFIG0_ENRMAP1 0x02000000 100 #define TX39_MEMCONFIG0_ENWRINPAGE 0x01000000 101 #define TX39_MEMCONFIG0_ENCS3USER 0x00800000 102 #define TX39_MEMCONFIG0_ENCS2USER 0x00400000 103 #define TX39_MEMCONFIG0_ENCS1USER 0x00200000 104 #define TX39_MEMCONFIG0_ENCS1DRAM 0x00100000 105 106 #define TX39_MEMCONFIG0_BANK1CONF_SHIFT 18 107 #define TX39_MEMCONFIG0_BANK1CONF_MASK 0x3 108 #define TX39_MEMCONFIG0_BANK1CONF(cr) \ 109 (((cr) >> TX39_MEMCONFIG0_BANK1CONF_SHIFT) & \ 110 TX39_MEMCONFIG0_BANK1CONF_MASK) 111 #define TX39_MEMCONFIG0_BANK1CONF_SET(cr, val) \ 112 ((cr) | (((val) << TX39_MEMCONFIG0_BANK1CONF_SHIFT) & \ 113 (TX39_MEMCONFIG0_BANK1CONF_MASK << TX39_MEMCONFIG0_BANK1CONF_SHIFT))) 114 #define TX39_MEMCONFIG0_BANK0CONF_SHIFT 16 115 #define TX39_MEMCONFIG0_BANK0CONF_MASK 0x3 116 #define TX39_MEMCONFIG0_BANK0CONF(cr) \ 117 (((cr) >> TX39_MEMCONFIG0_BANK0CONF_SHIFT) & \ 118 TX39_MEMCONFIG0_BANK0CONF_MASK) 119 #define TX39_MEMCONFIG0_BANK0CONF_SET(cr, val) \ 120 ((cr) | (((val) << TX39_MEMCONFIG0_BANK0CONF_SHIFT) & \ 121 (TX39_MEMCONFIG0_BANK0CONF_MASK << TX39_MEMCONFIG0_BANK0CONF_SHIFT))) 122 #define TX39_MEMCONFIG0_BANKCONF_16BITSDRAM 0x3 123 #define TX39_MEMCONFIG0_BANKCONF_8BITSDRAM 0x2 124 #define TX39_MEMCONFIG0_BANKCONF_32BITSDHDRAM 0x1 125 #define TX39_MEMCONFIG0_BANKCONF_16BITSDHDRAM 0x0 126 127 #define TX39_MEMCONFIG0_ROWSEL1_SHIFT 14 128 #define TX39_MEMCONFIG0_ROWSEL1_MASK 0x3 129 #define TX39_MEMCONFIG0_ROWSEL1(cr) \ 130 (((cr) >> TX39_MEMCONFIG0_ROWSEL1_SHIFT) & \ 131 TX39_MEMCONFIG0_ROWSEL1_MASK) 132 #define TX39_MEMCONFIG0_ROWSEL1_SET(cr, val) \ 133 ((cr) | (((val) << TX39_MEMCONFIG0_ROWSEL1_SHIFT) & \ 134 (TX39_MEMCONFIG0_ROWSEL1_MASK << TX39_MEMCONFIG0_ROWSEL1_SHIFT))) 135 #define TX39_MEMCONFIG0_ROWSEL0_SHIFT 12 136 #define TX39_MEMCONFIG0_ROWSEL0_MASK 0x3 137 #define TX39_MEMCONFIG0_ROWSEL0(cr) \ 138 (((cr) >> TX39_MEMCONFIG0_ROWSEL0_SHIFT) & \ 139 TX39_MEMCONFIG0_ROWSEL0_MASK) 140 #define TX39_MEMCONFIG0_ROWSEL0_SET(cr, val) \ 141 ((cr) | (((val) << TX39_MEMCONFIG0_ROWSEL0_SHIFT) & \ 142 (TX39_MEMCONFIG0_ROWSEL0_MASK << TX39_MEMCONFIG0_ROWSEL0_SHIFT))) 143 144 #define TX39_MEMCONFIG0_COLSEL1_SHIFT 8 145 #define TX39_MEMCONFIG0_COLSEL1_MASK 0xf 146 #define TX39_MEMCONFIG0_COLSEL1(cr) \ 147 (((cr) >> TX39_MEMCONFIG0_COLSEL1_SHIFT) & \ 148 TX39_MEMCONFIG0_COLSEL1_MASK) 149 #define TX39_MEMCONFIG0_COLSEL1_SET(cr, val) \ 150 ((cr) | (((val) << TX39_MEMCONFIG0_COLSEL1_SHIFT) & \ 151 (TX39_MEMCONFIG0_COLSEL1_MASK << TX39_MEMCONFIG0_COLSEL1_SHIFT))) 152 #define TX39_MEMCONFIG0_COLSEL0_SHIFT 4 153 #define TX39_MEMCONFIG0_COLSEL0_MASK 0xf 154 #define TX39_MEMCONFIG0_COLSEL0(cr) \ 155 (((cr) >> TX39_MEMCONFIG0_COLSEL0_SHIFT) & \ 156 TX39_MEMCONFIG0_COLSEL0_MASK) 157 #define TX39_MEMCONFIG0_COLSEL0_SET(cr, val) \ 158 ((cr) | (((val) << TX39_MEMCONFIG0_COLSEL0_SHIFT) & \ 159 (TX39_MEMCONFIG0_COLSEL0_MASK << TX39_MEMCONFIG0_COLSEL0_SHIFT))) 160 161 #define TX39_MEMCONFIG0_CS3SIZE 0x00000008 162 #define TX39_MEMCONFIG0_CS2SIZE 0x00000004 163 #define TX39_MEMCONFIG0_CS1SIZE 0x00000002 164 #define TX39_MEMCONFIG0_CS0SIZE 0x00000001 165 166 /* 167 * Memory Configuration 1 Register 168 */ 169 #ifdef TX391X 170 #define TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT 28 171 #define TX39_MEMCONFIG1_MCS3ACCVAL1_MASK 0xf 172 #define TX39_MEMCONFIG1_MCS3ACCVAL1(cr) \ 173 (((cr) >> TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT) & \ 174 TX39_MEMCONFIG1_MCS3ACCVAL1_MASK) 175 #define TX39_MEMCONFIG1_MCS3ACCVAL1_SET(cr, val) \ 176 ((cr) | (((val) << TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT) & \ 177 (TX39_MEMCONFIG1_MCS3ACCVAL1_MASK << TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT))) 178 179 #define TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT 24 180 #define TX39_MEMCONFIG1_MCS3ACCVAL2_MASK 0xf 181 #define TX39_MEMCONFIG1_MCS3ACCVAL2(cr) \ 182 (((cr) >> TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT) & \ 183 TX39_MEMCONFIG1_MCS3ACCVAL2_MASK) 184 #define TX39_MEMCONFIG1_MCS3ACCVAL2_SET(cr, val) \ 185 ((cr) | (((val) << TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT) & \ 186 (TX39_MEMCONFIG1_MCS3ACCVAL2_MASK << TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT))) 187 188 #define TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT 20 189 #define TX39_MEMCONFIG1_MCS2ACCVAL1_MASK 0xf 190 #define TX39_MEMCONFIG1_MCS2ACCVAL1(cr) \ 191 (((cr) >> TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT) & \ 192 TX39_MEMCONFIG1_MCS2ACCVAL1_MASK) 193 #define TX39_MEMCONFIG1_MCS2ACCVAL1_SET(cr, val) \ 194 ((cr) | (((val) << TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT) & \ 195 (TX39_MEMCONFIG1_MCS2ACCVAL1_MASK << TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT))) 196 197 #define TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT 16 198 #define TX39_MEMCONFIG1_MCS2ACCVAL2_MASK 0xf 199 #define TX39_MEMCONFIG1_MCS2ACCVAL2(cr) \ 200 (((cr) >> TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT) & \ 201 TX39_MEMCONFIG1_MCS2ACCVAL2_MASK) 202 #define TX39_MEMCONFIG1_MCS2ACCVAL2_SET(cr, val) \ 203 ((cr) | (((val) << TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT) & \ 204 (TX39_MEMCONFIG1_MCS2ACCVAL2_MASK << TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT))) 205 #endif /* TX391X */ 206 #ifdef TX392X 207 #define TX39_MEMCONFIG1_C48MPLLON 0x40000000 208 #define TX39_MEMCONFIG1_ENMCS1BE 0x20000000 209 #define TX39_MEMCONFIG1_ENMCS0BE 0x10000000 210 #define TX39_MEMCONFIG1_ENMCS1ACC 0x08000000 211 #define TX39_MEMCONFIG1_ENMCS0ACC 0x04000000 212 #define TX39_MEMCONFIG1_BCLKDIV_SHIFT 23 213 #define TX39_MEMCONFIG1_BCLKDIV_MASK 0x7 214 #define TX39_MEMCONFIG1_BCLKDIV(cr) \ 215 (((cr) >> TX39_MEMCONFIG1_BCLKDIV_SHIFT) & \ 216 TX39_MEMCONFIG1_BCLKDIV_MASK) 217 #define TX39_MEMCONFIG1_BCLKDIV_SET(cr, val) \ 218 ((cr) | (((val) << TX39_MEMCONFIG1_BCLKDIV_SHIFT) & \ 219 (TX39_MEMCONFIG1_BCLKDIV_MASK << TX39_MEMCONFIG1_BCLKDIV_SHIFT))) 220 #define TX39_MEMCONFIG1_ENBCLK 0x00400000 221 #define TX39_MEMCONFIG1_ENMCS1PAGE 0x00200000 222 #define TX39_MEMCONFIG1_ENMCS0PAGE 0x00100000 223 #define TX39_MEMCONFIG1_ENMCS1WAIT 0x00080000 224 #define TX39_MEMCONFIG1_ENMCS0WAIT 0x00040000 225 #define TX39_MEMCONFIG1_MCS1_32 0x00020000 226 #define TX39_MEMCONFIG1_MCS0_32 0x00010000 227 #endif /* TX392X */ 228 229 #define TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT 12 230 #define TX39_MEMCONFIG1_MCS1ACCVAL1_MASK 0xf 231 #define TX39_MEMCONFIG1_MCS1ACCVAL1(cr) \ 232 (((cr) >> TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT) & \ 233 TX39_MEMCONFIG1_MCS1ACCVAL1_MASK) 234 #define TX39_MEMCONFIG1_MCS1ACCVAL1_SET(cr, val) \ 235 ((cr) | (((val) << TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT) & \ 236 (TX39_MEMCONFIG1_MCS1ACCVAL1_MASK << TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT))) 237 238 #define TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT 8 239 #define TX39_MEMCONFIG1_MCS1ACCVAL2_MASK 0xf 240 #define TX39_MEMCONFIG1_MCS1ACCVAL2(cr) \ 241 (((cr) >> TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT) & \ 242 TX39_MEMCONFIG1_MCS1ACCVAL2_MASK) 243 #define TX39_MEMCONFIG1_MCS1ACCVAL2_SET(cr, val) \ 244 ((cr) | (((val) << TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT) & \ 245 (TX39_MEMCONFIG1_MCS1ACCVAL2_MASK << TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT))) 246 247 #define TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT 4 248 #define TX39_MEMCONFIG1_MCS0ACCVAL1_MASK 0xf 249 #define TX39_MEMCONFIG1_MCS0ACCVAL1(cr) \ 250 (((cr) >> TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT) & \ 251 TX39_MEMCONFIG1_MCS0ACCVAL1_MASK) 252 #define TX39_MEMCONFIG1_MCS0ACCVAL1_SET(cr, val) \ 253 ((cr) | (((val) << TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT) & \ 254 (TX39_MEMCONFIG1_MCS0ACCVAL1_MASK << TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT))) 255 256 #define TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT 0 257 #define TX39_MEMCONFIG1_MCS0ACCVAL2_MASK 0xf 258 #define TX39_MEMCONFIG1_MCS0ACCVAL2(cr) \ 259 (((cr) >> TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT) & \ 260 TX39_MEMCONFIG1_MCS0ACCVAL2_MASK) 261 #define TX39_MEMCONFIG1_MCS0ACCVAL2_SET(cr, val) \ 262 ((cr) | (((val) << TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT) & \ 263 (TX39_MEMCONFIG1_MCS0ACCVAL2_MASK << TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT))) 264 265 /* 266 * Memory Configuration 2 Register 267 */ 268 /* Define access timing. not required yet */ 269 #define TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT 28 270 #define TX39_MEMCONFIG2_CS3ACCVAL1_MASK 0xf 271 #define TX39_MEMCONFIG2_CS3ACCVAL1(cr) \ 272 (((cr) >> TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT) & \ 273 TX39_MEMCONFIG2_CS3ACCVAL1_MASK) 274 #define TX39_MEMCONFIG2_CS3ACCVAL1_SET(cr, val) \ 275 ((cr) | (((val) << TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT) & \ 276 (TX39_MEMCONFIG2_CS3ACCVAL1_MASK << TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT))) 277 278 #define TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT 24 279 #define TX39_MEMCONFIG2_CS3ACCVAL2_MASK 0xf 280 #define TX39_MEMCONFIG2_CS3ACCVAL2(cr) \ 281 (((cr) >> TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT) & \ 282 TX39_MEMCONFIG2_CS3ACCVAL2_MASK) 283 #define TX39_MEMCONFIG2_CS3ACCVAL2_SET(cr, val) \ 284 ((cr) | (((val) << TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT) & \ 285 (TX39_MEMCONFIG2_CS3ACCVAL2_MASK << TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT))) 286 287 #define TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT 20 288 #define TX39_MEMCONFIG2_CS2ACCVAL1_MASK 0xf 289 #define TX39_MEMCONFIG2_CS2ACCVAL1(cr) \ 290 (((cr) >> TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT) & \ 291 TX39_MEMCONFIG2_CS2ACCVAL1_MASK) 292 #define TX39_MEMCONFIG2_CS2ACCVAL1_SET(cr, val) \ 293 ((cr) | (((val) << TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT) & \ 294 (TX39_MEMCONFIG2_CS2ACCVAL1_MASK << TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT))) 295 296 #define TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT 16 297 #define TX39_MEMCONFIG2_CS2ACCVAL2_MASK 0xf 298 #define TX39_MEMCONFIG2_CS2ACCVAL2(cr) \ 299 (((cr) >> TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT) & \ 300 TX39_MEMCONFIG2_CS2ACCVAL2_MASK) 301 #define TX39_MEMCONFIG2_CS2ACCVAL2_SET(cr, val) \ 302 ((cr) | (((val) << TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT) & \ 303 (TX39_MEMCONFIG2_CS2ACCVAL2_MASK << TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT))) 304 305 #define TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT 12 306 #define TX39_MEMCONFIG2_CS1ACCVAL1_MASK 0xf 307 #define TX39_MEMCONFIG2_CS1ACCVAL1(cr) \ 308 (((cr) >> TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT) & \ 309 TX39_MEMCONFIG2_CS1ACCVAL1_MASK) 310 #define TX39_MEMCONFIG2_CS1ACCVAL1_SET(cr, val) \ 311 ((cr) | (((val) << TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT) & \ 312 (TX39_MEMCONFIG2_CS1ACCVAL1_MASK << TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT))) 313 314 #define TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT 8 315 #define TX39_MEMCONFIG2_CS1ACCVAL2_MASK 0xf 316 #define TX39_MEMCONFIG2_CS1ACCVAL2(cr) \ 317 (((cr) >> TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT) & \ 318 TX39_MEMCONFIG2_CS1ACCVAL2_MASK) 319 #define TX39_MEMCONFIG2_CS1ACCVAL2_SET(cr, val) \ 320 ((cr) | (((val) << TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT) & \ 321 (TX39_MEMCONFIG2_CS1ACCVAL2_MASK << TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT))) 322 323 #define TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT 4 324 #define TX39_MEMCONFIG2_CS0ACCVAL1_MASK 0xf 325 #define TX39_MEMCONFIG2_CS0ACCVAL1(cr) \ 326 (((cr) >> TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT) & \ 327 TX39_MEMCONFIG2_CS0ACCVAL1_MASK) 328 #define TX39_MEMCONFIG2_CS0ACCVAL1_SET(cr, val) \ 329 ((cr) | (((val) << TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT) & \ 330 (TX39_MEMCONFIG2_CS0ACCVAL1_MASK << TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT))) 331 332 #define TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT 0 333 #define TX39_MEMCONFIG2_CS0ACCVAL2_MASK 0xf 334 #define TX39_MEMCONFIG2_CS0ACCVAL2(cr) \ 335 (((cr) >> TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT) & \ 336 TX39_MEMCONFIG2_CS0ACCVAL2_MASK) 337 #define TX39_MEMCONFIG2_CS0ACCVAL2_SET(cr, val) \ 338 ((cr) | (((val) << TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT) & \ 339 (TX39_MEMCONFIG2_CS0ACCVAL2_MASK << TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT))) 340 341 /* 342 * Memory Configuration 3 Register 343 */ 344 /* Define access timing, enable read page mode, PC-Card. */ 345 #define TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT 28 346 #define TX39_MEMCONFIG3_CARD2ACCVAL_MASK 0xf 347 #define TX39_MEMCONFIG3_CARD2ACCVAL(cr) \ 348 (((cr) >> TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT) & \ 349 TX39_MEMCONFIG3_CARD2ACCVAL_MASK) 350 #define TX39_MEMCONFIG3_CARD2ACCVAL_SET(cr, val) \ 351 ((cr) | (((val) << TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT) & \ 352 (TX39_MEMCONFIG3_CARD2ACCVAL_MASK << TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT))) 353 354 #define TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT 24 355 #define TX39_MEMCONFIG3_CARD1ACCVAL_MASK 0xf 356 #define TX39_MEMCONFIG3_CARD1ACCVAL(cr) \ 357 (((cr) >> TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT) & \ 358 TX39_MEMCONFIG3_CARD1ACCVAL_MASK) 359 #define TX39_MEMCONFIG3_CARD1ACCVAL_SET(cr, val) \ 360 ((cr) | (((val) << TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT) & \ 361 (TX39_MEMCONFIG3_CARD1ACCVAL_MASK << TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT))) 362 363 #define TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT 20 364 #define TX39_MEMCONFIG3_CARD2IOACCVAL_MASK 0xf 365 #define TX39_MEMCONFIG3_CARD2IOACCVAL(cr) \ 366 (((cr) >> TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT) & \ 367 TX39_MEMCONFIG3_CARD2IOACCVAL_MASK) 368 #define TX39_MEMCONFIG3_CARD2IOACCVAL_SET(cr, val) \ 369 ((cr) | (((val) << TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT) & \ 370 (TX39_MEMCONFIG3_CARD2IOACCVAL_MASK << TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT))) 371 372 #define TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT 16 373 #define TX39_MEMCONFIG3_CARD1IOACCVAL_MASK 0xf 374 #define TX39_MEMCONFIG3_CARD1IOACCVAL(cr) \ 375 (((cr) >> TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT) & \ 376 TX39_MEMCONFIG3_CARD1IOACCVAL_MASK) 377 #define TX39_MEMCONFIG3_CARD1IOACCVAL_SET(cr, val) \ 378 ((cr) | (((val) << TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT) & \ 379 (TX39_MEMCONFIG3_CARD1IOACCVAL_MASK << TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT))) 380 #ifdef TX391X 381 #define TX39_MEMCONFIG3_ENMCS3PAGE 0x00008000 382 #define TX39_MEMCONFIG3_ENMCS2PAGE 0x00004000 383 #define TX39_MEMCONFIG3_ENMCS1PAGE 0x00002000 384 #define TX39_MEMCONFIG3_ENMCS0PAGE 0x00001000 385 #endif /* TX391X */ 386 #define TX39_MEMCONFIG3_ENCS3PAGE 0x00000800 387 #define TX39_MEMCONFIG3_ENCS2PAGE 0x00000400 388 #define TX39_MEMCONFIG3_ENCS1PAGE 0x00000200 389 #define TX39_MEMCONFIG3_ENCS0PAGE 0x00000100 390 #define TX39_MEMCONFIG3_CARD2WAITEN 0x00000080 391 #define TX39_MEMCONFIG3_CARD1WAITEN 0x00000040 392 #define TX39_MEMCONFIG3_CARD2IOEN 0x00000020 393 #define TX39_MEMCONFIG3_CARD1IOEN 0x00000010 394 #ifdef TX391X 395 #define TX39_MEMCONFIG3_PORT8SEL 0x00000008 396 #endif /* TX391X */ 397 #ifdef TX392X 398 #define TX39_MEMCONFIG3_CARD2_8SEL 0x00000008 399 #define TX39_MEMCONFIG3_CARD1_8SEL 0x00000004 400 #endif /* TX392X */ 401 /* 402 * Memory Configuration 4 Register 403 */ 404 /* DMA */ 405 #define TX39_MEMCONFIG4_ENBANK1HDRAM 0x80000000 406 #define TX39_MEMCONFIG4_ENBANK0HDRAM 0x40000000 407 #define TX39_MEMCONFIG4_ENARB 0x20000000 408 #define TX39_MEMCONFIG4_DISSNOOP 0x10000000 409 #define TX39_MEMCONFIG4_CLRWRBUSERRINT 0x08000000 410 #define TX39_MEMCONFIG4_ENBANK1OPT 0x04000000 411 #define TX39_MEMCONFIG4_ENBANK0OPT 0x02000000 412 #define TX39_MEMCONFIG4_ENWATCH 0x01000000 413 414 /* 415 * WatchDogTimerRate = (WATCHTIME[3:0] + 1) * 64 / 36.864MHz 416 */ 417 #define TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT 20 418 #define TX39_MEMCONFIG4_WATCHTIMEVAL_MASK 0xf 419 #define TX39_MEMCONFIG4_WATCHTIMEVAL(cr) \ 420 (((cr) >> TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT) & \ 421 TX39_MEMCONFIG4_WATCHTIMEVAL_MASK) 422 #define TX39_MEMCONFIG4_WATCHTIMEVAL_SET(cr, val) \ 423 ((cr) | (((val) << TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT) & \ 424 (TX39_MEMCONFIG4_WATCHTIMEVAL_MASK << TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT))) 425 426 427 #define TX39_MEMCONFIG4_MEMPOWERDOWN 0x00010000 428 #define TX39_MEMCONFIG4_ENRFSH1 0x00008000 429 #define TX39_MEMCONFIG4_ENRFSH0 0x00004000 430 431 #define TX39_MEMCONFIG4_RFSHVAL1_SHIFT 8 432 #define TX39_MEMCONFIG4_RFSHVAL1_MASK 0x3f 433 #define TX39_MEMCONFIG4_RFSHVAL1(cr) \ 434 (((cr) >> TX39_MEMCONFIG4_RFSHVAL1_SHIFT) & \ 435 TX39_MEMCONFIG4_RFSHVAL1_MASK) 436 #define TX39_MEMCONFIG4_RFSHVAL1_SET(cr, val) \ 437 ((cr) | (((val) << TX39_MEMCONFIG4_RFSHVAL1_SHIFT) & \ 438 (TX39_MEMCONFIG4_RFSHVAL1_MASK << TX39_MEMCONFIG4_RFSHVAL1_SHIFT))) 439 440 #define TX39_MEMCONFIG4_RFSHVAL0_SHIFT 0 441 #define TX39_MEMCONFIG4_RFSHVAL0_MASK 0x3f 442 #define TX39_MEMCONFIG4_RFSHVAL0(cr) \ 443 (((cr) >> TX39_MEMCONFIG4_RFSHVAL0_SHIFT) & \ 444 TX39_MEMCONFIG4_RFSHVAL0_MASK) 445 #define TX39_MEMCONFIG4_RFSHVAL0_SET(cr, val) \ 446 ((cr) | (((val) << TX39_MEMCONFIG4_RFSHVAL0_SHIFT) & \ 447 (TX39_MEMCONFIG4_RFSHVAL0_MASK << TX39_MEMCONFIG4_RFSHVAL0_SHIFT))) 448 449 /* 450 * Memory Configuration 5 Register 451 */ 452 /* Address remap region 2 */ 453 #define TX39_MEMCONFIG5_STARTVAL2_SHIFT 9 454 #define TX39_MEMCONFIG5_STARTVAL2_MASK 0x007fffff 455 #define TX39_MEMCONFIG5_STARTVAL2(cr) \ 456 (((cr) >> TX39_MEMCONFIG5_STARTVAL2_SHIFT) & \ 457 TX39_MEMCONFIG5_STARTVAL2_MASK) 458 #define TX39_MEMCONFIG5_STARTVAL2_SET(cr, val) \ 459 ((cr) | (((val) << TX39_MEMCONFIG5_STARTVAL2_SHIFT) & \ 460 (TX39_MEMCONFIG5_STARTVAL2_MASK << TX39_MEMCONFIG5_STARTVAL2_SHIFT))) 461 462 #define TX39_MEMCONFIG5_MASK2_SHIFT 0 463 #define TX39_MEMCONFIG5_MASK2_MASK 0xf 464 #define TX39_MEMCONFIG5_MASK2(cr) \ 465 (((cr) >> TX39_MEMCONFIG5_MASK2_SHIFT) & \ 466 TX39_MEMCONFIG5_MASK2_MASK) 467 #define TX39_MEMCONFIG5_MASK2_SET(cr, val) \ 468 ((cr) | (((val) << TX39_MEMCONFIG5_MASK2_SHIFT) & \ 469 (TX39_MEMCONFIG5_MASK2_MASK << TX39_MEMCONFIG5_MASK2_SHIFT))) 470 471 /* 472 * Memory Configuration 6 Register 473 */ 474 /* Address remap region 1 */ 475 #define TX39_MEMCONFIG6_STARTVAL1_SHIFT 9 476 #define TX39_MEMCONFIG6_STARTVAL1_MASK 0x007fffff 477 #define TX39_MEMCONFIG6_STARTVAL1(cr) \ 478 (((cr) >> TX39_MEMCONFIG6_STARTVAL1_SHIFT) & \ 479 TX39_MEMCONFIG6_STARTVAL1_MASK) 480 #define TX39_MEMCONFIG6_STARTVAL1_SET(cr, val) \ 481 ((cr) | (((val) << TX39_MEMCONFIG6_STARTVAL1_SHIFT) & \ 482 (TX39_MEMCONFIG6_STARTVAL1_MASK << TX39_MEMCONFIG6_STARTVAL1_SHIFT))) 483 484 #define TX39_MEMCONFIG6_MASK1_SHIFT 0 485 #define TX39_MEMCONFIG6_MASK1_MASK 0xf 486 #define TX39_MEMCONFIG6_MASK1(cr) \ 487 (((cr) >> TX39_MEMCONFIG6_MASK1_SHIFT) & \ 488 TX39_MEMCONFIG6_MASK1_MASK) 489 #define TX39_MEMCONFIG6_MASK1_SET(cr, val) \ 490 ((cr) | (((val) << TX39_MEMCONFIG6_MASK1_SHIFT) & \ 491 (TX39_MEMCONFIG6_MASK1_MASK << TX39_MEMCONFIG6_MASK1_SHIFT))) 492 493 /* 494 * Memory Configuration 7 Register 495 */ 496 /* Address remap region 2 */ 497 #define TX39_MEMCONFIG7_RMAPADD2_SHIFT 9 498 #define TX39_MEMCONFIG7_RMAPADD2_MASK 0x007fffff 499 #define TX39_MEMCONFIG7_RMAPADD2(cr) \ 500 (((cr) >> TX39_MEMCONFIG7_RMAPADD2_SHIFT) & \ 501 TX39_MEMCONFIG7_RMAPADD2_MASK) 502 #define TX39_MEMCONFIG7_RMAPADD2_SET(cr, val) \ 503 ((cr) | (((val) << TX39_MEMCONFIG7_RMAPADD2_SHIFT) & \ 504 (TX39_MEMCONFIG7_RMAPADD2_MASK << TX39_MEMCONFIG7_RMAPADD2_SHIFT))) 505 506 /* 507 * Memory Configuration 8 Register 508 */ 509 /* Address remap region 1 */ 510 #define TX39_MEMCONFIG8_RMAPADD1_SHIFT 9 511 #define TX39_MEMCONFIG8_RMAPADD1_MASK 0x007fffff 512 #define TX39_MEMCONFIG8_RMAPADD1(cr) \ 513 (((cr) >> TX39_MEMCONFIG8_RMAPADD1_SHIFT) & \ 514 TX39_MEMCONFIG8_RMAPADD1_MASK) 515 #define TX39_MEMCONFIG8_RMAPADD1_SET(cr, val) \ 516 ((cr) | (((val) << TX39_MEMCONFIG8_RMAPADD1_SHIFT) & \ 517 (TX39_MEMCONFIG8_RMAPADD1_MASK << TX39_MEMCONFIG8_RMAPADD1_SHIFT))) 518
Indexes created Wed Nov 05 01:09:58 GMT 2025