tx39biureg.h revision 1.3.24.1
1 /* $NetBSD: tx39biureg.h,v 1.3.24.1 2005/11/10 13:56:27 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 /* 39 * Toshiba TX3912/3922 BIU module (Bus Interface Unit) 40 */ 41 42 /* 43 * System Address Map 44 */ 45 #define TX39_SYSADDR_DRAMBANK0CS1 0x00000000 46 #define TX39_SYSADDR_DRAMBANK1CS1 0x02000000 47 #define TX39_SYSADDR_DRAMBANK0 0x04000000 48 #define TX39_SYSADDR_DRAMBANK1 0x06000000 49 #define TX39_SYSADDR_DRAMBANK_LEN 0x02000000 50 51 #define TX39_SYSADDR_CARD1 0x08000000 52 #define TX39_SYSADDR_CARD2 0x0C000000 53 /* 64MByte */ 54 #define TX39_SYSADDR_CARD_SIZE 0x04000000 55 56 #define TX39_SYSADDR_CS1 0x10000000 57 #define TX39_SYSADDR_CS2 0x10400000 58 #define TX39_SYSADDR_CS3 0x10800000 59 /* 4MByte */ 60 #define TX39_SYSADDR_CS_SIZE 0x00400000 61 62 #define TX39_SYSADDR_CONFIG_REG 0x10c00000 63 #define TX39_SYSADDR_CONFIG_REG_LEN 0x00200000 64 65 #define TX39_SYSADDR_SDRAMBANK0MODE_REG 0x10e00000 66 #define TX39_SYSADDR_SDRAMBANK1MODE_REG 0x10f00000 67 #define TX39_SYSADDR_CS0 0x11000000 68 #define TX39_SYSADDR_KUSEG_DRAMBANK0CS1 0x40000000 69 #define TX39_SYSADDR_KUSEG_DRAMBANK1CS1 0x42000000 70 #define TX39_SYSADDR_KUSEG_DRAMBANK0 0x44000000 71 #define TX39_SYSADDR_KUSEG_DRAMBANK1 0x46000000 72 #define TX39_SYSADDR_KUSEG_CS0 0x50000000 73 #define TX39_SYSADDR_KUSEG_CS1 0x58000000 74 #define TX39_SYSADDR_KUSEG_CS2 0x5c000000 75 #define TX39_SYSADDR_KUSEG_CS3 0x60000000 76 /* 64MByte */ 77 #define TX39_SYSADDR_KUCS_SIZE 0x04000000 78 79 #define TX39_SYSADDR_CARD1MEM 0x64000000 80 #define TX39_SYSADDR_CARD2MEM 0x68000000 81 #define TX39_SYSADDR_MCS0 0x6c000000 82 #define TX39_SYSADDR_MCS1 0x70000000 83 #ifdef TX391X 84 #define TX39_SYSADDR_MCS2 0x74000000 85 #define TX39_SYSADDR_MCS3 0x78000000 86 #endif /* TX391X */ 87 /* 64MByte */ 88 #define TX39_SYSADDR_MCS_SIZE 0x04000000 89 90 /* 91 * BIU module registers. 92 */ 93 #define TX39_MEMCONFIG0_REG 0x00 94 #define TX39_MEMCONFIG1_REG 0x04 95 #define TX39_MEMCONFIG2_REG 0x08 96 #define TX39_MEMCONFIG3_REG 0x0C 97 #define TX39_MEMCONFIG4_REG 0x10 98 #define TX39_MEMCONFIG5_REG 0x14 99 #define TX39_MEMCONFIG6_REG 0x18 100 #define TX39_MEMCONFIG7_REG 0x1C 101 #define TX39_MEMCONFIG8_REG 0x20 102 103 /* 104 * Memory Configuration 0 Register 105 */ 106 /* R/W */ 107 #define TX39_MEMCONFIG0_ENDCLKOUTTRI 0x40000000 108 #define TX39_MEMCONFIG0_DISDQMINIT 0x20000000 109 #define TX39_MEMCONFIG0_ENSDRAMPD 0x10000000 110 #define TX39_MEMCONFIG0_SHOWDINO 0x08000000 111 #define TX39_MEMCONFIG0_ENRMAP2 0x04000000 112 #define TX39_MEMCONFIG0_ENRMAP1 0x02000000 113 #define TX39_MEMCONFIG0_ENWRINPAGE 0x01000000 114 #define TX39_MEMCONFIG0_ENCS3USER 0x00800000 115 #define TX39_MEMCONFIG0_ENCS2USER 0x00400000 116 #define TX39_MEMCONFIG0_ENCS1USER 0x00200000 117 #define TX39_MEMCONFIG0_ENCS1DRAM 0x00100000 118 119 #define TX39_MEMCONFIG0_BANK1CONF_SHIFT 18 120 #define TX39_MEMCONFIG0_BANK1CONF_MASK 0x3 121 #define TX39_MEMCONFIG0_BANK1CONF(cr) \ 122 (((cr) >> TX39_MEMCONFIG0_BANK1CONF_SHIFT) & \ 123 TX39_MEMCONFIG0_BANK1CONF_MASK) 124 #define TX39_MEMCONFIG0_BANK1CONF_SET(cr, val) \ 125 ((cr) | (((val) << TX39_MEMCONFIG0_BANK1CONF_SHIFT) & \ 126 (TX39_MEMCONFIG0_BANK1CONF_MASK << TX39_MEMCONFIG0_BANK1CONF_SHIFT))) 127 #define TX39_MEMCONFIG0_BANK0CONF_SHIFT 16 128 #define TX39_MEMCONFIG0_BANK0CONF_MASK 0x3 129 #define TX39_MEMCONFIG0_BANK0CONF(cr) \ 130 (((cr) >> TX39_MEMCONFIG0_BANK0CONF_SHIFT) & \ 131 TX39_MEMCONFIG0_BANK0CONF_MASK) 132 #define TX39_MEMCONFIG0_BANK0CONF_SET(cr, val) \ 133 ((cr) | (((val) << TX39_MEMCONFIG0_BANK0CONF_SHIFT) & \ 134 (TX39_MEMCONFIG0_BANK0CONF_MASK << TX39_MEMCONFIG0_BANK0CONF_SHIFT))) 135 #define TX39_MEMCONFIG0_BANKCONF_16BITSDRAM 0x3 136 #define TX39_MEMCONFIG0_BANKCONF_8BITSDRAM 0x2 137 #define TX39_MEMCONFIG0_BANKCONF_32BITSDHDRAM 0x1 138 #define TX39_MEMCONFIG0_BANKCONF_16BITSDHDRAM 0x0 139 140 #define TX39_MEMCONFIG0_ROWSEL1_SHIFT 14 141 #define TX39_MEMCONFIG0_ROWSEL1_MASK 0x3 142 #define TX39_MEMCONFIG0_ROWSEL1(cr) \ 143 (((cr) >> TX39_MEMCONFIG0_ROWSEL1_SHIFT) & \ 144 TX39_MEMCONFIG0_ROWSEL1_MASK) 145 #define TX39_MEMCONFIG0_ROWSEL1_SET(cr, val) \ 146 ((cr) | (((val) << TX39_MEMCONFIG0_ROWSEL1_SHIFT) & \ 147 (TX39_MEMCONFIG0_ROWSEL1_MASK << TX39_MEMCONFIG0_ROWSEL1_SHIFT))) 148 #define TX39_MEMCONFIG0_ROWSEL0_SHIFT 12 149 #define TX39_MEMCONFIG0_ROWSEL0_MASK 0x3 150 #define TX39_MEMCONFIG0_ROWSEL0(cr) \ 151 (((cr) >> TX39_MEMCONFIG0_ROWSEL0_SHIFT) & \ 152 TX39_MEMCONFIG0_ROWSEL0_MASK) 153 #define TX39_MEMCONFIG0_ROWSEL0_SET(cr, val) \ 154 ((cr) | (((val) << TX39_MEMCONFIG0_ROWSEL0_SHIFT) & \ 155 (TX39_MEMCONFIG0_ROWSEL0_MASK << TX39_MEMCONFIG0_ROWSEL0_SHIFT))) 156 157 #define TX39_MEMCONFIG0_COLSEL1_SHIFT 8 158 #define TX39_MEMCONFIG0_COLSEL1_MASK 0xf 159 #define TX39_MEMCONFIG0_COLSEL1(cr) \ 160 (((cr) >> TX39_MEMCONFIG0_COLSEL1_SHIFT) & \ 161 TX39_MEMCONFIG0_COLSEL1_MASK) 162 #define TX39_MEMCONFIG0_COLSEL1_SET(cr, val) \ 163 ((cr) | (((val) << TX39_MEMCONFIG0_COLSEL1_SHIFT) & \ 164 (TX39_MEMCONFIG0_COLSEL1_MASK << TX39_MEMCONFIG0_COLSEL1_SHIFT))) 165 #define TX39_MEMCONFIG0_COLSEL0_SHIFT 4 166 #define TX39_MEMCONFIG0_COLSEL0_MASK 0xf 167 #define TX39_MEMCONFIG0_COLSEL0(cr) \ 168 (((cr) >> TX39_MEMCONFIG0_COLSEL0_SHIFT) & \ 169 TX39_MEMCONFIG0_COLSEL0_MASK) 170 #define TX39_MEMCONFIG0_COLSEL0_SET(cr, val) \ 171 ((cr) | (((val) << TX39_MEMCONFIG0_COLSEL0_SHIFT) & \ 172 (TX39_MEMCONFIG0_COLSEL0_MASK << TX39_MEMCONFIG0_COLSEL0_SHIFT))) 173 174 #define TX39_MEMCONFIG0_CS3SIZE 0x00000008 175 #define TX39_MEMCONFIG0_CS2SIZE 0x00000004 176 #define TX39_MEMCONFIG0_CS1SIZE 0x00000002 177 #define TX39_MEMCONFIG0_CS0SIZE 0x00000001 178 179 /* 180 * Memory Configuration 1 Register 181 */ 182 #ifdef TX391X 183 #define TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT 28 184 #define TX39_MEMCONFIG1_MCS3ACCVAL1_MASK 0xf 185 #define TX39_MEMCONFIG1_MCS3ACCVAL1(cr) \ 186 (((cr) >> TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT) & \ 187 TX39_MEMCONFIG1_MCS3ACCVAL1_MASK) 188 #define TX39_MEMCONFIG1_MCS3ACCVAL1_SET(cr, val) \ 189 ((cr) | (((val) << TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT) & \ 190 (TX39_MEMCONFIG1_MCS3ACCVAL1_MASK << \ 191 TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT))) 192 193 #define TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT 24 194 #define TX39_MEMCONFIG1_MCS3ACCVAL2_MASK 0xf 195 #define TX39_MEMCONFIG1_MCS3ACCVAL2(cr) \ 196 (((cr) >> TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT) & \ 197 TX39_MEMCONFIG1_MCS3ACCVAL2_MASK) 198 #define TX39_MEMCONFIG1_MCS3ACCVAL2_SET(cr, val) \ 199 ((cr) | (((val) << TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT) & \ 200 (TX39_MEMCONFIG1_MCS3ACCVAL2_MASK << \ 201 TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT))) 202 203 #define TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT 20 204 #define TX39_MEMCONFIG1_MCS2ACCVAL1_MASK 0xf 205 #define TX39_MEMCONFIG1_MCS2ACCVAL1(cr) \ 206 (((cr) >> TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT) & \ 207 TX39_MEMCONFIG1_MCS2ACCVAL1_MASK) 208 #define TX39_MEMCONFIG1_MCS2ACCVAL1_SET(cr, val) \ 209 ((cr) | (((val) << TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT) & \ 210 (TX39_MEMCONFIG1_MCS2ACCVAL1_MASK << \ 211 TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT))) 212 213 #define TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT 16 214 #define TX39_MEMCONFIG1_MCS2ACCVAL2_MASK 0xf 215 #define TX39_MEMCONFIG1_MCS2ACCVAL2(cr) \ 216 (((cr) >> TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT) & \ 217 TX39_MEMCONFIG1_MCS2ACCVAL2_MASK) 218 #define TX39_MEMCONFIG1_MCS2ACCVAL2_SET(cr, val) \ 219 ((cr) | (((val) << TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT) & \ 220 (TX39_MEMCONFIG1_MCS2ACCVAL2_MASK << \ 221 TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT))) 222 #endif /* TX391X */ 223 #ifdef TX392X 224 #define TX39_MEMCONFIG1_C48MPLLON 0x40000000 225 #define TX39_MEMCONFIG1_ENMCS1BE 0x20000000 226 #define TX39_MEMCONFIG1_ENMCS0BE 0x10000000 227 #define TX39_MEMCONFIG1_ENMCS1ACC 0x08000000 228 #define TX39_MEMCONFIG1_ENMCS0ACC 0x04000000 229 #define TX39_MEMCONFIG1_BCLKDIV_SHIFT 23 230 #define TX39_MEMCONFIG1_BCLKDIV_MASK 0x7 231 #define TX39_MEMCONFIG1_BCLKDIV(cr) \ 232 (((cr) >> TX39_MEMCONFIG1_BCLKDIV_SHIFT) & \ 233 TX39_MEMCONFIG1_BCLKDIV_MASK) 234 #define TX39_MEMCONFIG1_BCLKDIV_SET(cr, val) \ 235 ((cr) | (((val) << TX39_MEMCONFIG1_BCLKDIV_SHIFT) & \ 236 (TX39_MEMCONFIG1_BCLKDIV_MASK << TX39_MEMCONFIG1_BCLKDIV_SHIFT))) 237 #define TX39_MEMCONFIG1_ENBCLK 0x00400000 238 #define TX39_MEMCONFIG1_ENMCS1PAGE 0x00200000 239 #define TX39_MEMCONFIG1_ENMCS0PAGE 0x00100000 240 #define TX39_MEMCONFIG1_ENMCS1WAIT 0x00080000 241 #define TX39_MEMCONFIG1_ENMCS0WAIT 0x00040000 242 #define TX39_MEMCONFIG1_MCS1_32 0x00020000 243 #define TX39_MEMCONFIG1_MCS0_32 0x00010000 244 #endif /* TX392X */ 245 246 #define TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT 12 247 #define TX39_MEMCONFIG1_MCS1ACCVAL1_MASK 0xf 248 #define TX39_MEMCONFIG1_MCS1ACCVAL1(cr) \ 249 (((cr) >> TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT) & \ 250 TX39_MEMCONFIG1_MCS1ACCVAL1_MASK) 251 #define TX39_MEMCONFIG1_MCS1ACCVAL1_SET(cr, val) \ 252 ((cr) | (((val) << TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT) & \ 253 (TX39_MEMCONFIG1_MCS1ACCVAL1_MASK << \ 254 TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT))) 255 256 #define TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT 8 257 #define TX39_MEMCONFIG1_MCS1ACCVAL2_MASK 0xf 258 #define TX39_MEMCONFIG1_MCS1ACCVAL2(cr) \ 259 (((cr) >> TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT) & \ 260 TX39_MEMCONFIG1_MCS1ACCVAL2_MASK) 261 #define TX39_MEMCONFIG1_MCS1ACCVAL2_SET(cr, val) \ 262 ((cr) | (((val) << TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT) & \ 263 (TX39_MEMCONFIG1_MCS1ACCVAL2_MASK << \ 264 TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT))) 265 266 #define TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT 4 267 #define TX39_MEMCONFIG1_MCS0ACCVAL1_MASK 0xf 268 #define TX39_MEMCONFIG1_MCS0ACCVAL1(cr) \ 269 (((cr) >> TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT) & \ 270 TX39_MEMCONFIG1_MCS0ACCVAL1_MASK) 271 #define TX39_MEMCONFIG1_MCS0ACCVAL1_SET(cr, val) \ 272 ((cr) | (((val) << TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT) & \ 273 (TX39_MEMCONFIG1_MCS0ACCVAL1_MASK << \ 274 TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT))) 275 276 #define TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT 0 277 #define TX39_MEMCONFIG1_MCS0ACCVAL2_MASK 0xf 278 #define TX39_MEMCONFIG1_MCS0ACCVAL2(cr) \ 279 (((cr) >> TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT) & \ 280 TX39_MEMCONFIG1_MCS0ACCVAL2_MASK) 281 #define TX39_MEMCONFIG1_MCS0ACCVAL2_SET(cr, val) \ 282 ((cr) | (((val) << TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT) & \ 283 (TX39_MEMCONFIG1_MCS0ACCVAL2_MASK << \ 284 TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT))) 285 286 /* 287 * Memory Configuration 2 Register 288 */ 289 /* Define access timing. not required yet */ 290 #define TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT 28 291 #define TX39_MEMCONFIG2_CS3ACCVAL1_MASK 0xf 292 #define TX39_MEMCONFIG2_CS3ACCVAL1(cr) \ 293 (((cr) >> TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT) & \ 294 TX39_MEMCONFIG2_CS3ACCVAL1_MASK) 295 #define TX39_MEMCONFIG2_CS3ACCVAL1_SET(cr, val) \ 296 ((cr) | (((val) << TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT) & \ 297 (TX39_MEMCONFIG2_CS3ACCVAL1_MASK << TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT))) 298 299 #define TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT 24 300 #define TX39_MEMCONFIG2_CS3ACCVAL2_MASK 0xf 301 #define TX39_MEMCONFIG2_CS3ACCVAL2(cr) \ 302 (((cr) >> TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT) & \ 303 TX39_MEMCONFIG2_CS3ACCVAL2_MASK) 304 #define TX39_MEMCONFIG2_CS3ACCVAL2_SET(cr, val) \ 305 ((cr) | (((val) << TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT) & \ 306 (TX39_MEMCONFIG2_CS3ACCVAL2_MASK << TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT))) 307 308 #define TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT 20 309 #define TX39_MEMCONFIG2_CS2ACCVAL1_MASK 0xf 310 #define TX39_MEMCONFIG2_CS2ACCVAL1(cr) \ 311 (((cr) >> TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT) & \ 312 TX39_MEMCONFIG2_CS2ACCVAL1_MASK) 313 #define TX39_MEMCONFIG2_CS2ACCVAL1_SET(cr, val) \ 314 ((cr) | (((val) << TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT) & \ 315 (TX39_MEMCONFIG2_CS2ACCVAL1_MASK << TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT))) 316 317 #define TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT 16 318 #define TX39_MEMCONFIG2_CS2ACCVAL2_MASK 0xf 319 #define TX39_MEMCONFIG2_CS2ACCVAL2(cr) \ 320 (((cr) >> TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT) & \ 321 TX39_MEMCONFIG2_CS2ACCVAL2_MASK) 322 #define TX39_MEMCONFIG2_CS2ACCVAL2_SET(cr, val) \ 323 ((cr) | (((val) << TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT) & \ 324 (TX39_MEMCONFIG2_CS2ACCVAL2_MASK << TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT))) 325 326 #define TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT 12 327 #define TX39_MEMCONFIG2_CS1ACCVAL1_MASK 0xf 328 #define TX39_MEMCONFIG2_CS1ACCVAL1(cr) \ 329 (((cr) >> TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT) & \ 330 TX39_MEMCONFIG2_CS1ACCVAL1_MASK) 331 #define TX39_MEMCONFIG2_CS1ACCVAL1_SET(cr, val) \ 332 ((cr) | (((val) << TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT) & \ 333 (TX39_MEMCONFIG2_CS1ACCVAL1_MASK << TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT))) 334 335 #define TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT 8 336 #define TX39_MEMCONFIG2_CS1ACCVAL2_MASK 0xf 337 #define TX39_MEMCONFIG2_CS1ACCVAL2(cr) \ 338 (((cr) >> TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT) & \ 339 TX39_MEMCONFIG2_CS1ACCVAL2_MASK) 340 #define TX39_MEMCONFIG2_CS1ACCVAL2_SET(cr, val) \ 341 ((cr) | (((val) << TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT) & \ 342 (TX39_MEMCONFIG2_CS1ACCVAL2_MASK << TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT))) 343 344 #define TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT 4 345 #define TX39_MEMCONFIG2_CS0ACCVAL1_MASK 0xf 346 #define TX39_MEMCONFIG2_CS0ACCVAL1(cr) \ 347 (((cr) >> TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT) & \ 348 TX39_MEMCONFIG2_CS0ACCVAL1_MASK) 349 #define TX39_MEMCONFIG2_CS0ACCVAL1_SET(cr, val) \ 350 ((cr) | (((val) << TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT) & \ 351 (TX39_MEMCONFIG2_CS0ACCVAL1_MASK << TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT))) 352 353 #define TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT 0 354 #define TX39_MEMCONFIG2_CS0ACCVAL2_MASK 0xf 355 #define TX39_MEMCONFIG2_CS0ACCVAL2(cr) \ 356 (((cr) >> TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT) & \ 357 TX39_MEMCONFIG2_CS0ACCVAL2_MASK) 358 #define TX39_MEMCONFIG2_CS0ACCVAL2_SET(cr, val) \ 359 ((cr) | (((val) << TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT) & \ 360 (TX39_MEMCONFIG2_CS0ACCVAL2_MASK << TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT))) 361 362 /* 363 * Memory Configuration 3 Register 364 */ 365 /* Define access timing, enable read page mode, PC-Card. */ 366 #define TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT 28 367 #define TX39_MEMCONFIG3_CARD2ACCVAL_MASK 0xf 368 #define TX39_MEMCONFIG3_CARD2ACCVAL(cr) \ 369 (((cr) >> TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT) & \ 370 TX39_MEMCONFIG3_CARD2ACCVAL_MASK) 371 #define TX39_MEMCONFIG3_CARD2ACCVAL_SET(cr, val) \ 372 ((cr) | (((val) << TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT) & \ 373 (TX39_MEMCONFIG3_CARD2ACCVAL_MASK << \ 374 TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT))) 375 376 #define TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT 24 377 #define TX39_MEMCONFIG3_CARD1ACCVAL_MASK 0xf 378 #define TX39_MEMCONFIG3_CARD1ACCVAL(cr) \ 379 (((cr) >> TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT) & \ 380 TX39_MEMCONFIG3_CARD1ACCVAL_MASK) 381 #define TX39_MEMCONFIG3_CARD1ACCVAL_SET(cr, val) \ 382 ((cr) | (((val) << TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT) & \ 383 (TX39_MEMCONFIG3_CARD1ACCVAL_MASK << \ 384 TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT))) 385 386 #define TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT 20 387 #define TX39_MEMCONFIG3_CARD2IOACCVAL_MASK 0xf 388 #define TX39_MEMCONFIG3_CARD2IOACCVAL(cr) \ 389 (((cr) >> TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT) & \ 390 TX39_MEMCONFIG3_CARD2IOACCVAL_MASK) 391 #define TX39_MEMCONFIG3_CARD2IOACCVAL_SET(cr, val) \ 392 ((cr) | (((val) << TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT) & \ 393 (TX39_MEMCONFIG3_CARD2IOACCVAL_MASK << \ 394 TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT))) 395 396 #define TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT 16 397 #define TX39_MEMCONFIG3_CARD1IOACCVAL_MASK 0xf 398 #define TX39_MEMCONFIG3_CARD1IOACCVAL(cr) \ 399 (((cr) >> TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT) & \ 400 TX39_MEMCONFIG3_CARD1IOACCVAL_MASK) 401 #define TX39_MEMCONFIG3_CARD1IOACCVAL_SET(cr, val) \ 402 ((cr) | (((val) << TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT) & \ 403 (TX39_MEMCONFIG3_CARD1IOACCVAL_MASK << \ 404 TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT))) 405 #ifdef TX391X 406 #define TX39_MEMCONFIG3_ENMCS3PAGE 0x00008000 407 #define TX39_MEMCONFIG3_ENMCS2PAGE 0x00004000 408 #define TX39_MEMCONFIG3_ENMCS1PAGE 0x00002000 409 #define TX39_MEMCONFIG3_ENMCS0PAGE 0x00001000 410 #endif /* TX391X */ 411 #define TX39_MEMCONFIG3_ENCS3PAGE 0x00000800 412 #define TX39_MEMCONFIG3_ENCS2PAGE 0x00000400 413 #define TX39_MEMCONFIG3_ENCS1PAGE 0x00000200 414 #define TX39_MEMCONFIG3_ENCS0PAGE 0x00000100 415 #define TX39_MEMCONFIG3_CARD2WAITEN 0x00000080 416 #define TX39_MEMCONFIG3_CARD1WAITEN 0x00000040 417 #define TX39_MEMCONFIG3_CARD2IOEN 0x00000020 418 #define TX39_MEMCONFIG3_CARD1IOEN 0x00000010 419 #ifdef TX391X 420 #define TX39_MEMCONFIG3_PORT8SEL 0x00000008 421 #endif /* TX391X */ 422 #ifdef TX392X 423 #define TX39_MEMCONFIG3_CARD2_8SEL 0x00000008 424 #define TX39_MEMCONFIG3_CARD1_8SEL 0x00000004 425 #endif /* TX392X */ 426 /* 427 * Memory Configuration 4 Register 428 */ 429 /* DMA */ 430 #define TX39_MEMCONFIG4_ENBANK1HDRAM 0x80000000 431 #define TX39_MEMCONFIG4_ENBANK0HDRAM 0x40000000 432 #define TX39_MEMCONFIG4_ENARB 0x20000000 433 #define TX39_MEMCONFIG4_DISSNOOP 0x10000000 434 #define TX39_MEMCONFIG4_CLRWRBUSERRINT 0x08000000 435 #define TX39_MEMCONFIG4_ENBANK1OPT 0x04000000 436 #define TX39_MEMCONFIG4_ENBANK0OPT 0x02000000 437 #define TX39_MEMCONFIG4_ENWATCH 0x01000000 438 439 /* 440 * WatchDogTimerRate = (WATCHTIME[3:0] + 1) * 64 / 36.864MHz 441 */ 442 #define TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT 20 443 #define TX39_MEMCONFIG4_WATCHTIMEVAL_MASK 0xf 444 #define TX39_MEMCONFIG4_WATCHTIMEVAL(cr) \ 445 (((cr) >> TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT) & \ 446 TX39_MEMCONFIG4_WATCHTIMEVAL_MASK) 447 #define TX39_MEMCONFIG4_WATCHTIMEVAL_SET(cr, val) \ 448 ((cr) | (((val) << TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT) & \ 449 (TX39_MEMCONFIG4_WATCHTIMEVAL_MASK << \ 450 TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT))) 451 452 453 #define TX39_MEMCONFIG4_MEMPOWERDOWN 0x00010000 454 #define TX39_MEMCONFIG4_ENRFSH1 0x00008000 455 #define TX39_MEMCONFIG4_ENRFSH0 0x00004000 456 457 #define TX39_MEMCONFIG4_RFSHVAL1_SHIFT 8 458 #define TX39_MEMCONFIG4_RFSHVAL1_MASK 0x3f 459 #define TX39_MEMCONFIG4_RFSHVAL1(cr) \ 460 (((cr) >> TX39_MEMCONFIG4_RFSHVAL1_SHIFT) & \ 461 TX39_MEMCONFIG4_RFSHVAL1_MASK) 462 #define TX39_MEMCONFIG4_RFSHVAL1_SET(cr, val) \ 463 ((cr) | (((val) << TX39_MEMCONFIG4_RFSHVAL1_SHIFT) & \ 464 (TX39_MEMCONFIG4_RFSHVAL1_MASK << TX39_MEMCONFIG4_RFSHVAL1_SHIFT))) 465 466 #define TX39_MEMCONFIG4_RFSHVAL0_SHIFT 0 467 #define TX39_MEMCONFIG4_RFSHVAL0_MASK 0x3f 468 #define TX39_MEMCONFIG4_RFSHVAL0(cr) \ 469 (((cr) >> TX39_MEMCONFIG4_RFSHVAL0_SHIFT) & \ 470 TX39_MEMCONFIG4_RFSHVAL0_MASK) 471 #define TX39_MEMCONFIG4_RFSHVAL0_SET(cr, val) \ 472 ((cr) | (((val) << TX39_MEMCONFIG4_RFSHVAL0_SHIFT) & \ 473 (TX39_MEMCONFIG4_RFSHVAL0_MASK << TX39_MEMCONFIG4_RFSHVAL0_SHIFT))) 474 475 /* 476 * Memory Configuration 5 Register 477 */ 478 /* Address remap region 2 */ 479 #define TX39_MEMCONFIG5_STARTVAL2_SHIFT 9 480 #define TX39_MEMCONFIG5_STARTVAL2_MASK 0x007fffff 481 #define TX39_MEMCONFIG5_STARTVAL2(cr) \ 482 (((cr) >> TX39_MEMCONFIG5_STARTVAL2_SHIFT) & \ 483 TX39_MEMCONFIG5_STARTVAL2_MASK) 484 #define TX39_MEMCONFIG5_STARTVAL2_SET(cr, val) \ 485 ((cr) | (((val) << TX39_MEMCONFIG5_STARTVAL2_SHIFT) & \ 486 (TX39_MEMCONFIG5_STARTVAL2_MASK << TX39_MEMCONFIG5_STARTVAL2_SHIFT))) 487 488 #define TX39_MEMCONFIG5_MASK2_SHIFT 0 489 #define TX39_MEMCONFIG5_MASK2_MASK 0xf 490 #define TX39_MEMCONFIG5_MASK2(cr) \ 491 (((cr) >> TX39_MEMCONFIG5_MASK2_SHIFT) & \ 492 TX39_MEMCONFIG5_MASK2_MASK) 493 #define TX39_MEMCONFIG5_MASK2_SET(cr, val) \ 494 ((cr) | (((val) << TX39_MEMCONFIG5_MASK2_SHIFT) & \ 495 (TX39_MEMCONFIG5_MASK2_MASK << TX39_MEMCONFIG5_MASK2_SHIFT))) 496 497 /* 498 * Memory Configuration 6 Register 499 */ 500 /* Address remap region 1 */ 501 #define TX39_MEMCONFIG6_STARTVAL1_SHIFT 9 502 #define TX39_MEMCONFIG6_STARTVAL1_MASK 0x007fffff 503 #define TX39_MEMCONFIG6_STARTVAL1(cr) \ 504 (((cr) >> TX39_MEMCONFIG6_STARTVAL1_SHIFT) & \ 505 TX39_MEMCONFIG6_STARTVAL1_MASK) 506 #define TX39_MEMCONFIG6_STARTVAL1_SET(cr, val) \ 507 ((cr) | (((val) << TX39_MEMCONFIG6_STARTVAL1_SHIFT) & \ 508 (TX39_MEMCONFIG6_STARTVAL1_MASK << TX39_MEMCONFIG6_STARTVAL1_SHIFT))) 509 510 #define TX39_MEMCONFIG6_MASK1_SHIFT 0 511 #define TX39_MEMCONFIG6_MASK1_MASK 0xf 512 #define TX39_MEMCONFIG6_MASK1(cr) \ 513 (((cr) >> TX39_MEMCONFIG6_MASK1_SHIFT) & \ 514 TX39_MEMCONFIG6_MASK1_MASK) 515 #define TX39_MEMCONFIG6_MASK1_SET(cr, val) \ 516 ((cr) | (((val) << TX39_MEMCONFIG6_MASK1_SHIFT) & \ 517 (TX39_MEMCONFIG6_MASK1_MASK << TX39_MEMCONFIG6_MASK1_SHIFT))) 518 519 /* 520 * Memory Configuration 7 Register 521 */ 522 /* Address remap region 2 */ 523 #define TX39_MEMCONFIG7_RMAPADD2_SHIFT 9 524 #define TX39_MEMCONFIG7_RMAPADD2_MASK 0x007fffff 525 #define TX39_MEMCONFIG7_RMAPADD2(cr) \ 526 (((cr) >> TX39_MEMCONFIG7_RMAPADD2_SHIFT) & \ 527 TX39_MEMCONFIG7_RMAPADD2_MASK) 528 #define TX39_MEMCONFIG7_RMAPADD2_SET(cr, val) \ 529 ((cr) | (((val) << TX39_MEMCONFIG7_RMAPADD2_SHIFT) & \ 530 (TX39_MEMCONFIG7_RMAPADD2_MASK << TX39_MEMCONFIG7_RMAPADD2_SHIFT))) 531 532 /* 533 * Memory Configuration 8 Register 534 */ 535 /* Address remap region 1 */ 536 #define TX39_MEMCONFIG8_RMAPADD1_SHIFT 9 537 #define TX39_MEMCONFIG8_RMAPADD1_MASK 0x007fffff 538 #define TX39_MEMCONFIG8_RMAPADD1(cr) \ 539 (((cr) >> TX39_MEMCONFIG8_RMAPADD1_SHIFT) & \ 540 TX39_MEMCONFIG8_RMAPADD1_MASK) 541 #define TX39_MEMCONFIG8_RMAPADD1_SET(cr, val) \ 542 ((cr) | (((val) << TX39_MEMCONFIG8_RMAPADD1_SHIFT) & \ 543 (TX39_MEMCONFIG8_RMAPADD1_MASK << TX39_MEMCONFIG8_RMAPADD1_SHIFT))) 544
Indexes created Wed Nov 05 01:09:58 GMT 2025