tx39biureg.h revision 1.3.8.2
1 /* $NetBSD: tx39biureg.h,v 1.3.8.2 2001/06/14 11:09:56 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 /* 39 * Toshiba TX3912/3922 BIU module (Bus Interface Unit) 40 */ 41 42 /* 43 * System Address Map 44 */ 45 #define TX39_SYSADDR_DRAMBANK0CS1 0x00000000 46 #define TX39_SYSADDR_DRAMBANK1CS1 0x02000000 47 #define TX39_SYSADDR_DRAMBANK0 0x04000000 48 #define TX39_SYSADDR_DRAMBANK1 0x06000000 49 #define TX39_SYSADDR_DRAMBANK_LEN 0x02000000 50 51 #define TX39_SYSADDR_CARD1 0x08000000 52 #define TX39_SYSADDR_CARD2 0x0C000000 53 /* 64MByte */ 54 #define TX39_SYSADDR_CARD_SIZE 0x04000000 55 56 #define TX39_SYSADDR_CS1 0x10000000 57 #define TX39_SYSADDR_CS2 0x10400000 58 #define TX39_SYSADDR_CS3 0x10800000 59 /* 4MByte */ 60 #define TX39_SYSADDR_CS_SIZE 0x00400000 61 62 #define TX39_SYSADDR_CONFIG_REG 0x10c00000 63 #define TX39_SYSADDR_CONFIG_REG_LEN 0x00200000 64 65 #define TX39_SYSADDR_SDRAMBANK0MODE_REG 0x10e00000 66 #define TX39_SYSADDR_SDRAMBANK1MODE_REG 0x10f00000 67 #define TX39_SYSADDR_CS0 0x11000000 68 #define TX39_SYSADDR_KUSEG_DRAMBANK0CS1 0x40000000 69 #define TX39_SYSADDR_KUSEG_DRAMBANK1CS1 0x42000000 70 #define TX39_SYSADDR_KUSEG_DRAMBANK0 0x44000000 71 #define TX39_SYSADDR_KUSEG_DRAMBANK1 0x46000000 72 #define TX39_SYSADDR_KUSEG_CS0 0x50000000 73 #define TX39_SYSADDR_KUSEG_CS1 0x58000000 74 #define TX39_SYSADDR_KUSEG_CS2 0x5c000000 75 #define TX39_SYSADDR_KUSEG_CS3 0x60000000 76 #define TX39_SYSADDR_CARD1MEM 0x64000000 77 #define TX39_SYSADDR_CARD2MEM 0x68000000 78 #define TX39_SYSADDR_MCS0 0x6c000000 79 #define TX39_SYSADDR_MCS1 0x70000000 80 #ifdef TX391X 81 #define TX39_SYSADDR_MCS2 0x74000000 82 #define TX39_SYSADDR_MCS3 0x78000000 83 #endif /* TX391X */ 84 /* 64MByte */ 85 #define TX39_SYSADDR_MCS_SIZE 0x04000000 86 87 /* 88 * BIU module registers. 89 */ 90 #define TX39_MEMCONFIG0_REG 0x00 91 #define TX39_MEMCONFIG1_REG 0x04 92 #define TX39_MEMCONFIG2_REG 0x08 93 #define TX39_MEMCONFIG3_REG 0x0C 94 #define TX39_MEMCONFIG4_REG 0x10 95 #define TX39_MEMCONFIG5_REG 0x14 96 #define TX39_MEMCONFIG6_REG 0x18 97 #define TX39_MEMCONFIG7_REG 0x1C 98 #define TX39_MEMCONFIG8_REG 0x20 99 100 /* 101 * Memory Configuration 0 Register 102 */ 103 /* R/W */ 104 #define TX39_MEMCONFIG0_ENDCLKOUTTRI 0x40000000 105 #define TX39_MEMCONFIG0_DISDQMINIT 0x20000000 106 #define TX39_MEMCONFIG0_ENSDRAMPD 0x10000000 107 #define TX39_MEMCONFIG0_SHOWDINO 0x08000000 108 #define TX39_MEMCONFIG0_ENRMAP2 0x04000000 109 #define TX39_MEMCONFIG0_ENRMAP1 0x02000000 110 #define TX39_MEMCONFIG0_ENWRINPAGE 0x01000000 111 #define TX39_MEMCONFIG0_ENCS3USER 0x00800000 112 #define TX39_MEMCONFIG0_ENCS2USER 0x00400000 113 #define TX39_MEMCONFIG0_ENCS1USER 0x00200000 114 #define TX39_MEMCONFIG0_ENCS1DRAM 0x00100000 115 116 #define TX39_MEMCONFIG0_BANK1CONF_SHIFT 18 117 #define TX39_MEMCONFIG0_BANK1CONF_MASK 0x3 118 #define TX39_MEMCONFIG0_BANK1CONF(cr) \ 119 (((cr) >> TX39_MEMCONFIG0_BANK1CONF_SHIFT) & \ 120 TX39_MEMCONFIG0_BANK1CONF_MASK) 121 #define TX39_MEMCONFIG0_BANK1CONF_SET(cr, val) \ 122 ((cr) | (((val) << TX39_MEMCONFIG0_BANK1CONF_SHIFT) & \ 123 (TX39_MEMCONFIG0_BANK1CONF_MASK << TX39_MEMCONFIG0_BANK1CONF_SHIFT))) 124 #define TX39_MEMCONFIG0_BANK0CONF_SHIFT 16 125 #define TX39_MEMCONFIG0_BANK0CONF_MASK 0x3 126 #define TX39_MEMCONFIG0_BANK0CONF(cr) \ 127 (((cr) >> TX39_MEMCONFIG0_BANK0CONF_SHIFT) & \ 128 TX39_MEMCONFIG0_BANK0CONF_MASK) 129 #define TX39_MEMCONFIG0_BANK0CONF_SET(cr, val) \ 130 ((cr) | (((val) << TX39_MEMCONFIG0_BANK0CONF_SHIFT) & \ 131 (TX39_MEMCONFIG0_BANK0CONF_MASK << TX39_MEMCONFIG0_BANK0CONF_SHIFT))) 132 #define TX39_MEMCONFIG0_BANKCONF_16BITSDRAM 0x3 133 #define TX39_MEMCONFIG0_BANKCONF_8BITSDRAM 0x2 134 #define TX39_MEMCONFIG0_BANKCONF_32BITSDHDRAM 0x1 135 #define TX39_MEMCONFIG0_BANKCONF_16BITSDHDRAM 0x0 136 137 #define TX39_MEMCONFIG0_ROWSEL1_SHIFT 14 138 #define TX39_MEMCONFIG0_ROWSEL1_MASK 0x3 139 #define TX39_MEMCONFIG0_ROWSEL1(cr) \ 140 (((cr) >> TX39_MEMCONFIG0_ROWSEL1_SHIFT) & \ 141 TX39_MEMCONFIG0_ROWSEL1_MASK) 142 #define TX39_MEMCONFIG0_ROWSEL1_SET(cr, val) \ 143 ((cr) | (((val) << TX39_MEMCONFIG0_ROWSEL1_SHIFT) & \ 144 (TX39_MEMCONFIG0_ROWSEL1_MASK << TX39_MEMCONFIG0_ROWSEL1_SHIFT))) 145 #define TX39_MEMCONFIG0_ROWSEL0_SHIFT 12 146 #define TX39_MEMCONFIG0_ROWSEL0_MASK 0x3 147 #define TX39_MEMCONFIG0_ROWSEL0(cr) \ 148 (((cr) >> TX39_MEMCONFIG0_ROWSEL0_SHIFT) & \ 149 TX39_MEMCONFIG0_ROWSEL0_MASK) 150 #define TX39_MEMCONFIG0_ROWSEL0_SET(cr, val) \ 151 ((cr) | (((val) << TX39_MEMCONFIG0_ROWSEL0_SHIFT) & \ 152 (TX39_MEMCONFIG0_ROWSEL0_MASK << TX39_MEMCONFIG0_ROWSEL0_SHIFT))) 153 154 #define TX39_MEMCONFIG0_COLSEL1_SHIFT 8 155 #define TX39_MEMCONFIG0_COLSEL1_MASK 0xf 156 #define TX39_MEMCONFIG0_COLSEL1(cr) \ 157 (((cr) >> TX39_MEMCONFIG0_COLSEL1_SHIFT) & \ 158 TX39_MEMCONFIG0_COLSEL1_MASK) 159 #define TX39_MEMCONFIG0_COLSEL1_SET(cr, val) \ 160 ((cr) | (((val) << TX39_MEMCONFIG0_COLSEL1_SHIFT) & \ 161 (TX39_MEMCONFIG0_COLSEL1_MASK << TX39_MEMCONFIG0_COLSEL1_SHIFT))) 162 #define TX39_MEMCONFIG0_COLSEL0_SHIFT 4 163 #define TX39_MEMCONFIG0_COLSEL0_MASK 0xf 164 #define TX39_MEMCONFIG0_COLSEL0(cr) \ 165 (((cr) >> TX39_MEMCONFIG0_COLSEL0_SHIFT) & \ 166 TX39_MEMCONFIG0_COLSEL0_MASK) 167 #define TX39_MEMCONFIG0_COLSEL0_SET(cr, val) \ 168 ((cr) | (((val) << TX39_MEMCONFIG0_COLSEL0_SHIFT) & \ 169 (TX39_MEMCONFIG0_COLSEL0_MASK << TX39_MEMCONFIG0_COLSEL0_SHIFT))) 170 171 #define TX39_MEMCONFIG0_CS3SIZE 0x00000008 172 #define TX39_MEMCONFIG0_CS2SIZE 0x00000004 173 #define TX39_MEMCONFIG0_CS1SIZE 0x00000002 174 #define TX39_MEMCONFIG0_CS0SIZE 0x00000001 175 176 /* 177 * Memory Configuration 1 Register 178 */ 179 #ifdef TX391X 180 #define TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT 28 181 #define TX39_MEMCONFIG1_MCS3ACCVAL1_MASK 0xf 182 #define TX39_MEMCONFIG1_MCS3ACCVAL1(cr) \ 183 (((cr) >> TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT) & \ 184 TX39_MEMCONFIG1_MCS3ACCVAL1_MASK) 185 #define TX39_MEMCONFIG1_MCS3ACCVAL1_SET(cr, val) \ 186 ((cr) | (((val) << TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT) & \ 187 (TX39_MEMCONFIG1_MCS3ACCVAL1_MASK << \ 188 TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT))) 189 190 #define TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT 24 191 #define TX39_MEMCONFIG1_MCS3ACCVAL2_MASK 0xf 192 #define TX39_MEMCONFIG1_MCS3ACCVAL2(cr) \ 193 (((cr) >> TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT) & \ 194 TX39_MEMCONFIG1_MCS3ACCVAL2_MASK) 195 #define TX39_MEMCONFIG1_MCS3ACCVAL2_SET(cr, val) \ 196 ((cr) | (((val) << TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT) & \ 197 (TX39_MEMCONFIG1_MCS3ACCVAL2_MASK << \ 198 TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT))) 199 200 #define TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT 20 201 #define TX39_MEMCONFIG1_MCS2ACCVAL1_MASK 0xf 202 #define TX39_MEMCONFIG1_MCS2ACCVAL1(cr) \ 203 (((cr) >> TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT) & \ 204 TX39_MEMCONFIG1_MCS2ACCVAL1_MASK) 205 #define TX39_MEMCONFIG1_MCS2ACCVAL1_SET(cr, val) \ 206 ((cr) | (((val) << TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT) & \ 207 (TX39_MEMCONFIG1_MCS2ACCVAL1_MASK << \ 208 TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT))) 209 210 #define TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT 16 211 #define TX39_MEMCONFIG1_MCS2ACCVAL2_MASK 0xf 212 #define TX39_MEMCONFIG1_MCS2ACCVAL2(cr) \ 213 (((cr) >> TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT) & \ 214 TX39_MEMCONFIG1_MCS2ACCVAL2_MASK) 215 #define TX39_MEMCONFIG1_MCS2ACCVAL2_SET(cr, val) \ 216 ((cr) | (((val) << TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT) & \ 217 (TX39_MEMCONFIG1_MCS2ACCVAL2_MASK << \ 218 TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT))) 219 #endif /* TX391X */ 220 #ifdef TX392X 221 #define TX39_MEMCONFIG1_C48MPLLON 0x40000000 222 #define TX39_MEMCONFIG1_ENMCS1BE 0x20000000 223 #define TX39_MEMCONFIG1_ENMCS0BE 0x10000000 224 #define TX39_MEMCONFIG1_ENMCS1ACC 0x08000000 225 #define TX39_MEMCONFIG1_ENMCS0ACC 0x04000000 226 #define TX39_MEMCONFIG1_BCLKDIV_SHIFT 23 227 #define TX39_MEMCONFIG1_BCLKDIV_MASK 0x7 228 #define TX39_MEMCONFIG1_BCLKDIV(cr) \ 229 (((cr) >> TX39_MEMCONFIG1_BCLKDIV_SHIFT) & \ 230 TX39_MEMCONFIG1_BCLKDIV_MASK) 231 #define TX39_MEMCONFIG1_BCLKDIV_SET(cr, val) \ 232 ((cr) | (((val) << TX39_MEMCONFIG1_BCLKDIV_SHIFT) & \ 233 (TX39_MEMCONFIG1_BCLKDIV_MASK << TX39_MEMCONFIG1_BCLKDIV_SHIFT))) 234 #define TX39_MEMCONFIG1_ENBCLK 0x00400000 235 #define TX39_MEMCONFIG1_ENMCS1PAGE 0x00200000 236 #define TX39_MEMCONFIG1_ENMCS0PAGE 0x00100000 237 #define TX39_MEMCONFIG1_ENMCS1WAIT 0x00080000 238 #define TX39_MEMCONFIG1_ENMCS0WAIT 0x00040000 239 #define TX39_MEMCONFIG1_MCS1_32 0x00020000 240 #define TX39_MEMCONFIG1_MCS0_32 0x00010000 241 #endif /* TX392X */ 242 243 #define TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT 12 244 #define TX39_MEMCONFIG1_MCS1ACCVAL1_MASK 0xf 245 #define TX39_MEMCONFIG1_MCS1ACCVAL1(cr) \ 246 (((cr) >> TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT) & \ 247 TX39_MEMCONFIG1_MCS1ACCVAL1_MASK) 248 #define TX39_MEMCONFIG1_MCS1ACCVAL1_SET(cr, val) \ 249 ((cr) | (((val) << TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT) & \ 250 (TX39_MEMCONFIG1_MCS1ACCVAL1_MASK << \ 251 TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT))) 252 253 #define TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT 8 254 #define TX39_MEMCONFIG1_MCS1ACCVAL2_MASK 0xf 255 #define TX39_MEMCONFIG1_MCS1ACCVAL2(cr) \ 256 (((cr) >> TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT) & \ 257 TX39_MEMCONFIG1_MCS1ACCVAL2_MASK) 258 #define TX39_MEMCONFIG1_MCS1ACCVAL2_SET(cr, val) \ 259 ((cr) | (((val) << TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT) & \ 260 (TX39_MEMCONFIG1_MCS1ACCVAL2_MASK << \ 261 TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT))) 262 263 #define TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT 4 264 #define TX39_MEMCONFIG1_MCS0ACCVAL1_MASK 0xf 265 #define TX39_MEMCONFIG1_MCS0ACCVAL1(cr) \ 266 (((cr) >> TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT) & \ 267 TX39_MEMCONFIG1_MCS0ACCVAL1_MASK) 268 #define TX39_MEMCONFIG1_MCS0ACCVAL1_SET(cr, val) \ 269 ((cr) | (((val) << TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT) & \ 270 (TX39_MEMCONFIG1_MCS0ACCVAL1_MASK << \ 271 TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT))) 272 273 #define TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT 0 274 #define TX39_MEMCONFIG1_MCS0ACCVAL2_MASK 0xf 275 #define TX39_MEMCONFIG1_MCS0ACCVAL2(cr) \ 276 (((cr) >> TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT) & \ 277 TX39_MEMCONFIG1_MCS0ACCVAL2_MASK) 278 #define TX39_MEMCONFIG1_MCS0ACCVAL2_SET(cr, val) \ 279 ((cr) | (((val) << TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT) & \ 280 (TX39_MEMCONFIG1_MCS0ACCVAL2_MASK << \ 281 TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT))) 282 283 /* 284 * Memory Configuration 2 Register 285 */ 286 /* Define access timing. not required yet */ 287 #define TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT 28 288 #define TX39_MEMCONFIG2_CS3ACCVAL1_MASK 0xf 289 #define TX39_MEMCONFIG2_CS3ACCVAL1(cr) \ 290 (((cr) >> TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT) & \ 291 TX39_MEMCONFIG2_CS3ACCVAL1_MASK) 292 #define TX39_MEMCONFIG2_CS3ACCVAL1_SET(cr, val) \ 293 ((cr) | (((val) << TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT) & \ 294 (TX39_MEMCONFIG2_CS3ACCVAL1_MASK << TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT))) 295 296 #define TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT 24 297 #define TX39_MEMCONFIG2_CS3ACCVAL2_MASK 0xf 298 #define TX39_MEMCONFIG2_CS3ACCVAL2(cr) \ 299 (((cr) >> TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT) & \ 300 TX39_MEMCONFIG2_CS3ACCVAL2_MASK) 301 #define TX39_MEMCONFIG2_CS3ACCVAL2_SET(cr, val) \ 302 ((cr) | (((val) << TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT) & \ 303 (TX39_MEMCONFIG2_CS3ACCVAL2_MASK << TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT))) 304 305 #define TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT 20 306 #define TX39_MEMCONFIG2_CS2ACCVAL1_MASK 0xf 307 #define TX39_MEMCONFIG2_CS2ACCVAL1(cr) \ 308 (((cr) >> TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT) & \ 309 TX39_MEMCONFIG2_CS2ACCVAL1_MASK) 310 #define TX39_MEMCONFIG2_CS2ACCVAL1_SET(cr, val) \ 311 ((cr) | (((val) << TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT) & \ 312 (TX39_MEMCONFIG2_CS2ACCVAL1_MASK << TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT))) 313 314 #define TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT 16 315 #define TX39_MEMCONFIG2_CS2ACCVAL2_MASK 0xf 316 #define TX39_MEMCONFIG2_CS2ACCVAL2(cr) \ 317 (((cr) >> TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT) & \ 318 TX39_MEMCONFIG2_CS2ACCVAL2_MASK) 319 #define TX39_MEMCONFIG2_CS2ACCVAL2_SET(cr, val) \ 320 ((cr) | (((val) << TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT) & \ 321 (TX39_MEMCONFIG2_CS2ACCVAL2_MASK << TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT))) 322 323 #define TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT 12 324 #define TX39_MEMCONFIG2_CS1ACCVAL1_MASK 0xf 325 #define TX39_MEMCONFIG2_CS1ACCVAL1(cr) \ 326 (((cr) >> TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT) & \ 327 TX39_MEMCONFIG2_CS1ACCVAL1_MASK) 328 #define TX39_MEMCONFIG2_CS1ACCVAL1_SET(cr, val) \ 329 ((cr) | (((val) << TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT) & \ 330 (TX39_MEMCONFIG2_CS1ACCVAL1_MASK << TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT))) 331 332 #define TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT 8 333 #define TX39_MEMCONFIG2_CS1ACCVAL2_MASK 0xf 334 #define TX39_MEMCONFIG2_CS1ACCVAL2(cr) \ 335 (((cr) >> TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT) & \ 336 TX39_MEMCONFIG2_CS1ACCVAL2_MASK) 337 #define TX39_MEMCONFIG2_CS1ACCVAL2_SET(cr, val) \ 338 ((cr) | (((val) << TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT) & \ 339 (TX39_MEMCONFIG2_CS1ACCVAL2_MASK << TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT))) 340 341 #define TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT 4 342 #define TX39_MEMCONFIG2_CS0ACCVAL1_MASK 0xf 343 #define TX39_MEMCONFIG2_CS0ACCVAL1(cr) \ 344 (((cr) >> TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT) & \ 345 TX39_MEMCONFIG2_CS0ACCVAL1_MASK) 346 #define TX39_MEMCONFIG2_CS0ACCVAL1_SET(cr, val) \ 347 ((cr) | (((val) << TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT) & \ 348 (TX39_MEMCONFIG2_CS0ACCVAL1_MASK << TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT))) 349 350 #define TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT 0 351 #define TX39_MEMCONFIG2_CS0ACCVAL2_MASK 0xf 352 #define TX39_MEMCONFIG2_CS0ACCVAL2(cr) \ 353 (((cr) >> TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT) & \ 354 TX39_MEMCONFIG2_CS0ACCVAL2_MASK) 355 #define TX39_MEMCONFIG2_CS0ACCVAL2_SET(cr, val) \ 356 ((cr) | (((val) << TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT) & \ 357 (TX39_MEMCONFIG2_CS0ACCVAL2_MASK << TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT))) 358 359 /* 360 * Memory Configuration 3 Register 361 */ 362 /* Define access timing, enable read page mode, PC-Card. */ 363 #define TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT 28 364 #define TX39_MEMCONFIG3_CARD2ACCVAL_MASK 0xf 365 #define TX39_MEMCONFIG3_CARD2ACCVAL(cr) \ 366 (((cr) >> TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT) & \ 367 TX39_MEMCONFIG3_CARD2ACCVAL_MASK) 368 #define TX39_MEMCONFIG3_CARD2ACCVAL_SET(cr, val) \ 369 ((cr) | (((val) << TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT) & \ 370 (TX39_MEMCONFIG3_CARD2ACCVAL_MASK << \ 371 TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT))) 372 373 #define TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT 24 374 #define TX39_MEMCONFIG3_CARD1ACCVAL_MASK 0xf 375 #define TX39_MEMCONFIG3_CARD1ACCVAL(cr) \ 376 (((cr) >> TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT) & \ 377 TX39_MEMCONFIG3_CARD1ACCVAL_MASK) 378 #define TX39_MEMCONFIG3_CARD1ACCVAL_SET(cr, val) \ 379 ((cr) | (((val) << TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT) & \ 380 (TX39_MEMCONFIG3_CARD1ACCVAL_MASK << \ 381 TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT))) 382 383 #define TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT 20 384 #define TX39_MEMCONFIG3_CARD2IOACCVAL_MASK 0xf 385 #define TX39_MEMCONFIG3_CARD2IOACCVAL(cr) \ 386 (((cr) >> TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT) & \ 387 TX39_MEMCONFIG3_CARD2IOACCVAL_MASK) 388 #define TX39_MEMCONFIG3_CARD2IOACCVAL_SET(cr, val) \ 389 ((cr) | (((val) << TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT) & \ 390 (TX39_MEMCONFIG3_CARD2IOACCVAL_MASK << \ 391 TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT))) 392 393 #define TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT 16 394 #define TX39_MEMCONFIG3_CARD1IOACCVAL_MASK 0xf 395 #define TX39_MEMCONFIG3_CARD1IOACCVAL(cr) \ 396 (((cr) >> TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT) & \ 397 TX39_MEMCONFIG3_CARD1IOACCVAL_MASK) 398 #define TX39_MEMCONFIG3_CARD1IOACCVAL_SET(cr, val) \ 399 ((cr) | (((val) << TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT) & \ 400 (TX39_MEMCONFIG3_CARD1IOACCVAL_MASK << \ 401 TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT))) 402 #ifdef TX391X 403 #define TX39_MEMCONFIG3_ENMCS3PAGE 0x00008000 404 #define TX39_MEMCONFIG3_ENMCS2PAGE 0x00004000 405 #define TX39_MEMCONFIG3_ENMCS1PAGE 0x00002000 406 #define TX39_MEMCONFIG3_ENMCS0PAGE 0x00001000 407 #endif /* TX391X */ 408 #define TX39_MEMCONFIG3_ENCS3PAGE 0x00000800 409 #define TX39_MEMCONFIG3_ENCS2PAGE 0x00000400 410 #define TX39_MEMCONFIG3_ENCS1PAGE 0x00000200 411 #define TX39_MEMCONFIG3_ENCS0PAGE 0x00000100 412 #define TX39_MEMCONFIG3_CARD2WAITEN 0x00000080 413 #define TX39_MEMCONFIG3_CARD1WAITEN 0x00000040 414 #define TX39_MEMCONFIG3_CARD2IOEN 0x00000020 415 #define TX39_MEMCONFIG3_CARD1IOEN 0x00000010 416 #ifdef TX391X 417 #define TX39_MEMCONFIG3_PORT8SEL 0x00000008 418 #endif /* TX391X */ 419 #ifdef TX392X 420 #define TX39_MEMCONFIG3_CARD2_8SEL 0x00000008 421 #define TX39_MEMCONFIG3_CARD1_8SEL 0x00000004 422 #endif /* TX392X */ 423 /* 424 * Memory Configuration 4 Register 425 */ 426 /* DMA */ 427 #define TX39_MEMCONFIG4_ENBANK1HDRAM 0x80000000 428 #define TX39_MEMCONFIG4_ENBANK0HDRAM 0x40000000 429 #define TX39_MEMCONFIG4_ENARB 0x20000000 430 #define TX39_MEMCONFIG4_DISSNOOP 0x10000000 431 #define TX39_MEMCONFIG4_CLRWRBUSERRINT 0x08000000 432 #define TX39_MEMCONFIG4_ENBANK1OPT 0x04000000 433 #define TX39_MEMCONFIG4_ENBANK0OPT 0x02000000 434 #define TX39_MEMCONFIG4_ENWATCH 0x01000000 435 436 /* 437 * WatchDogTimerRate = (WATCHTIME[3:0] + 1) * 64 / 36.864MHz 438 */ 439 #define TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT 20 440 #define TX39_MEMCONFIG4_WATCHTIMEVAL_MASK 0xf 441 #define TX39_MEMCONFIG4_WATCHTIMEVAL(cr) \ 442 (((cr) >> TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT) & \ 443 TX39_MEMCONFIG4_WATCHTIMEVAL_MASK) 444 #define TX39_MEMCONFIG4_WATCHTIMEVAL_SET(cr, val) \ 445 ((cr) | (((val) << TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT) & \ 446 (TX39_MEMCONFIG4_WATCHTIMEVAL_MASK << \ 447 TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT))) 448 449 450 #define TX39_MEMCONFIG4_MEMPOWERDOWN 0x00010000 451 #define TX39_MEMCONFIG4_ENRFSH1 0x00008000 452 #define TX39_MEMCONFIG4_ENRFSH0 0x00004000 453 454 #define TX39_MEMCONFIG4_RFSHVAL1_SHIFT 8 455 #define TX39_MEMCONFIG4_RFSHVAL1_MASK 0x3f 456 #define TX39_MEMCONFIG4_RFSHVAL1(cr) \ 457 (((cr) >> TX39_MEMCONFIG4_RFSHVAL1_SHIFT) & \ 458 TX39_MEMCONFIG4_RFSHVAL1_MASK) 459 #define TX39_MEMCONFIG4_RFSHVAL1_SET(cr, val) \ 460 ((cr) | (((val) << TX39_MEMCONFIG4_RFSHVAL1_SHIFT) & \ 461 (TX39_MEMCONFIG4_RFSHVAL1_MASK << TX39_MEMCONFIG4_RFSHVAL1_SHIFT))) 462 463 #define TX39_MEMCONFIG4_RFSHVAL0_SHIFT 0 464 #define TX39_MEMCONFIG4_RFSHVAL0_MASK 0x3f 465 #define TX39_MEMCONFIG4_RFSHVAL0(cr) \ 466 (((cr) >> TX39_MEMCONFIG4_RFSHVAL0_SHIFT) & \ 467 TX39_MEMCONFIG4_RFSHVAL0_MASK) 468 #define TX39_MEMCONFIG4_RFSHVAL0_SET(cr, val) \ 469 ((cr) | (((val) << TX39_MEMCONFIG4_RFSHVAL0_SHIFT) & \ 470 (TX39_MEMCONFIG4_RFSHVAL0_MASK << TX39_MEMCONFIG4_RFSHVAL0_SHIFT))) 471 472 /* 473 * Memory Configuration 5 Register 474 */ 475 /* Address remap region 2 */ 476 #define TX39_MEMCONFIG5_STARTVAL2_SHIFT 9 477 #define TX39_MEMCONFIG5_STARTVAL2_MASK 0x007fffff 478 #define TX39_MEMCONFIG5_STARTVAL2(cr) \ 479 (((cr) >> TX39_MEMCONFIG5_STARTVAL2_SHIFT) & \ 480 TX39_MEMCONFIG5_STARTVAL2_MASK) 481 #define TX39_MEMCONFIG5_STARTVAL2_SET(cr, val) \ 482 ((cr) | (((val) << TX39_MEMCONFIG5_STARTVAL2_SHIFT) & \ 483 (TX39_MEMCONFIG5_STARTVAL2_MASK << TX39_MEMCONFIG5_STARTVAL2_SHIFT))) 484 485 #define TX39_MEMCONFIG5_MASK2_SHIFT 0 486 #define TX39_MEMCONFIG5_MASK2_MASK 0xf 487 #define TX39_MEMCONFIG5_MASK2(cr) \ 488 (((cr) >> TX39_MEMCONFIG5_MASK2_SHIFT) & \ 489 TX39_MEMCONFIG5_MASK2_MASK) 490 #define TX39_MEMCONFIG5_MASK2_SET(cr, val) \ 491 ((cr) | (((val) << TX39_MEMCONFIG5_MASK2_SHIFT) & \ 492 (TX39_MEMCONFIG5_MASK2_MASK << TX39_MEMCONFIG5_MASK2_SHIFT))) 493 494 /* 495 * Memory Configuration 6 Register 496 */ 497 /* Address remap region 1 */ 498 #define TX39_MEMCONFIG6_STARTVAL1_SHIFT 9 499 #define TX39_MEMCONFIG6_STARTVAL1_MASK 0x007fffff 500 #define TX39_MEMCONFIG6_STARTVAL1(cr) \ 501 (((cr) >> TX39_MEMCONFIG6_STARTVAL1_SHIFT) & \ 502 TX39_MEMCONFIG6_STARTVAL1_MASK) 503 #define TX39_MEMCONFIG6_STARTVAL1_SET(cr, val) \ 504 ((cr) | (((val) << TX39_MEMCONFIG6_STARTVAL1_SHIFT) & \ 505 (TX39_MEMCONFIG6_STARTVAL1_MASK << TX39_MEMCONFIG6_STARTVAL1_SHIFT))) 506 507 #define TX39_MEMCONFIG6_MASK1_SHIFT 0 508 #define TX39_MEMCONFIG6_MASK1_MASK 0xf 509 #define TX39_MEMCONFIG6_MASK1(cr) \ 510 (((cr) >> TX39_MEMCONFIG6_MASK1_SHIFT) & \ 511 TX39_MEMCONFIG6_MASK1_MASK) 512 #define TX39_MEMCONFIG6_MASK1_SET(cr, val) \ 513 ((cr) | (((val) << TX39_MEMCONFIG6_MASK1_SHIFT) & \ 514 (TX39_MEMCONFIG6_MASK1_MASK << TX39_MEMCONFIG6_MASK1_SHIFT))) 515 516 /* 517 * Memory Configuration 7 Register 518 */ 519 /* Address remap region 2 */ 520 #define TX39_MEMCONFIG7_RMAPADD2_SHIFT 9 521 #define TX39_MEMCONFIG7_RMAPADD2_MASK 0x007fffff 522 #define TX39_MEMCONFIG7_RMAPADD2(cr) \ 523 (((cr) >> TX39_MEMCONFIG7_RMAPADD2_SHIFT) & \ 524 TX39_MEMCONFIG7_RMAPADD2_MASK) 525 #define TX39_MEMCONFIG7_RMAPADD2_SET(cr, val) \ 526 ((cr) | (((val) << TX39_MEMCONFIG7_RMAPADD2_SHIFT) & \ 527 (TX39_MEMCONFIG7_RMAPADD2_MASK << TX39_MEMCONFIG7_RMAPADD2_SHIFT))) 528 529 /* 530 * Memory Configuration 8 Register 531 */ 532 /* Address remap region 1 */ 533 #define TX39_MEMCONFIG8_RMAPADD1_SHIFT 9 534 #define TX39_MEMCONFIG8_RMAPADD1_MASK 0x007fffff 535 #define TX39_MEMCONFIG8_RMAPADD1(cr) \ 536 (((cr) >> TX39_MEMCONFIG8_RMAPADD1_SHIFT) & \ 537 TX39_MEMCONFIG8_RMAPADD1_MASK) 538 #define TX39_MEMCONFIG8_RMAPADD1_SET(cr, val) \ 539 ((cr) | (((val) << TX39_MEMCONFIG8_RMAPADD1_SHIFT) & \ 540 (TX39_MEMCONFIG8_RMAPADD1_MASK << TX39_MEMCONFIG8_RMAPADD1_SHIFT))) 541
Indexes created Wed Nov 05 01:09:58 GMT 2025