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tx39clock.c revision 1.4.2.2
      1  1.4.2.2  wrstuden /*	$NetBSD: tx39clock.c,v 1.4.2.2 1999/12/27 18:32:11 wrstuden Exp $ */
      2  1.4.2.2  wrstuden 
      3  1.4.2.2  wrstuden /*
      4  1.4.2.2  wrstuden  * Copyright (c) 1999, by UCHIYAMA Yasushi
      5  1.4.2.2  wrstuden  * All rights reserved.
      6  1.4.2.2  wrstuden  *
      7  1.4.2.2  wrstuden  * Redistribution and use in source and binary forms, with or without
      8  1.4.2.2  wrstuden  * modification, are permitted provided that the following conditions
      9  1.4.2.2  wrstuden  * are met:
     10  1.4.2.2  wrstuden  * 1. Redistributions of source code must retain the above copyright
     11  1.4.2.2  wrstuden  *    notice, this list of conditions and the following disclaimer.
     12  1.4.2.2  wrstuden  * 2. The name of the developer may NOT be used to endorse or promote products
     13  1.4.2.2  wrstuden  *    derived from this software without specific prior written permission.
     14  1.4.2.2  wrstuden  *
     15  1.4.2.2  wrstuden  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     16  1.4.2.2  wrstuden  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     17  1.4.2.2  wrstuden  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     18  1.4.2.2  wrstuden  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     19  1.4.2.2  wrstuden  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     20  1.4.2.2  wrstuden  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     21  1.4.2.2  wrstuden  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  1.4.2.2  wrstuden  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     23  1.4.2.2  wrstuden  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     24  1.4.2.2  wrstuden  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     25  1.4.2.2  wrstuden  * SUCH DAMAGE.
     26  1.4.2.2  wrstuden  *
     27  1.4.2.2  wrstuden  */
     28  1.4.2.2  wrstuden #include "opt_tx39_debug.h"
     29  1.4.2.2  wrstuden 
     30  1.4.2.2  wrstuden #include <sys/param.h>
     31  1.4.2.2  wrstuden #include <sys/systm.h>
     32  1.4.2.2  wrstuden #include <sys/device.h>
     33  1.4.2.2  wrstuden 
     34  1.4.2.2  wrstuden #include <machine/bus.h>
     35  1.4.2.2  wrstuden #include <machine/clock_machdep.h>
     36  1.4.2.2  wrstuden #include <machine/cpu.h>
     37  1.4.2.2  wrstuden 
     38  1.4.2.2  wrstuden #include <hpcmips/tx/tx39var.h>
     39  1.4.2.2  wrstuden #include <hpcmips/tx/tx39icureg.h> /* XXX */
     40  1.4.2.2  wrstuden #include <hpcmips/tx/tx39clockreg.h>
     41  1.4.2.2  wrstuden #include <hpcmips/tx/tx39timerreg.h>
     42  1.4.2.2  wrstuden #include <dev/dec/clockvar.h>
     43  1.4.2.2  wrstuden 
     44  1.4.2.2  wrstuden #define ISSETPRINT(r, m) __is_set_print(r, TX39_CLOCK_EN##m##CLK, #m)
     45  1.4.2.2  wrstuden 
     46  1.4.2.2  wrstuden void	clock_init __P((struct device*));
     47  1.4.2.2  wrstuden void	clock_get __P((struct device*, time_t, struct clocktime*));
     48  1.4.2.2  wrstuden void	clock_set __P((struct device*, struct clocktime*));
     49  1.4.2.2  wrstuden 
     50  1.4.2.2  wrstuden static const struct clockfns clockfns = {
     51  1.4.2.2  wrstuden 	clock_init, clock_get, clock_set,
     52  1.4.2.2  wrstuden };
     53  1.4.2.2  wrstuden 
     54  1.4.2.2  wrstuden int	tx39clock_match __P((struct device*, struct cfdata*, void*));
     55  1.4.2.2  wrstuden void	tx39clock_attach __P((struct device*, struct device*, void*));
     56  1.4.2.2  wrstuden void	tx39clock_dump __P((tx_chipset_tag_t));
     57  1.4.2.2  wrstuden 
     58  1.4.2.2  wrstuden void	tx39timer_freeze __P((tx_chipset_tag_t));
     59  1.4.2.2  wrstuden void	tx39timer_rtcreset __P((tx_chipset_tag_t));
     60  1.4.2.2  wrstuden 
     61  1.4.2.2  wrstuden struct tx39clock_softc {
     62  1.4.2.2  wrstuden 	struct	device sc_dev;
     63  1.4.2.2  wrstuden 	tx_chipset_tag_t sc_tc;
     64  1.4.2.2  wrstuden };
     65  1.4.2.2  wrstuden 
     66  1.4.2.2  wrstuden struct cfattach tx39clock_ca = {
     67  1.4.2.2  wrstuden 	sizeof(struct tx39clock_softc), tx39clock_match, tx39clock_attach
     68  1.4.2.2  wrstuden };
     69  1.4.2.2  wrstuden 
     70  1.4.2.2  wrstuden int
     71  1.4.2.2  wrstuden tx39clock_match(parent, cf, aux)
     72  1.4.2.2  wrstuden 	struct device *parent;
     73  1.4.2.2  wrstuden 	struct cfdata *cf;
     74  1.4.2.2  wrstuden 	void *aux;
     75  1.4.2.2  wrstuden {
     76  1.4.2.2  wrstuden 	return 2; /* 1st attach group of txsim */
     77  1.4.2.2  wrstuden }
     78  1.4.2.2  wrstuden 
     79  1.4.2.2  wrstuden void
     80  1.4.2.2  wrstuden tx39clock_attach(parent, self, aux)
     81  1.4.2.2  wrstuden 	struct device *parent;
     82  1.4.2.2  wrstuden 	struct device *self;
     83  1.4.2.2  wrstuden 	void *aux;
     84  1.4.2.2  wrstuden {
     85  1.4.2.2  wrstuden 	struct txsim_attach_args *ta = aux;
     86  1.4.2.2  wrstuden 	struct tx39clock_softc *sc = (void*)self;
     87  1.4.2.2  wrstuden 	tx_chipset_tag_t tc;
     88  1.4.2.2  wrstuden 	txreg_t reg;
     89  1.4.2.2  wrstuden 
     90  1.4.2.2  wrstuden 	tc = sc->sc_tc = ta->ta_tc;
     91  1.4.2.2  wrstuden 
     92  1.4.2.2  wrstuden 	/*
     93  1.4.2.2  wrstuden 	 *	Enable periodic timer
     94  1.4.2.2  wrstuden 	 *	 but interrupt don't arise yet. see clock_init().
     95  1.4.2.2  wrstuden 	 */
     96  1.4.2.2  wrstuden 	reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);
     97  1.4.2.2  wrstuden 	reg |= TX39_TIMERCONTROL_ENPERTIMER;
     98  1.4.2.2  wrstuden 	tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
     99  1.4.2.2  wrstuden 
    100  1.4.2.2  wrstuden 	/* Set counter */
    101  1.4.2.2  wrstuden #if 0
    102  1.4.2.2  wrstuden 	{
    103  1.4.2.2  wrstuden 		int cnt = 0xffff; /* XXX the most slower. */
    104  1.4.2.2  wrstuden 		reg = tx_conf_read(tc, TX39_TIMERPERIODIC_REG);
    105  1.4.2.2  wrstuden 		reg = TX39_TIMERPERIODIC_PERVAL_SET(reg, cnt);
    106  1.4.2.2  wrstuden 		tx_conf_write(tc, TX39_TIMERPERIODIC_REG, reg);
    107  1.4.2.2  wrstuden 	}
    108  1.4.2.2  wrstuden #endif
    109  1.4.2.2  wrstuden 	clockattach(self, &clockfns);
    110  1.4.2.2  wrstuden 
    111  1.4.2.2  wrstuden #ifdef TX39CLKDEBUG
    112  1.4.2.2  wrstuden 	tx39clock_dump(tc);
    113  1.4.2.2  wrstuden #endif /* TX39CLKDEBUG */
    114  1.4.2.2  wrstuden }
    115  1.4.2.2  wrstuden 
    116  1.4.2.2  wrstuden /*
    117  1.4.2.2  wrstuden  * RTC and ALARM
    118  1.4.2.2  wrstuden  *    RTCINT    ... INTR5 bit 31  (roll over)
    119  1.4.2.2  wrstuden  *    ALARMINT  ... INTR5 bit 30
    120  1.4.2.2  wrstuden  *    PERINT    ... INTR5 bit 29
    121  1.4.2.2  wrstuden  */
    122  1.4.2.2  wrstuden void
    123  1.4.2.2  wrstuden tx39timer_freeze(tc)
    124  1.4.2.2  wrstuden 	tx_chipset_tag_t tc;
    125  1.4.2.2  wrstuden {
    126  1.4.2.2  wrstuden 	txreg_t reg;
    127  1.4.2.2  wrstuden 
    128  1.4.2.2  wrstuden 	reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);
    129  1.4.2.2  wrstuden 	/* Freeze RTC */
    130  1.4.2.2  wrstuden 	reg |= TX39_TIMERCONTROL_FREEZEPRE; /* Upper 8bit */
    131  1.4.2.2  wrstuden 	reg |= TX39_TIMERCONTROL_FREEZERTC; /* Lower 32bit */
    132  1.4.2.2  wrstuden 	/* Freeze periodic timer */
    133  1.4.2.2  wrstuden 	reg |= TX39_TIMERCONTROL_FREEZETIMER;
    134  1.4.2.2  wrstuden 	reg &= ~TX39_TIMERCONTROL_ENPERTIMER;
    135  1.4.2.2  wrstuden 	tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
    136  1.4.2.2  wrstuden }
    137  1.4.2.2  wrstuden 
    138  1.4.2.2  wrstuden void
    139  1.4.2.2  wrstuden tx39timer_rtcreset(tc)
    140  1.4.2.2  wrstuden  	tx_chipset_tag_t tc;
    141  1.4.2.2  wrstuden {
    142  1.4.2.2  wrstuden 	txreg_t reg;
    143  1.4.2.2  wrstuden 
    144  1.4.2.2  wrstuden 	reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);
    145  1.4.2.2  wrstuden 	/* Reset counter and stop */
    146  1.4.2.2  wrstuden 	reg |= TX39_TIMERCONTROL_RTCCLR;
    147  1.4.2.2  wrstuden 	tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
    148  1.4.2.2  wrstuden 	/* Count again */
    149  1.4.2.2  wrstuden 	reg &= ~TX39_TIMERCONTROL_RTCCLR;
    150  1.4.2.2  wrstuden 	tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
    151  1.4.2.2  wrstuden }
    152  1.4.2.2  wrstuden 
    153  1.4.2.2  wrstuden void
    154  1.4.2.2  wrstuden clock_init(dev)
    155  1.4.2.2  wrstuden 	struct device *dev;
    156  1.4.2.2  wrstuden {
    157  1.4.2.2  wrstuden 	tx_chipset_tag_t tc;
    158  1.4.2.2  wrstuden 	txreg_t reg;
    159  1.4.2.2  wrstuden 
    160  1.4.2.2  wrstuden 	tc = tx_conf_get_tag();
    161  1.4.2.2  wrstuden 	/* Enable periodic timer */
    162  1.4.2.2  wrstuden 	reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);
    163  1.4.2.2  wrstuden 	reg |= TX39_INTRPRI13_TIMER_PERIODIC_BIT;
    164  1.4.2.2  wrstuden 	tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);
    165  1.4.2.2  wrstuden 
    166  1.4.2.2  wrstuden }
    167  1.4.2.2  wrstuden 
    168  1.4.2.2  wrstuden void
    169  1.4.2.2  wrstuden clock_get(dev, base, ct)
    170  1.4.2.2  wrstuden 	struct device *dev;
    171  1.4.2.2  wrstuden 	time_t base;
    172  1.4.2.2  wrstuden 	struct clocktime *ct;
    173  1.4.2.2  wrstuden {
    174  1.4.2.2  wrstuden 	tx_chipset_tag_t tc;
    175  1.4.2.2  wrstuden 	txreg_t reghi, reglo, oreghi, oreglo;
    176  1.4.2.2  wrstuden 	int i;
    177  1.4.2.2  wrstuden 
    178  1.4.2.2  wrstuden 	tc = tx_conf_get_tag();
    179  1.4.2.2  wrstuden 	i = 10;
    180  1.4.2.2  wrstuden 	do {
    181  1.4.2.2  wrstuden 		reghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG);
    182  1.4.2.2  wrstuden 		reglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG);
    183  1.4.2.2  wrstuden 		oreghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG);
    184  1.4.2.2  wrstuden 		oreglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG);
    185  1.4.2.2  wrstuden 	} while ((reghi != oreghi || reglo != oreglo) && (--i > 0));
    186  1.4.2.2  wrstuden 	if (i < 0) {
    187  1.4.2.2  wrstuden 		panic("RTC timer read error.\n");
    188  1.4.2.2  wrstuden 	}
    189  1.4.2.2  wrstuden 	/* XXX not coded yet */
    190  1.4.2.2  wrstuden }
    191  1.4.2.2  wrstuden 
    192  1.4.2.2  wrstuden void
    193  1.4.2.2  wrstuden clock_set(dev, ct)
    194  1.4.2.2  wrstuden 	struct device *dev;
    195  1.4.2.2  wrstuden 	struct clocktime *ct;
    196  1.4.2.2  wrstuden {
    197  1.4.2.2  wrstuden 	/* XXX not coded yet */
    198  1.4.2.2  wrstuden }
    199  1.4.2.2  wrstuden 
    200  1.4.2.2  wrstuden void
    201  1.4.2.2  wrstuden tx39clock_dump(tc)
    202  1.4.2.2  wrstuden 	tx_chipset_tag_t tc;
    203  1.4.2.2  wrstuden {
    204  1.4.2.2  wrstuden 	txreg_t reg;
    205  1.4.2.2  wrstuden 
    206  1.4.2.2  wrstuden 	reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);
    207  1.4.2.2  wrstuden 	printf(" ");
    208  1.4.2.2  wrstuden 	ISSETPRINT(reg, CHIM);
    209  1.4.2.2  wrstuden #ifdef TX391X
    210  1.4.2.2  wrstuden 	ISSETPRINT(reg, VID);
    211  1.4.2.2  wrstuden 	ISSETPRINT(reg, MBUS);
    212  1.4.2.2  wrstuden #endif /* TX391X */
    213  1.4.2.2  wrstuden #ifdef TX392X
    214  1.4.2.2  wrstuden 	ISSETPRINT(reg, IRDA);
    215  1.4.2.2  wrstuden #endif /* TX392X */
    216  1.4.2.2  wrstuden 	ISSETPRINT(reg, SPI);
    217  1.4.2.2  wrstuden 	ISSETPRINT(reg, TIMER);
    218  1.4.2.2  wrstuden 	ISSETPRINT(reg, FASTTIMER);
    219  1.4.2.2  wrstuden #ifdef TX392X
    220  1.4.2.2  wrstuden 	ISSETPRINT(reg, C48MOUT);
    221  1.4.2.2  wrstuden #endif /* TX392X */
    222  1.4.2.2  wrstuden 	ISSETPRINT(reg, SIBM);
    223  1.4.2.2  wrstuden 	ISSETPRINT(reg, CSER);
    224  1.4.2.2  wrstuden 	ISSETPRINT(reg, IR);
    225  1.4.2.2  wrstuden 	ISSETPRINT(reg, UARTA);
    226  1.4.2.2  wrstuden 	ISSETPRINT(reg, UARTB);
    227  1.4.2.2  wrstuden 	printf("\n");
    228  1.4.2.2  wrstuden }
    229  1.4.2.2  wrstuden 
    230  1.4.2.2  wrstuden 
    231  1.4.2.2  wrstuden 
    232  1.4.2.2  wrstuden 
    233