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tx39clock.c revision 1.10 
      1 /*	$NetBSD: tx39clock.c,v 1.10 2001/09/18 17:37:28 uch Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 1999-2001 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by UCHIYAMA Yasushi.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *        This product includes software developed by the NetBSD
     21  *        Foundation, Inc. and its contributors.
     22  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  *    contributors may be used to endorse or promote products derived
     24  *    from this software without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  * POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 
     39 #include "opt_tx39_debug.h"
     40 
     41 #include <sys/param.h>
     42 #include <sys/systm.h>
     43 
     44 #include <dev/clock_subr.h>
     45 
     46 #include <machine/bus.h>
     47 #include <machine/sysconf.h>
     48 
     49 #include <hpcmips/tx/tx39var.h>
     50 #include <hpcmips/tx/tx39icureg.h>
     51 #include <hpcmips/tx/tx39clockvar.h>
     52 #include <hpcmips/tx/tx39clockreg.h>
     53 #include <hpcmips/tx/tx39timerreg.h>
     54 
     55 #ifdef TX39CLKDEBUG
     56 #define	DPRINTF(arg)	printf arg
     57 #else
     58 #define	DPRINTF(arg)	((void)0)
     59 #endif
     60 
     61 #define ISSETPRINT(r, m)	__is_set_print(r, TX39_CLOCK_EN ## m ## CLK, #m)
     62 
     63 void	tx39clock_init(struct device *);
     64 void	tx39clock_get(struct device *, time_t, struct clock_ymdhms *);
     65 void	tx39clock_set(struct device *, struct clock_ymdhms *);
     66 
     67 struct platform_clock tx39_clock = {
     68 #define CLOCK_RATE	100
     69 	CLOCK_RATE, tx39clock_init, tx39clock_get, tx39clock_set,
     70 };
     71 
     72 struct txtime {
     73 	u_int32_t t_hi;
     74 	u_int32_t t_lo;
     75 };
     76 
     77 struct tx39clock_softc {
     78 	struct	device sc_dev;
     79 	tx_chipset_tag_t sc_tc;
     80 
     81 	int sc_alarm;
     82 	int sc_enabled;
     83 	int sc_year;
     84 	struct clock_ymdhms sc_epoch;
     85 };
     86 
     87 int	tx39clock_match(struct device *, struct cfdata *, void *);
     88 void	tx39clock_attach(struct device *, struct device *, void *);
     89 void	tx39clock_dump(tx_chipset_tag_t);
     90 
     91 void	tx39clock_cpuspeed(int *, int *);
     92 
     93 void	__tx39timer_rtcfreeze(tx_chipset_tag_t);
     94 void	__tx39timer_rtcreset(tx_chipset_tag_t);
     95 __inline__ void	__tx39timer_rtcget(struct txtime *);
     96 __inline__ time_t __tx39timer_rtc2sec(struct txtime *);
     97 
     98 struct cfattach tx39clock_ca = {
     99 	sizeof(struct tx39clock_softc), tx39clock_match, tx39clock_attach
    100 };
    101 
    102 int
    103 tx39clock_match(struct device *parent, struct cfdata *cf, void *aux)
    104 {
    105 
    106 	return (ATTACH_FIRST);
    107 }
    108 
    109 void
    110 tx39clock_attach(struct device *parent, struct device *self, void *aux)
    111 {
    112 	struct txsim_attach_args *ta = aux;
    113 	struct tx39clock_softc *sc = (void*)self;
    114 	tx_chipset_tag_t tc;
    115 	txreg_t reg;
    116 
    117 	tc = sc->sc_tc = ta->ta_tc;
    118 	tx_conf_register_clock(tc, self);
    119 
    120 	/* Reset timer module */
    121 	tx_conf_write(tc, TX39_TIMERCONTROL_REG, 0);
    122 
    123 	/* Enable periodic timer */
    124 	reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);
    125 	reg |= TX39_TIMERCONTROL_ENPERTIMER;
    126 	tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
    127 
    128 	sc->sc_enabled = 0;
    129 	/*
    130 	 * RTC and ALARM
    131 	 *    RTCINT    ... INTR5 bit 31  (roll over)
    132 	 *    ALARMINT  ... INTR5 bit 30
    133 	 *    PERINT    ... INTR5 bit 29
    134 	 */
    135 
    136 	platform_clock_attach(self, &tx39_clock);
    137 
    138 #ifdef TX39CLKDEBUG
    139 	tx39clock_dump(tc);
    140 #endif /* TX39CLKDEBUG */
    141 }
    142 
    143 /*
    144  * cpuclock ... CPU clock (Hz)
    145  * cpuspeed ... instructions-per-microsecond
    146  */
    147 void
    148 tx39clock_cpuspeed(int *cpuclock, int *cpuspeed)
    149 {
    150 	struct txtime t0, t1;
    151 	int elapsed;
    152 
    153 	__tx39timer_rtcget(&t0);
    154 	__asm__ __volatile__("
    155 		.set	noreorder;
    156 		li	$8, 10000000;
    157 	1:	nop;
    158 		nop;
    159 		nop;
    160 		nop;
    161 		nop;
    162 		nop;
    163 		nop;
    164 		add	$8, $8, -1;
    165 		bnez	$8, 1b;
    166 		nop;
    167 		.set	reorder;
    168 	");
    169 	__tx39timer_rtcget(&t1);
    170 
    171 	elapsed = t1.t_lo - t0.t_lo;
    172 
    173 	*cpuclock = (100000000 / elapsed) * TX39_RTCLOCK;
    174 	*cpuspeed = *cpuclock / 1000000;
    175 }
    176 
    177 void
    178 __tx39timer_rtcfreeze(tx_chipset_tag_t tc)
    179 {
    180 	txreg_t reg;
    181 
    182 	reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);
    183 
    184 	/* Freeze RTC */
    185 	reg |= TX39_TIMERCONTROL_FREEZEPRE; /* Upper 8bit */
    186 	reg |= TX39_TIMERCONTROL_FREEZERTC; /* Lower 32bit */
    187 
    188 	/* Freeze periodic timer */
    189 	reg |= TX39_TIMERCONTROL_FREEZETIMER;
    190 	reg &= ~TX39_TIMERCONTROL_ENPERTIMER;
    191 	tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
    192 }
    193 
    194 __inline__ time_t
    195 __tx39timer_rtc2sec(struct txtime *t)
    196 {
    197 	/* This rely on RTC is 32.768kHz */
    198 	return ((t->t_lo >> 15) | (t->t_hi << 17));
    199 }
    200 
    201 __inline__ void
    202 __tx39timer_rtcget(struct txtime *t)
    203 {
    204 	tx_chipset_tag_t tc;
    205 	txreg_t reghi, reglo, oreghi, oreglo;
    206 	int retry;
    207 
    208 	tc = tx_conf_get_tag();
    209 
    210 	retry = 10;
    211 
    212 	do {
    213 		oreglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG);
    214 		reglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG);
    215 
    216 		oreghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG);
    217 		reghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG);
    218 	} while ((reghi != oreghi || reglo != oreglo) && (--retry > 0));
    219 
    220 	if (retry < 0) {
    221 		printf("RTC timer read error.\n");
    222 	}
    223 
    224 	t->t_hi = TX39_TIMERRTCHI(reghi);
    225 	t->t_lo = reglo;
    226 }
    227 
    228 void
    229 __tx39timer_rtcreset(tx_chipset_tag_t tc)
    230 {
    231 	txreg_t reg;
    232 
    233 	reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);
    234 
    235 	/* Reset counter and stop */
    236 	reg |= TX39_TIMERCONTROL_RTCCLR;
    237 	tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
    238 
    239 	/* Count again */
    240 	reg &= ~TX39_TIMERCONTROL_RTCCLR;
    241 	tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
    242 }
    243 
    244 void
    245 tx39clock_init(struct device *dev)
    246 {
    247 	struct tx39clock_softc *sc = (void*)dev;
    248 	tx_chipset_tag_t tc = sc->sc_tc;
    249 	txreg_t reg;
    250 	int pcnt;
    251 
    252 	/*
    253 	 * Setup periodic timer (interrupting hz times per second.)
    254 	 */
    255 	pcnt = TX39_TIMERCLK / CLOCK_RATE - 1;
    256 	reg = tx_conf_read(tc, TX39_TIMERPERIODIC_REG);
    257 	TX39_TIMERPERIODIC_PERVAL_CLR(reg);
    258 	reg = TX39_TIMERPERIODIC_PERVAL_SET(reg, pcnt);
    259 	tx_conf_write(tc, TX39_TIMERPERIODIC_REG, reg);
    260 
    261 	/*
    262 	 * Enable periodic timer
    263 	 */
    264 	reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);
    265 	reg |= TX39_INTRPRI13_TIMER_PERIODIC_BIT;
    266 	tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);
    267 }
    268 
    269 void
    270 tx39clock_get(struct device *dev, time_t base, struct clock_ymdhms *t)
    271 {
    272 	struct tx39clock_softc *sc = (void *)dev;
    273 	struct clock_ymdhms dt;
    274 	struct txtime tt;
    275 	time_t sec;
    276 
    277 	__tx39timer_rtcget(&tt);
    278 	sec = __tx39timer_rtc2sec(&tt);
    279 
    280 	if (!sc->sc_enabled) {
    281 		DPRINTF(("bootstrap: %d sec from previous reboot\n",
    282 		    (int)sec));
    283 
    284 		sc->sc_enabled = 1;
    285 		base += sec;
    286 	} else {
    287 		dt.dt_year = sc->sc_year;
    288 		dt.dt_mon = sc->sc_epoch.dt_mon;
    289 		dt.dt_day = sc->sc_epoch.dt_day;
    290 		dt.dt_hour = sc->sc_epoch.dt_hour;
    291 		dt.dt_min = sc->sc_epoch.dt_min;
    292 		dt.dt_sec = sc->sc_epoch.dt_sec;
    293 		dt.dt_wday = sc->sc_epoch.dt_wday;
    294 		base = sec + clock_ymdhms_to_secs(&dt);
    295 	}
    296 
    297 	clock_secs_to_ymdhms(base, &dt);
    298 
    299 	t->dt_year = dt.dt_year % 100;
    300 	t->dt_mon = dt.dt_mon;
    301 	t->dt_day = dt.dt_day;
    302 	t->dt_hour = dt.dt_hour;
    303 	t->dt_min = dt.dt_min;
    304 	t->dt_sec = dt.dt_sec;
    305 	t->dt_wday = dt.dt_wday;
    306 
    307 	sc->sc_year = dt.dt_year;
    308 }
    309 
    310 void
    311 tx39clock_set(struct device *dev, struct clock_ymdhms *dt)
    312 {
    313 	struct tx39clock_softc *sc = (void *)dev;
    314 
    315 	if (sc->sc_enabled) {
    316 		sc->sc_epoch = *dt;
    317 	}
    318 }
    319 
    320 int
    321 tx39clock_alarm_set(tx_chipset_tag_t tc, int msec)
    322 {
    323 	struct tx39clock_softc *sc = tc->tc_clockt;
    324 
    325 	sc->sc_alarm = TX39_MSEC2RTC(msec);
    326 	tx39clock_alarm_refill(tc);
    327 
    328 	return (0);
    329 }
    330 
    331 void
    332 tx39clock_alarm_refill(tx_chipset_tag_t tc)
    333 {
    334 	struct tx39clock_softc *sc = tc->tc_clockt;
    335 	struct txtime t;
    336 	u_int64_t time;
    337 
    338 	__tx39timer_rtcget(&t);
    339 
    340 	time = ((u_int64_t)t.t_hi << 32) | (u_int64_t)t.t_lo;
    341 	time += (u_int64_t)sc->sc_alarm;
    342 
    343 	t.t_hi = (u_int32_t)((time >> 32) & TX39_TIMERALARMHI_MASK);
    344 	t.t_lo = (u_int32_t)(time & 0xffffffff);
    345 
    346 	tx_conf_write(tc, TX39_TIMERALARMHI_REG, t.t_hi);
    347 	tx_conf_write(tc, TX39_TIMERALARMLO_REG, t.t_lo);
    348 }
    349 
    350 void
    351 tx39clock_dump(tx_chipset_tag_t tc)
    352 {
    353 	txreg_t reg;
    354 
    355 	reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);
    356 
    357 	printf(" ");
    358 	ISSETPRINT(reg, CHIM);
    359 #ifdef TX391X
    360 	ISSETPRINT(reg, VID);
    361 	ISSETPRINT(reg, MBUS);
    362 #endif /* TX391X */
    363 #ifdef TX392X
    364 	ISSETPRINT(reg, IRDA);
    365 #endif /* TX392X */
    366 	ISSETPRINT(reg, SPI);
    367 	ISSETPRINT(reg, TIMER);
    368 	ISSETPRINT(reg, FASTTIMER);
    369 #ifdef TX392X
    370 	ISSETPRINT(reg, C48MOUT);
    371 #endif /* TX392X */
    372 	ISSETPRINT(reg, SIBM);
    373 	ISSETPRINT(reg, CSER);
    374 	ISSETPRINT(reg, IR);
    375 	ISSETPRINT(reg, UARTA);
    376 	ISSETPRINT(reg, UARTB);
    377 	printf("\n");
    378 }
    379