tx39clock.c revision 1.11
1 /* $NetBSD: tx39clock.c,v 1.11 2002/01/29 18:53:15 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_tx39clock_debug.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 44 #include <dev/clock_subr.h> 45 46 #include <machine/bus.h> 47 #include <machine/sysconf.h> 48 49 #include <hpcmips/tx/tx39var.h> 50 #include <hpcmips/tx/tx39icureg.h> 51 #include <hpcmips/tx/tx39clockvar.h> 52 #include <hpcmips/tx/tx39clockreg.h> 53 #include <hpcmips/tx/tx39timerreg.h> 54 55 #ifdef TX39CLOCK_DEBUG 56 #define DPRINTF_ENABLE 57 #define DPRINTF_DEBUG tx39clock_debug 58 #endif 59 #include <machine/debug.h> 60 61 #define ISSETPRINT(r, m) \ 62 dbg_bitmask_print(r, TX39_CLOCK_EN ## m ## CLK, #m) 63 64 void tx39clock_init(struct device *); 65 void tx39clock_get(struct device *, time_t, struct clock_ymdhms *); 66 void tx39clock_set(struct device *, struct clock_ymdhms *); 67 68 struct platform_clock tx39_clock = { 69 #define CLOCK_RATE 100 70 CLOCK_RATE, tx39clock_init, tx39clock_get, tx39clock_set, 71 }; 72 73 struct txtime { 74 u_int32_t t_hi; 75 u_int32_t t_lo; 76 }; 77 78 struct tx39clock_softc { 79 struct device sc_dev; 80 tx_chipset_tag_t sc_tc; 81 82 int sc_alarm; 83 int sc_enabled; 84 int sc_year; 85 struct clock_ymdhms sc_epoch; 86 }; 87 88 int tx39clock_match(struct device *, struct cfdata *, void *); 89 void tx39clock_attach(struct device *, struct device *, void *); 90 #ifdef TX39CLOCK_DEBUG 91 void tx39clock_dump(tx_chipset_tag_t); 92 #endif 93 94 void tx39clock_cpuspeed(int *, int *); 95 96 void __tx39timer_rtcfreeze(tx_chipset_tag_t); 97 void __tx39timer_rtcreset(tx_chipset_tag_t); 98 __inline__ void __tx39timer_rtcget(struct txtime *); 99 __inline__ time_t __tx39timer_rtc2sec(struct txtime *); 100 101 struct cfattach tx39clock_ca = { 102 sizeof(struct tx39clock_softc), tx39clock_match, tx39clock_attach 103 }; 104 105 int 106 tx39clock_match(struct device *parent, struct cfdata *cf, void *aux) 107 { 108 109 return (ATTACH_FIRST); 110 } 111 112 void 113 tx39clock_attach(struct device *parent, struct device *self, void *aux) 114 { 115 struct txsim_attach_args *ta = aux; 116 struct tx39clock_softc *sc = (void*)self; 117 tx_chipset_tag_t tc; 118 txreg_t reg; 119 120 tc = sc->sc_tc = ta->ta_tc; 121 tx_conf_register_clock(tc, self); 122 123 /* Reset timer module */ 124 tx_conf_write(tc, TX39_TIMERCONTROL_REG, 0); 125 126 /* Enable periodic timer */ 127 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 128 reg |= TX39_TIMERCONTROL_ENPERTIMER; 129 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 130 131 sc->sc_enabled = 0; 132 /* 133 * RTC and ALARM 134 * RTCINT ... INTR5 bit 31 (roll over) 135 * ALARMINT ... INTR5 bit 30 136 * PERINT ... INTR5 bit 29 137 */ 138 139 platform_clock_attach(self, &tx39_clock); 140 141 #ifdef TX39CLOCK_DEBUG 142 tx39clock_dump(tc); 143 #endif /* TX39CLOCK_DEBUG */ 144 } 145 146 /* 147 * cpuclock ... CPU clock (Hz) 148 * cpuspeed ... instructions-per-microsecond 149 */ 150 void 151 tx39clock_cpuspeed(int *cpuclock, int *cpuspeed) 152 { 153 struct txtime t0, t1; 154 int elapsed; 155 156 __tx39timer_rtcget(&t0); 157 __asm__ __volatile__(" 158 .set noreorder; 159 li $8, 10000000; 160 1: nop; 161 nop; 162 nop; 163 nop; 164 nop; 165 nop; 166 nop; 167 add $8, $8, -1; 168 bnez $8, 1b; 169 nop; 170 .set reorder; 171 "); 172 __tx39timer_rtcget(&t1); 173 174 elapsed = t1.t_lo - t0.t_lo; 175 176 *cpuclock = (100000000 / elapsed) * TX39_RTCLOCK; 177 *cpuspeed = *cpuclock / 1000000; 178 } 179 180 void 181 __tx39timer_rtcfreeze(tx_chipset_tag_t tc) 182 { 183 txreg_t reg; 184 185 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 186 187 /* Freeze RTC */ 188 reg |= TX39_TIMERCONTROL_FREEZEPRE; /* Upper 8bit */ 189 reg |= TX39_TIMERCONTROL_FREEZERTC; /* Lower 32bit */ 190 191 /* Freeze periodic timer */ 192 reg |= TX39_TIMERCONTROL_FREEZETIMER; 193 reg &= ~TX39_TIMERCONTROL_ENPERTIMER; 194 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 195 } 196 197 __inline__ time_t 198 __tx39timer_rtc2sec(struct txtime *t) 199 { 200 /* This rely on RTC is 32.768kHz */ 201 return ((t->t_lo >> 15) | (t->t_hi << 17)); 202 } 203 204 __inline__ void 205 __tx39timer_rtcget(struct txtime *t) 206 { 207 tx_chipset_tag_t tc; 208 txreg_t reghi, reglo, oreghi, oreglo; 209 int retry; 210 211 tc = tx_conf_get_tag(); 212 213 retry = 10; 214 215 do { 216 oreglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG); 217 reglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG); 218 219 oreghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG); 220 reghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG); 221 } while ((reghi != oreghi || reglo != oreglo) && (--retry > 0)); 222 223 if (retry < 0) { 224 printf("RTC timer read error.\n"); 225 } 226 227 t->t_hi = TX39_TIMERRTCHI(reghi); 228 t->t_lo = reglo; 229 } 230 231 void 232 __tx39timer_rtcreset(tx_chipset_tag_t tc) 233 { 234 txreg_t reg; 235 236 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 237 238 /* Reset counter and stop */ 239 reg |= TX39_TIMERCONTROL_RTCCLR; 240 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 241 242 /* Count again */ 243 reg &= ~TX39_TIMERCONTROL_RTCCLR; 244 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 245 } 246 247 void 248 tx39clock_init(struct device *dev) 249 { 250 struct tx39clock_softc *sc = (void*)dev; 251 tx_chipset_tag_t tc = sc->sc_tc; 252 txreg_t reg; 253 int pcnt; 254 255 /* 256 * Setup periodic timer (interrupting hz times per second.) 257 */ 258 pcnt = TX39_TIMERCLK / CLOCK_RATE - 1; 259 reg = tx_conf_read(tc, TX39_TIMERPERIODIC_REG); 260 TX39_TIMERPERIODIC_PERVAL_CLR(reg); 261 reg = TX39_TIMERPERIODIC_PERVAL_SET(reg, pcnt); 262 tx_conf_write(tc, TX39_TIMERPERIODIC_REG, reg); 263 264 /* 265 * Enable periodic timer 266 */ 267 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 268 reg |= TX39_INTRPRI13_TIMER_PERIODIC_BIT; 269 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 270 } 271 272 void 273 tx39clock_get(struct device *dev, time_t base, struct clock_ymdhms *t) 274 { 275 struct tx39clock_softc *sc = (void *)dev; 276 struct clock_ymdhms dt; 277 struct txtime tt; 278 time_t sec; 279 280 __tx39timer_rtcget(&tt); 281 sec = __tx39timer_rtc2sec(&tt); 282 283 if (!sc->sc_enabled) { 284 DPRINTF(("bootstrap: %d sec from previous reboot\n", 285 (int)sec)); 286 287 sc->sc_enabled = 1; 288 base += sec; 289 } else { 290 dt.dt_year = sc->sc_year; 291 dt.dt_mon = sc->sc_epoch.dt_mon; 292 dt.dt_day = sc->sc_epoch.dt_day; 293 dt.dt_hour = sc->sc_epoch.dt_hour; 294 dt.dt_min = sc->sc_epoch.dt_min; 295 dt.dt_sec = sc->sc_epoch.dt_sec; 296 dt.dt_wday = sc->sc_epoch.dt_wday; 297 base = sec + clock_ymdhms_to_secs(&dt); 298 } 299 300 clock_secs_to_ymdhms(base, &dt); 301 302 t->dt_year = dt.dt_year % 100; 303 t->dt_mon = dt.dt_mon; 304 t->dt_day = dt.dt_day; 305 t->dt_hour = dt.dt_hour; 306 t->dt_min = dt.dt_min; 307 t->dt_sec = dt.dt_sec; 308 t->dt_wday = dt.dt_wday; 309 310 sc->sc_year = dt.dt_year; 311 } 312 313 void 314 tx39clock_set(struct device *dev, struct clock_ymdhms *dt) 315 { 316 struct tx39clock_softc *sc = (void *)dev; 317 318 if (sc->sc_enabled) { 319 sc->sc_epoch = *dt; 320 } 321 } 322 323 int 324 tx39clock_alarm_set(tx_chipset_tag_t tc, int msec) 325 { 326 struct tx39clock_softc *sc = tc->tc_clockt; 327 328 sc->sc_alarm = TX39_MSEC2RTC(msec); 329 tx39clock_alarm_refill(tc); 330 331 return (0); 332 } 333 334 void 335 tx39clock_alarm_refill(tx_chipset_tag_t tc) 336 { 337 struct tx39clock_softc *sc = tc->tc_clockt; 338 struct txtime t; 339 u_int64_t time; 340 341 __tx39timer_rtcget(&t); 342 343 time = ((u_int64_t)t.t_hi << 32) | (u_int64_t)t.t_lo; 344 time += (u_int64_t)sc->sc_alarm; 345 346 t.t_hi = (u_int32_t)((time >> 32) & TX39_TIMERALARMHI_MASK); 347 t.t_lo = (u_int32_t)(time & 0xffffffff); 348 349 tx_conf_write(tc, TX39_TIMERALARMHI_REG, t.t_hi); 350 tx_conf_write(tc, TX39_TIMERALARMLO_REG, t.t_lo); 351 } 352 353 #ifdef TX39CLOCK_DEBUG 354 void 355 tx39clock_dump(tx_chipset_tag_t tc) 356 { 357 txreg_t reg; 358 359 reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG); 360 361 printf(" "); 362 ISSETPRINT(reg, CHIM); 363 #ifdef TX391X 364 ISSETPRINT(reg, VID); 365 ISSETPRINT(reg, MBUS); 366 #endif /* TX391X */ 367 #ifdef TX392X 368 ISSETPRINT(reg, IRDA); 369 #endif /* TX392X */ 370 ISSETPRINT(reg, SPI); 371 ISSETPRINT(reg, TIMER); 372 ISSETPRINT(reg, FASTTIMER); 373 #ifdef TX392X 374 ISSETPRINT(reg, C48MOUT); 375 #endif /* TX392X */ 376 ISSETPRINT(reg, SIBM); 377 ISSETPRINT(reg, CSER); 378 ISSETPRINT(reg, IR); 379 ISSETPRINT(reg, UARTA); 380 ISSETPRINT(reg, UARTB); 381 printf("\n"); 382 } 383 #endif /* TX39CLOCK_DEBUG */ 384
Indexes created Sun Nov 02 23:10:09 GMT 2025