tx39clock.c revision 1.20
1 /* $NetBSD: tx39clock.c,v 1.20 2006/06/16 00:08:28 gdamore Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: tx39clock.c,v 1.20 2006/06/16 00:08:28 gdamore Exp $"); 41 42 #include "opt_tx39clock_debug.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 47 #include <dev/clock_subr.h> 48 49 #include <machine/bus.h> 50 #include <machine/sysconf.h> 51 52 #include <hpcmips/tx/tx39var.h> 53 #include <hpcmips/tx/tx39icureg.h> 54 #include <hpcmips/tx/tx39clockvar.h> 55 #include <hpcmips/tx/tx39clockreg.h> 56 #include <hpcmips/tx/tx39timerreg.h> 57 58 #ifdef TX39CLOCK_DEBUG 59 #define DPRINTF_ENABLE 60 #define DPRINTF_DEBUG tx39clock_debug 61 #endif 62 #include <machine/debug.h> 63 64 #define ISSETPRINT(r, m) \ 65 dbg_bitmask_print(r, TX39_CLOCK_EN ## m ## CLK, #m) 66 67 void tx39clock_init(struct device *); 68 void tx39clock_get(struct device *, time_t, struct clock_ymdhms *); 69 void tx39clock_set(struct device *, struct clock_ymdhms *); 70 71 struct platform_clock tx39_clock = { 72 #define CLOCK_RATE 100 73 CLOCK_RATE, tx39clock_init, tx39clock_get, tx39clock_set, 74 }; 75 76 struct txtime { 77 u_int32_t t_hi; 78 u_int32_t t_lo; 79 }; 80 81 struct tx39clock_softc { 82 struct device sc_dev; 83 tx_chipset_tag_t sc_tc; 84 85 int sc_alarm; 86 int sc_enabled; 87 int sc_year; 88 struct clock_ymdhms sc_epoch; 89 }; 90 91 int tx39clock_match(struct device *, struct cfdata *, void *); 92 void tx39clock_attach(struct device *, struct device *, void *); 93 #ifdef TX39CLOCK_DEBUG 94 void tx39clock_dump(tx_chipset_tag_t); 95 #endif 96 97 void tx39clock_cpuspeed(int *, int *); 98 99 void __tx39timer_rtcfreeze(tx_chipset_tag_t); 100 void __tx39timer_rtcreset(tx_chipset_tag_t); 101 inline void __tx39timer_rtcget(struct txtime *); 102 inline time_t __tx39timer_rtc2sec(struct txtime *); 103 104 CFATTACH_DECL(tx39clock, sizeof(struct tx39clock_softc), 105 tx39clock_match, tx39clock_attach, NULL, NULL); 106 107 int 108 tx39clock_match(struct device *parent, struct cfdata *cf, void *aux) 109 { 110 111 return (ATTACH_FIRST); 112 } 113 114 void 115 tx39clock_attach(struct device *parent, struct device *self, void *aux) 116 { 117 struct txsim_attach_args *ta = aux; 118 struct tx39clock_softc *sc = (void*)self; 119 tx_chipset_tag_t tc; 120 txreg_t reg; 121 122 tc = sc->sc_tc = ta->ta_tc; 123 tx_conf_register_clock(tc, self); 124 125 /* Reset timer module */ 126 tx_conf_write(tc, TX39_TIMERCONTROL_REG, 0); 127 128 /* Enable periodic timer */ 129 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 130 reg |= TX39_TIMERCONTROL_ENPERTIMER; 131 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 132 133 sc->sc_enabled = 0; 134 /* 135 * RTC and ALARM 136 * RTCINT ... INTR5 bit 31 (roll over) 137 * ALARMINT ... INTR5 bit 30 138 * PERINT ... INTR5 bit 29 139 */ 140 141 platform_clock_attach(self, &tx39_clock); 142 143 #ifdef TX39CLOCK_DEBUG 144 tx39clock_dump(tc); 145 #endif /* TX39CLOCK_DEBUG */ 146 } 147 148 /* 149 * cpuclock ... CPU clock (Hz) 150 * cpuspeed ... instructions-per-microsecond 151 */ 152 void 153 tx39clock_cpuspeed(int *cpuclock, int *cpu_speed) 154 { 155 struct txtime t0, t1; 156 int elapsed; 157 158 __tx39timer_rtcget(&t0); 159 __asm volatile( 160 ".set noreorder; \n\t" 161 "li $8, 10000000; \n" 162 "1: nop; \n\t" 163 "nop; \n\t" 164 "nop; \n\t" 165 "nop; \n\t" 166 "nop; \n\t" 167 "nop; \n\t" 168 "nop; \n\t" 169 "add $8, $8, -1; \n\t" 170 "bnez $8, 1b; \n\t" 171 "nop; \n\t" 172 ".set reorder;"); 173 __tx39timer_rtcget(&t1); 174 175 elapsed = t1.t_lo - t0.t_lo; 176 177 *cpuclock = (100000000 / elapsed) * TX39_RTCLOCK; 178 *cpu_speed = *cpuclock / 1000000; 179 } 180 181 void 182 __tx39timer_rtcfreeze(tx_chipset_tag_t tc) 183 { 184 txreg_t reg; 185 186 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 187 188 /* Freeze RTC */ 189 reg |= TX39_TIMERCONTROL_FREEZEPRE; /* Upper 8bit */ 190 reg |= TX39_TIMERCONTROL_FREEZERTC; /* Lower 32bit */ 191 192 /* Freeze periodic timer */ 193 reg |= TX39_TIMERCONTROL_FREEZETIMER; 194 reg &= ~TX39_TIMERCONTROL_ENPERTIMER; 195 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 196 } 197 198 inline time_t 199 __tx39timer_rtc2sec(struct txtime *t) 200 { 201 /* This rely on RTC is 32.768kHz */ 202 return ((t->t_lo >> 15) | (t->t_hi << 17)); 203 } 204 205 inline void 206 __tx39timer_rtcget(struct txtime *t) 207 { 208 tx_chipset_tag_t tc; 209 txreg_t reghi, reglo, oreghi, oreglo; 210 int retry; 211 212 tc = tx_conf_get_tag(); 213 214 retry = 10; 215 216 do { 217 oreglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG); 218 reglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG); 219 220 oreghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG); 221 reghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG); 222 } while ((reghi != oreghi || reglo != oreglo) && (--retry > 0)); 223 224 if (retry < 0) { 225 printf("RTC timer read error.\n"); 226 } 227 228 t->t_hi = TX39_TIMERRTCHI(reghi); 229 t->t_lo = reglo; 230 } 231 232 void 233 __tx39timer_rtcreset(tx_chipset_tag_t tc) 234 { 235 txreg_t reg; 236 237 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 238 239 /* Reset counter and stop */ 240 reg |= TX39_TIMERCONTROL_RTCCLR; 241 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 242 243 /* Count again */ 244 reg &= ~TX39_TIMERCONTROL_RTCCLR; 245 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 246 } 247 248 void 249 tx39clock_init(struct device *dev) 250 { 251 struct tx39clock_softc *sc = (void*)dev; 252 tx_chipset_tag_t tc = sc->sc_tc; 253 txreg_t reg; 254 int pcnt; 255 256 /* 257 * Setup periodic timer (interrupting hz times per second.) 258 */ 259 pcnt = TX39_TIMERCLK / CLOCK_RATE - 1; 260 reg = tx_conf_read(tc, TX39_TIMERPERIODIC_REG); 261 TX39_TIMERPERIODIC_PERVAL_CLR(reg); 262 reg = TX39_TIMERPERIODIC_PERVAL_SET(reg, pcnt); 263 tx_conf_write(tc, TX39_TIMERPERIODIC_REG, reg); 264 265 /* 266 * Enable periodic timer 267 */ 268 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 269 reg |= TX39_INTRPRI13_TIMER_PERIODIC_BIT; 270 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 271 } 272 273 void 274 tx39clock_get(struct device *dev, time_t base, struct clock_ymdhms *t) 275 { 276 struct tx39clock_softc *sc = (void *)dev; 277 struct clock_ymdhms dt; 278 struct txtime tt; 279 time_t sec; 280 281 __tx39timer_rtcget(&tt); 282 sec = __tx39timer_rtc2sec(&tt); 283 284 if (!sc->sc_enabled) { 285 DPRINTF(("bootstrap: %d sec from previous reboot\n", 286 (int)sec)); 287 288 sc->sc_enabled = 1; 289 clock_secs_to_ymdhms(base, &dt); 290 sc->sc_epoch = dt; 291 base += sec; 292 } else { 293 dt.dt_year = sc->sc_year; 294 dt.dt_mon = sc->sc_epoch.dt_mon; 295 dt.dt_day = sc->sc_epoch.dt_day; 296 dt.dt_hour = sc->sc_epoch.dt_hour; 297 dt.dt_min = sc->sc_epoch.dt_min; 298 dt.dt_sec = sc->sc_epoch.dt_sec; 299 dt.dt_wday = sc->sc_epoch.dt_wday; 300 base = sec + clock_ymdhms_to_secs(&dt); 301 } 302 303 clock_secs_to_ymdhms(base, &dt); 304 305 t->dt_year = dt.dt_year % 100; 306 t->dt_mon = dt.dt_mon; 307 t->dt_day = dt.dt_day; 308 t->dt_hour = dt.dt_hour; 309 t->dt_min = dt.dt_min; 310 t->dt_sec = dt.dt_sec; 311 t->dt_wday = dt.dt_wday; 312 313 sc->sc_year = dt.dt_year; 314 } 315 316 void 317 tx39clock_set(struct device *dev, struct clock_ymdhms *dt) 318 { 319 struct tx39clock_softc *sc = (void *)dev; 320 321 if (sc->sc_enabled) { 322 sc->sc_epoch = *dt; 323 __tx39timer_rtcreset(sc->sc_tc); 324 tx39clock_alarm_refill(sc->sc_tc); 325 } 326 } 327 328 int 329 tx39clock_alarm_set(tx_chipset_tag_t tc, int msec) 330 { 331 struct tx39clock_softc *sc = tc->tc_clockt; 332 333 sc->sc_alarm = TX39_MSEC2RTC(msec); 334 tx39clock_alarm_refill(tc); 335 336 return (0); 337 } 338 339 void 340 tx39clock_alarm_refill(tx_chipset_tag_t tc) 341 { 342 struct tx39clock_softc *sc = tc->tc_clockt; 343 struct txtime t; 344 u_int64_t mytime; 345 346 __tx39timer_rtcget(&t); 347 348 mytime = ((u_int64_t)t.t_hi << 32) | (u_int64_t)t.t_lo; 349 mytime += (u_int64_t)sc->sc_alarm; 350 351 t.t_hi = (u_int32_t)((mytime >> 32) & TX39_TIMERALARMHI_MASK); 352 t.t_lo = (u_int32_t)(mytime & 0xffffffff); 353 354 tx_conf_write(tc, TX39_TIMERALARMHI_REG, t.t_hi); 355 tx_conf_write(tc, TX39_TIMERALARMLO_REG, t.t_lo); 356 } 357 358 #ifdef TX39CLOCK_DEBUG 359 void 360 tx39clock_dump(tx_chipset_tag_t tc) 361 { 362 txreg_t reg; 363 364 reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG); 365 366 printf(" "); 367 ISSETPRINT(reg, CHIM); 368 #ifdef TX391X 369 ISSETPRINT(reg, VID); 370 ISSETPRINT(reg, MBUS); 371 #endif /* TX391X */ 372 #ifdef TX392X 373 ISSETPRINT(reg, IRDA); 374 #endif /* TX392X */ 375 ISSETPRINT(reg, SPI); 376 ISSETPRINT(reg, TIMER); 377 ISSETPRINT(reg, FASTTIMER); 378 #ifdef TX392X 379 ISSETPRINT(reg, C48MOUT); 380 #endif /* TX392X */ 381 ISSETPRINT(reg, SIBM); 382 ISSETPRINT(reg, CSER); 383 ISSETPRINT(reg, IR); 384 ISSETPRINT(reg, UARTA); 385 ISSETPRINT(reg, UARTB); 386 printf("\n"); 387 } 388 #endif /* TX39CLOCK_DEBUG */ 389
Indexes created Mon Nov 03 10:09:51 GMT 2025