tx39clock.c revision 1.21
1 /* $NetBSD: tx39clock.c,v 1.21 2006/09/16 02:14:57 gdamore Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: tx39clock.c,v 1.21 2006/09/16 02:14:57 gdamore Exp $"); 41 42 #include "opt_tx39clock_debug.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/timetc.h> 47 48 #include <dev/clock_subr.h> 49 50 #include <machine/bus.h> 51 #include <machine/sysconf.h> 52 53 #include <hpcmips/tx/tx39var.h> 54 #include <hpcmips/tx/tx39icureg.h> 55 #include <hpcmips/tx/tx39clockvar.h> 56 #include <hpcmips/tx/tx39clockreg.h> 57 #include <hpcmips/tx/tx39timerreg.h> 58 59 #ifdef TX39CLOCK_DEBUG 60 #define DPRINTF_ENABLE 61 #define DPRINTF_DEBUG tx39clock_debug 62 #endif 63 #include <machine/debug.h> 64 65 #define ISSETPRINT(r, m) \ 66 dbg_bitmask_print(r, TX39_CLOCK_EN ## m ## CLK, #m) 67 68 void tx39clock_init(struct device *); 69 70 struct platform_clock tx39_clock = { 71 #define CLOCK_RATE 100 72 CLOCK_RATE, tx39clock_init, 73 }; 74 75 struct txtime { 76 u_int32_t t_hi; 77 u_int32_t t_lo; 78 }; 79 80 struct tx39clock_softc { 81 struct device sc_dev; 82 tx_chipset_tag_t sc_tc; 83 84 int sc_alarm; 85 int sc_enabled; 86 int sc_year; 87 struct clock_ymdhms sc_epoch; 88 struct timecounter sc_tcounter; 89 }; 90 91 int tx39clock_match(struct device *, struct cfdata *, void *); 92 void tx39clock_attach(struct device *, struct device *, void *); 93 #ifdef TX39CLOCK_DEBUG 94 void tx39clock_dump(tx_chipset_tag_t); 95 #endif 96 97 void tx39clock_cpuspeed(int *, int *); 98 99 void __tx39timer_rtcfreeze(tx_chipset_tag_t); 100 void __tx39timer_rtcreset(tx_chipset_tag_t); 101 inline void __tx39timer_rtcget(struct txtime *); 102 inline time_t __tx39timer_rtc2sec(struct txtime *); 103 uint32_t tx39_timecount(struct timecounter *); 104 105 CFATTACH_DECL(tx39clock, sizeof(struct tx39clock_softc), 106 tx39clock_match, tx39clock_attach, NULL, NULL); 107 108 int 109 tx39clock_match(struct device *parent, struct cfdata *cf, void *aux) 110 { 111 112 return (ATTACH_FIRST); 113 } 114 115 void 116 tx39clock_attach(struct device *parent, struct device *self, void *aux) 117 { 118 struct txsim_attach_args *ta = aux; 119 struct tx39clock_softc *sc = (void*)self; 120 tx_chipset_tag_t tc; 121 txreg_t reg; 122 123 tc = sc->sc_tc = ta->ta_tc; 124 tx_conf_register_clock(tc, self); 125 126 /* Reset timer module */ 127 tx_conf_write(tc, TX39_TIMERCONTROL_REG, 0); 128 129 /* Enable periodic timer */ 130 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 131 reg |= TX39_TIMERCONTROL_ENPERTIMER; 132 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 133 134 sc->sc_enabled = 0; 135 /* 136 * RTC and ALARM 137 * RTCINT ... INTR5 bit 31 (roll over) 138 * ALARMINT ... INTR5 bit 30 139 * PERINT ... INTR5 bit 29 140 */ 141 142 platform_clock_attach(self, &tx39_clock); 143 144 #ifdef TX39CLOCK_DEBUG 145 tx39clock_dump(tc); 146 #endif /* TX39CLOCK_DEBUG */ 147 } 148 149 /* 150 * cpuclock ... CPU clock (Hz) 151 * cpuspeed ... instructions-per-microsecond 152 */ 153 void 154 tx39clock_cpuspeed(int *cpuclock, int *cpu_speed) 155 { 156 struct txtime t0, t1; 157 int elapsed; 158 159 __tx39timer_rtcget(&t0); 160 __asm volatile( 161 ".set noreorder; \n\t" 162 "li $8, 10000000; \n" 163 "1: nop; \n\t" 164 "nop; \n\t" 165 "nop; \n\t" 166 "nop; \n\t" 167 "nop; \n\t" 168 "nop; \n\t" 169 "nop; \n\t" 170 "add $8, $8, -1; \n\t" 171 "bnez $8, 1b; \n\t" 172 "nop; \n\t" 173 ".set reorder;"); 174 __tx39timer_rtcget(&t1); 175 176 elapsed = t1.t_lo - t0.t_lo; 177 178 *cpuclock = (100000000 / elapsed) * TX39_RTCLOCK; 179 *cpu_speed = *cpuclock / 1000000; 180 } 181 182 void 183 __tx39timer_rtcfreeze(tx_chipset_tag_t tc) 184 { 185 txreg_t reg; 186 187 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 188 189 /* Freeze RTC */ 190 reg |= TX39_TIMERCONTROL_FREEZEPRE; /* Upper 8bit */ 191 reg |= TX39_TIMERCONTROL_FREEZERTC; /* Lower 32bit */ 192 193 /* Freeze periodic timer */ 194 reg |= TX39_TIMERCONTROL_FREEZETIMER; 195 reg &= ~TX39_TIMERCONTROL_ENPERTIMER; 196 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 197 } 198 199 inline void 200 __tx39timer_rtcget(struct txtime *t) 201 { 202 tx_chipset_tag_t tc; 203 txreg_t reghi, reglo, oreghi, oreglo; 204 int retry; 205 206 tc = tx_conf_get_tag(); 207 208 retry = 10; 209 210 do { 211 oreglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG); 212 reglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG); 213 214 oreghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG); 215 reghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG); 216 } while ((reghi != oreghi || reglo != oreglo) && (--retry > 0)); 217 218 if (retry < 0) { 219 printf("RTC timer read error.\n"); 220 } 221 222 t->t_hi = TX39_TIMERRTCHI(reghi); 223 t->t_lo = reglo; 224 } 225 226 void 227 __tx39timer_rtcreset(tx_chipset_tag_t tc) 228 { 229 txreg_t reg; 230 231 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 232 233 /* Reset counter and stop */ 234 reg |= TX39_TIMERCONTROL_RTCCLR; 235 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 236 237 /* Count again */ 238 reg &= ~TX39_TIMERCONTROL_RTCCLR; 239 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 240 } 241 242 uint32_t 243 tx39_timecount(struct timecounter *tch) 244 { 245 tx_chipset_tag_t tc = tch->tc_priv; 246 247 /* 248 * since we're only reading the low register, we don't care about 249 * if the chip increments it. we assume that the single read will 250 * always be consistent. This is much faster than the routine which 251 * has to get both values, improving the quality. 252 */ 253 return (tx_conf_read(tc, TX39_TIMERRTCLO_REG)); 254 } 255 256 void 257 tx39clock_init(struct device *dev) 258 { 259 struct tx39clock_softc *sc = (void*)dev; 260 tx_chipset_tag_t tc = sc->sc_tc; 261 txreg_t reg; 262 int pcnt; 263 264 /* 265 * Setup periodic timer (interrupting hz times per second.) 266 */ 267 pcnt = TX39_TIMERCLK / CLOCK_RATE - 1; 268 reg = tx_conf_read(tc, TX39_TIMERPERIODIC_REG); 269 TX39_TIMERPERIODIC_PERVAL_CLR(reg); 270 reg = TX39_TIMERPERIODIC_PERVAL_SET(reg, pcnt); 271 tx_conf_write(tc, TX39_TIMERPERIODIC_REG, reg); 272 273 /* 274 * Enable periodic timer 275 */ 276 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 277 reg |= TX39_INTRPRI13_TIMER_PERIODIC_BIT; 278 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 279 280 sc->sc_tcounter.tc_name = "tx39rtc"; 281 sc->sc_tcounter.tc_get_timecount = tx39_timecount; 282 sc->sc_tcounter.tc_priv = tc; 283 sc->sc_tcounter.tc_counter_mask = 0xffffffff; 284 sc->sc_tcounter.tc_frequency = TX39_RTCLOCK; 285 sc->sc_tcounter.tc_quality = 100; 286 tc_init(&sc->sc_tcounter); 287 } 288 289 int 290 tx39clock_alarm_set(tx_chipset_tag_t tc, int msec) 291 { 292 struct tx39clock_softc *sc = tc->tc_clockt; 293 294 sc->sc_alarm = TX39_MSEC2RTC(msec); 295 tx39clock_alarm_refill(tc); 296 297 return (0); 298 } 299 300 void 301 tx39clock_alarm_refill(tx_chipset_tag_t tc) 302 { 303 struct tx39clock_softc *sc = tc->tc_clockt; 304 struct txtime t; 305 u_int64_t mytime; 306 307 __tx39timer_rtcget(&t); 308 309 mytime = ((u_int64_t)t.t_hi << 32) | (u_int64_t)t.t_lo; 310 mytime += (u_int64_t)sc->sc_alarm; 311 312 t.t_hi = (u_int32_t)((mytime >> 32) & TX39_TIMERALARMHI_MASK); 313 t.t_lo = (u_int32_t)(mytime & 0xffffffff); 314 315 tx_conf_write(tc, TX39_TIMERALARMHI_REG, t.t_hi); 316 tx_conf_write(tc, TX39_TIMERALARMLO_REG, t.t_lo); 317 } 318 319 #ifdef TX39CLOCK_DEBUG 320 void 321 tx39clock_dump(tx_chipset_tag_t tc) 322 { 323 txreg_t reg; 324 325 reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG); 326 327 printf(" "); 328 ISSETPRINT(reg, CHIM); 329 #ifdef TX391X 330 ISSETPRINT(reg, VID); 331 ISSETPRINT(reg, MBUS); 332 #endif /* TX391X */ 333 #ifdef TX392X 334 ISSETPRINT(reg, IRDA); 335 #endif /* TX392X */ 336 ISSETPRINT(reg, SPI); 337 ISSETPRINT(reg, TIMER); 338 ISSETPRINT(reg, FASTTIMER); 339 #ifdef TX392X 340 ISSETPRINT(reg, C48MOUT); 341 #endif /* TX392X */ 342 ISSETPRINT(reg, SIBM); 343 ISSETPRINT(reg, CSER); 344 ISSETPRINT(reg, IR); 345 ISSETPRINT(reg, UARTA); 346 ISSETPRINT(reg, UARTB); 347 printf("\n"); 348 } 349 #endif /* TX39CLOCK_DEBUG */ 350
Indexes created Sun Nov 02 23:10:09 GMT 2025