tx39clock.c revision 1.22
1 /* $NetBSD: tx39clock.c,v 1.22 2008/01/04 22:13:57 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: tx39clock.c,v 1.22 2008/01/04 22:13:57 ad Exp $"); 41 42 #include "opt_tx39clock_debug.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/timetc.h> 47 #include <sys/device.h> 48 #include <sys/bus.h> 49 50 #include <dev/clock_subr.h> 51 52 #include <machine/sysconf.h> 53 54 #include <hpcmips/tx/tx39var.h> 55 #include <hpcmips/tx/tx39icureg.h> 56 #include <hpcmips/tx/tx39clockvar.h> 57 #include <hpcmips/tx/tx39clockreg.h> 58 #include <hpcmips/tx/tx39timerreg.h> 59 60 #ifdef TX39CLOCK_DEBUG 61 #define DPRINTF_ENABLE 62 #define DPRINTF_DEBUG tx39clock_debug 63 #endif 64 #include <machine/debug.h> 65 66 #define ISSETPRINT(r, m) \ 67 dbg_bitmask_print(r, TX39_CLOCK_EN ## m ## CLK, #m) 68 69 void tx39clock_init(struct device *); 70 71 struct platform_clock tx39_clock = { 72 #define CLOCK_RATE 100 73 CLOCK_RATE, tx39clock_init, 74 }; 75 76 struct txtime { 77 u_int32_t t_hi; 78 u_int32_t t_lo; 79 }; 80 81 struct tx39clock_softc { 82 struct device sc_dev; 83 tx_chipset_tag_t sc_tc; 84 85 int sc_alarm; 86 int sc_enabled; 87 int sc_year; 88 struct clock_ymdhms sc_epoch; 89 struct timecounter sc_tcounter; 90 }; 91 92 int tx39clock_match(struct device *, struct cfdata *, void *); 93 void tx39clock_attach(struct device *, struct device *, void *); 94 #ifdef TX39CLOCK_DEBUG 95 void tx39clock_dump(tx_chipset_tag_t); 96 #endif 97 98 void tx39clock_cpuspeed(int *, int *); 99 100 void __tx39timer_rtcfreeze(tx_chipset_tag_t); 101 void __tx39timer_rtcreset(tx_chipset_tag_t); 102 inline void __tx39timer_rtcget(struct txtime *); 103 inline time_t __tx39timer_rtc2sec(struct txtime *); 104 uint32_t tx39_timecount(struct timecounter *); 105 106 CFATTACH_DECL(tx39clock, sizeof(struct tx39clock_softc), 107 tx39clock_match, tx39clock_attach, NULL, NULL); 108 109 int 110 tx39clock_match(struct device *parent, struct cfdata *cf, void *aux) 111 { 112 113 return (ATTACH_FIRST); 114 } 115 116 void 117 tx39clock_attach(struct device *parent, struct device *self, void *aux) 118 { 119 struct txsim_attach_args *ta = aux; 120 struct tx39clock_softc *sc = (void*)self; 121 tx_chipset_tag_t tc; 122 txreg_t reg; 123 124 tc = sc->sc_tc = ta->ta_tc; 125 tx_conf_register_clock(tc, self); 126 127 /* Reset timer module */ 128 tx_conf_write(tc, TX39_TIMERCONTROL_REG, 0); 129 130 /* Enable periodic timer */ 131 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 132 reg |= TX39_TIMERCONTROL_ENPERTIMER; 133 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 134 135 sc->sc_enabled = 0; 136 /* 137 * RTC and ALARM 138 * RTCINT ... INTR5 bit 31 (roll over) 139 * ALARMINT ... INTR5 bit 30 140 * PERINT ... INTR5 bit 29 141 */ 142 143 platform_clock_attach(self, &tx39_clock); 144 145 #ifdef TX39CLOCK_DEBUG 146 tx39clock_dump(tc); 147 #endif /* TX39CLOCK_DEBUG */ 148 } 149 150 /* 151 * cpuclock ... CPU clock (Hz) 152 * cpuspeed ... instructions-per-microsecond 153 */ 154 void 155 tx39clock_cpuspeed(int *cpuclock, int *cpu_speed) 156 { 157 struct txtime t0, t1; 158 int elapsed; 159 160 __tx39timer_rtcget(&t0); 161 __asm volatile( 162 ".set noreorder; \n\t" 163 "li $8, 10000000; \n" 164 "1: nop; \n\t" 165 "nop; \n\t" 166 "nop; \n\t" 167 "nop; \n\t" 168 "nop; \n\t" 169 "nop; \n\t" 170 "nop; \n\t" 171 "add $8, $8, -1; \n\t" 172 "bnez $8, 1b; \n\t" 173 "nop; \n\t" 174 ".set reorder;"); 175 __tx39timer_rtcget(&t1); 176 177 elapsed = t1.t_lo - t0.t_lo; 178 179 *cpuclock = (100000000 / elapsed) * TX39_RTCLOCK; 180 *cpu_speed = *cpuclock / 1000000; 181 } 182 183 void 184 __tx39timer_rtcfreeze(tx_chipset_tag_t tc) 185 { 186 txreg_t reg; 187 188 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 189 190 /* Freeze RTC */ 191 reg |= TX39_TIMERCONTROL_FREEZEPRE; /* Upper 8bit */ 192 reg |= TX39_TIMERCONTROL_FREEZERTC; /* Lower 32bit */ 193 194 /* Freeze periodic timer */ 195 reg |= TX39_TIMERCONTROL_FREEZETIMER; 196 reg &= ~TX39_TIMERCONTROL_ENPERTIMER; 197 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 198 } 199 200 inline void 201 __tx39timer_rtcget(struct txtime *t) 202 { 203 tx_chipset_tag_t tc; 204 txreg_t reghi, reglo, oreghi, oreglo; 205 int retry; 206 207 tc = tx_conf_get_tag(); 208 209 retry = 10; 210 211 do { 212 oreglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG); 213 reglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG); 214 215 oreghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG); 216 reghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG); 217 } while ((reghi != oreghi || reglo != oreglo) && (--retry > 0)); 218 219 if (retry < 0) { 220 printf("RTC timer read error.\n"); 221 } 222 223 t->t_hi = TX39_TIMERRTCHI(reghi); 224 t->t_lo = reglo; 225 } 226 227 void 228 __tx39timer_rtcreset(tx_chipset_tag_t tc) 229 { 230 txreg_t reg; 231 232 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 233 234 /* Reset counter and stop */ 235 reg |= TX39_TIMERCONTROL_RTCCLR; 236 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 237 238 /* Count again */ 239 reg &= ~TX39_TIMERCONTROL_RTCCLR; 240 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 241 } 242 243 uint32_t 244 tx39_timecount(struct timecounter *tch) 245 { 246 tx_chipset_tag_t tc = tch->tc_priv; 247 248 /* 249 * since we're only reading the low register, we don't care about 250 * if the chip increments it. we assume that the single read will 251 * always be consistent. This is much faster than the routine which 252 * has to get both values, improving the quality. 253 */ 254 return (tx_conf_read(tc, TX39_TIMERRTCLO_REG)); 255 } 256 257 void 258 tx39clock_init(struct device *dev) 259 { 260 struct tx39clock_softc *sc = (void*)dev; 261 tx_chipset_tag_t tc = sc->sc_tc; 262 txreg_t reg; 263 int pcnt; 264 265 /* 266 * Setup periodic timer (interrupting hz times per second.) 267 */ 268 pcnt = TX39_TIMERCLK / CLOCK_RATE - 1; 269 reg = tx_conf_read(tc, TX39_TIMERPERIODIC_REG); 270 TX39_TIMERPERIODIC_PERVAL_CLR(reg); 271 reg = TX39_TIMERPERIODIC_PERVAL_SET(reg, pcnt); 272 tx_conf_write(tc, TX39_TIMERPERIODIC_REG, reg); 273 274 /* 275 * Enable periodic timer 276 */ 277 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 278 reg |= TX39_INTRPRI13_TIMER_PERIODIC_BIT; 279 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 280 281 sc->sc_tcounter.tc_name = "tx39rtc"; 282 sc->sc_tcounter.tc_get_timecount = tx39_timecount; 283 sc->sc_tcounter.tc_priv = tc; 284 sc->sc_tcounter.tc_counter_mask = 0xffffffff; 285 sc->sc_tcounter.tc_frequency = TX39_RTCLOCK; 286 sc->sc_tcounter.tc_quality = 100; 287 tc_init(&sc->sc_tcounter); 288 } 289 290 int 291 tx39clock_alarm_set(tx_chipset_tag_t tc, int msec) 292 { 293 struct tx39clock_softc *sc = tc->tc_clockt; 294 295 sc->sc_alarm = TX39_MSEC2RTC(msec); 296 tx39clock_alarm_refill(tc); 297 298 return (0); 299 } 300 301 void 302 tx39clock_alarm_refill(tx_chipset_tag_t tc) 303 { 304 struct tx39clock_softc *sc = tc->tc_clockt; 305 struct txtime t; 306 u_int64_t mytime; 307 308 __tx39timer_rtcget(&t); 309 310 mytime = ((u_int64_t)t.t_hi << 32) | (u_int64_t)t.t_lo; 311 mytime += (u_int64_t)sc->sc_alarm; 312 313 t.t_hi = (u_int32_t)((mytime >> 32) & TX39_TIMERALARMHI_MASK); 314 t.t_lo = (u_int32_t)(mytime & 0xffffffff); 315 316 tx_conf_write(tc, TX39_TIMERALARMHI_REG, t.t_hi); 317 tx_conf_write(tc, TX39_TIMERALARMLO_REG, t.t_lo); 318 } 319 320 #ifdef TX39CLOCK_DEBUG 321 void 322 tx39clock_dump(tx_chipset_tag_t tc) 323 { 324 txreg_t reg; 325 326 reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG); 327 328 printf(" "); 329 ISSETPRINT(reg, CHIM); 330 #ifdef TX391X 331 ISSETPRINT(reg, VID); 332 ISSETPRINT(reg, MBUS); 333 #endif /* TX391X */ 334 #ifdef TX392X 335 ISSETPRINT(reg, IRDA); 336 #endif /* TX392X */ 337 ISSETPRINT(reg, SPI); 338 ISSETPRINT(reg, TIMER); 339 ISSETPRINT(reg, FASTTIMER); 340 #ifdef TX392X 341 ISSETPRINT(reg, C48MOUT); 342 #endif /* TX392X */ 343 ISSETPRINT(reg, SIBM); 344 ISSETPRINT(reg, CSER); 345 ISSETPRINT(reg, IR); 346 ISSETPRINT(reg, UARTA); 347 ISSETPRINT(reg, UARTB); 348 printf("\n"); 349 } 350 #endif /* TX39CLOCK_DEBUG */ 351
Indexes created Sun Nov 02 23:10:09 GMT 2025