tx39clock.c revision 1.25
1 /* $NetBSD: tx39clock.c,v 1.25 2011/03/16 14:43:37 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tx39clock.c,v 1.25 2011/03/16 14:43:37 tsutsui Exp $"); 34 35 #include "opt_tx39clock_debug.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/timetc.h> 40 #include <sys/device.h> 41 #include <sys/bus.h> 42 43 #include <dev/clock_subr.h> 44 45 #include <machine/sysconf.h> 46 47 #include <hpcmips/tx/tx39var.h> 48 #include <hpcmips/tx/tx39icureg.h> 49 #include <hpcmips/tx/tx39clockvar.h> 50 #include <hpcmips/tx/tx39clockreg.h> 51 #include <hpcmips/tx/tx39timerreg.h> 52 53 #ifdef TX39CLOCK_DEBUG 54 #define DPRINTF_ENABLE 55 #define DPRINTF_DEBUG tx39clock_debug 56 #endif 57 #include <machine/debug.h> 58 59 #define ISSETPRINT(r, m) \ 60 dbg_bitmask_print(r, TX39_CLOCK_EN ## m ## CLK, #m) 61 62 void tx39clock_init(device_t); 63 64 struct platform_clock tx39_clock = { 65 #define CLOCK_RATE 100 66 CLOCK_RATE, tx39clock_init, 67 }; 68 69 struct txtime { 70 uint32_t t_hi; 71 uint32_t t_lo; 72 }; 73 74 struct tx39clock_softc { 75 struct device sc_dev; 76 tx_chipset_tag_t sc_tc; 77 78 int sc_alarm; 79 int sc_enabled; 80 int sc_year; 81 struct clock_ymdhms sc_epoch; 82 struct timecounter sc_tcounter; 83 }; 84 85 int tx39clock_match(struct device *, struct cfdata *, void *); 86 void tx39clock_attach(struct device *, struct device *, void *); 87 #ifdef TX39CLOCK_DEBUG 88 void tx39clock_dump(tx_chipset_tag_t); 89 #endif 90 91 void tx39clock_cpuspeed(int *, int *); 92 93 void __tx39timer_rtcfreeze(tx_chipset_tag_t); 94 void __tx39timer_rtcreset(tx_chipset_tag_t); 95 inline void __tx39timer_rtcget(struct txtime *); 96 inline time_t __tx39timer_rtc2sec(struct txtime *); 97 uint32_t tx39_timecount(struct timecounter *); 98 99 CFATTACH_DECL(tx39clock, sizeof(struct tx39clock_softc), 100 tx39clock_match, tx39clock_attach, NULL, NULL); 101 102 int 103 tx39clock_match(struct device *parent, struct cfdata *cf, void *aux) 104 { 105 106 return ATTACH_FIRST; 107 } 108 109 void 110 tx39clock_attach(struct device *parent, struct device *self, void *aux) 111 { 112 struct txsim_attach_args *ta = aux; 113 struct tx39clock_softc *sc = device_private(self); 114 tx_chipset_tag_t tc; 115 txreg_t reg; 116 117 tc = sc->sc_tc = ta->ta_tc; 118 tx_conf_register_clock(tc, self); 119 120 /* Reset timer module */ 121 tx_conf_write(tc, TX39_TIMERCONTROL_REG, 0); 122 123 /* Enable periodic timer */ 124 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 125 reg |= TX39_TIMERCONTROL_ENPERTIMER; 126 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 127 128 sc->sc_enabled = 0; 129 /* 130 * RTC and ALARM 131 * RTCINT ... INTR5 bit 31 (roll over) 132 * ALARMINT ... INTR5 bit 30 133 * PERINT ... INTR5 bit 29 134 */ 135 136 platform_clock_attach(self, &tx39_clock); 137 138 #ifdef TX39CLOCK_DEBUG 139 tx39clock_dump(tc); 140 #endif /* TX39CLOCK_DEBUG */ 141 } 142 143 /* 144 * cpuclock ... CPU clock (Hz) 145 * cpuspeed ... instructions-per-microsecond 146 */ 147 void 148 tx39clock_cpuspeed(int *cpuclock, int *cpu_speed) 149 { 150 struct txtime t0, t1; 151 int elapsed; 152 153 __tx39timer_rtcget(&t0); 154 __asm volatile( 155 ".set noreorder; \n\t" 156 "li $8, 10000000; \n" 157 "1: nop; \n\t" 158 "nop; \n\t" 159 "nop; \n\t" 160 "nop; \n\t" 161 "nop; \n\t" 162 "nop; \n\t" 163 "nop; \n\t" 164 "add $8, $8, -1; \n\t" 165 "bnez $8, 1b; \n\t" 166 "nop; \n\t" 167 ".set reorder;"); 168 __tx39timer_rtcget(&t1); 169 170 elapsed = t1.t_lo - t0.t_lo; 171 172 *cpuclock = (100000000 / elapsed) * TX39_RTCLOCK; 173 *cpu_speed = *cpuclock / 1000000; 174 } 175 176 void 177 __tx39timer_rtcfreeze(tx_chipset_tag_t tc) 178 { 179 txreg_t reg; 180 181 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 182 183 /* Freeze RTC */ 184 reg |= TX39_TIMERCONTROL_FREEZEPRE; /* Upper 8bit */ 185 reg |= TX39_TIMERCONTROL_FREEZERTC; /* Lower 32bit */ 186 187 /* Freeze periodic timer */ 188 reg |= TX39_TIMERCONTROL_FREEZETIMER; 189 reg &= ~TX39_TIMERCONTROL_ENPERTIMER; 190 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 191 } 192 193 inline void 194 __tx39timer_rtcget(struct txtime *t) 195 { 196 tx_chipset_tag_t tc; 197 txreg_t reghi, reglo, oreghi, oreglo; 198 int retry; 199 200 tc = tx_conf_get_tag(); 201 202 retry = 10; 203 204 do { 205 oreglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG); 206 reglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG); 207 208 oreghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG); 209 reghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG); 210 } while ((reghi != oreghi || reglo != oreglo) && (--retry > 0)); 211 212 if (retry < 0) { 213 printf("RTC timer read error.\n"); 214 } 215 216 t->t_hi = TX39_TIMERRTCHI(reghi); 217 t->t_lo = reglo; 218 } 219 220 void 221 __tx39timer_rtcreset(tx_chipset_tag_t tc) 222 { 223 txreg_t reg; 224 225 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 226 227 /* Reset counter and stop */ 228 reg |= TX39_TIMERCONTROL_RTCCLR; 229 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 230 231 /* Count again */ 232 reg &= ~TX39_TIMERCONTROL_RTCCLR; 233 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg); 234 } 235 236 uint32_t 237 tx39_timecount(struct timecounter *tch) 238 { 239 tx_chipset_tag_t tc = tch->tc_priv; 240 241 /* 242 * since we're only reading the low register, we don't care about 243 * if the chip increments it. we assume that the single read will 244 * always be consistent. This is much faster than the routine which 245 * has to get both values, improving the quality. 246 */ 247 return tx_conf_read(tc, TX39_TIMERRTCLO_REG); 248 } 249 250 void 251 tx39clock_init(device_t self) 252 { 253 struct tx39clock_softc *sc = device_private(self); 254 tx_chipset_tag_t tc = sc->sc_tc; 255 txreg_t reg; 256 int pcnt; 257 258 /* 259 * Setup periodic timer (interrupting hz times per second.) 260 */ 261 pcnt = TX39_TIMERCLK / CLOCK_RATE - 1; 262 reg = tx_conf_read(tc, TX39_TIMERPERIODIC_REG); 263 TX39_TIMERPERIODIC_PERVAL_CLR(reg); 264 reg = TX39_TIMERPERIODIC_PERVAL_SET(reg, pcnt); 265 tx_conf_write(tc, TX39_TIMERPERIODIC_REG, reg); 266 267 /* 268 * Enable periodic timer 269 */ 270 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 271 reg |= TX39_INTRPRI13_TIMER_PERIODIC_BIT; 272 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 273 274 sc->sc_tcounter.tc_name = "tx39rtc"; 275 sc->sc_tcounter.tc_get_timecount = tx39_timecount; 276 sc->sc_tcounter.tc_priv = tc; 277 sc->sc_tcounter.tc_counter_mask = 0xffffffff; 278 sc->sc_tcounter.tc_frequency = TX39_RTCLOCK; 279 sc->sc_tcounter.tc_quality = 100; 280 tc_init(&sc->sc_tcounter); 281 } 282 283 int 284 tx39clock_alarm_set(tx_chipset_tag_t tc, int msec) 285 { 286 struct tx39clock_softc *sc = tc->tc_clockt; 287 288 sc->sc_alarm = TX39_MSEC2RTC(msec); 289 tx39clock_alarm_refill(tc); 290 291 return 0; 292 } 293 294 void 295 tx39clock_alarm_refill(tx_chipset_tag_t tc) 296 { 297 struct tx39clock_softc *sc = tc->tc_clockt; 298 struct txtime t; 299 uint64_t mytime; 300 301 __tx39timer_rtcget(&t); 302 303 mytime = ((uint64_t)t.t_hi << 32) | (uint64_t)t.t_lo; 304 mytime += (uint64_t)sc->sc_alarm; 305 306 t.t_hi = (uint32_t)((mytime >> 32) & TX39_TIMERALARMHI_MASK); 307 t.t_lo = (uint32_t)(mytime & 0xffffffff); 308 309 tx_conf_write(tc, TX39_TIMERALARMHI_REG, t.t_hi); 310 tx_conf_write(tc, TX39_TIMERALARMLO_REG, t.t_lo); 311 } 312 313 #ifdef TX39CLOCK_DEBUG 314 void 315 tx39clock_dump(tx_chipset_tag_t tc) 316 { 317 txreg_t reg; 318 319 reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG); 320 321 printf(" "); 322 ISSETPRINT(reg, CHIM); 323 #ifdef TX391X 324 ISSETPRINT(reg, VID); 325 ISSETPRINT(reg, MBUS); 326 #endif /* TX391X */ 327 #ifdef TX392X 328 ISSETPRINT(reg, IRDA); 329 #endif /* TX392X */ 330 ISSETPRINT(reg, SPI); 331 ISSETPRINT(reg, TIMER); 332 ISSETPRINT(reg, FASTTIMER); 333 #ifdef TX392X 334 ISSETPRINT(reg, C48MOUT); 335 #endif /* TX392X */ 336 ISSETPRINT(reg, SIBM); 337 ISSETPRINT(reg, CSER); 338 ISSETPRINT(reg, IR); 339 ISSETPRINT(reg, UARTA); 340 ISSETPRINT(reg, UARTB); 341 printf("\n"); 342 } 343 #endif /* TX39CLOCK_DEBUG */ 344
Indexes created Sun Nov 02 23:10:09 GMT 2025