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tx39clock.c revision 1.3 
      1 /*	$NetBSD: tx39clock.c,v 1.3 1999/12/22 15:35:35 uch Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1999, by UCHIYAMA Yasushi
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. The name of the developer may NOT be used to endorse or promote products
     13  *    derived from this software without specific prior written permission.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     25  * SUCH DAMAGE.
     26  *
     27  */
     28 #include "opt_tx39_debug.h"
     29 
     30 #include <sys/param.h>
     31 #include <sys/kernel.h>
     32 #include <sys/systm.h>
     33 #include <sys/device.h>
     34 
     35 #include <dev/clock_subr.h>
     36 
     37 #include <machine/bus.h>
     38 #include <machine/clock_machdep.h>
     39 #include <machine/cpu.h>
     40 
     41 #include <hpcmips/tx/tx39var.h>
     42 #include <hpcmips/tx/tx39icureg.h>
     43 #include <hpcmips/tx/tx39clockreg.h>
     44 #include <hpcmips/tx/tx39timerreg.h>
     45 
     46 #include <dev/dec/clockvar.h>
     47 
     48 #ifdef TX39CLKDEBUG
     49 #define	DPRINTF(arg) printf arg
     50 #else
     51 #define	DPRINTF(arg)
     52 #endif
     53 
     54 #define ISSETPRINT(r, m) __is_set_print(r, TX39_CLOCK_EN##m##CLK, #m)
     55 
     56 void	tx39clock_init __P((struct device*));
     57 void	tx39clock_get __P((struct device*, time_t, struct clocktime*));
     58 void	tx39clock_set __P((struct device*, struct clocktime*));
     59 
     60 const struct clockfns tx39clockfns = {
     61 	tx39clock_init, tx39clock_get, tx39clock_set,
     62 };
     63 
     64 struct txtime {
     65 	u_int32_t t_hi;
     66 	u_int32_t t_lo;
     67 };
     68 
     69 struct tx39clock_softc {
     70 	struct	device sc_dev;
     71 	tx_chipset_tag_t sc_tc;
     72 
     73 	int sc_enabled;
     74 	int sc_year;
     75 	struct clocktime sc_epoch;
     76 };
     77 
     78 int	tx39clock_match __P((struct device*, struct cfdata*, void*));
     79 void	tx39clock_attach __P((struct device*, struct device*, void*));
     80 void	tx39clock_dump __P((tx_chipset_tag_t));
     81 
     82 void	tx39clock_cpuspeed __P((int*, int*));
     83 
     84 void	__tx39timer_rtcfreeze __P((tx_chipset_tag_t));
     85 void	__tx39timer_rtcreset __P((tx_chipset_tag_t));
     86 __inline void	__tx39timer_rtcget __P((struct txtime*));
     87 __inline time_t	__tx39timer_rtc2sec __P((struct txtime*));
     88 
     89 struct cfattach tx39clock_ca = {
     90 	sizeof(struct tx39clock_softc), tx39clock_match, tx39clock_attach
     91 };
     92 
     93 int
     94 tx39clock_match(parent, cf, aux)
     95 	struct device *parent;
     96 	struct cfdata *cf;
     97 	void *aux;
     98 {
     99 	return 2; /* 1st attach group of txsim */
    100 }
    101 
    102 void
    103 tx39clock_attach(parent, self, aux)
    104 	struct device *parent;
    105 	struct device *self;
    106 	void *aux;
    107 {
    108 	struct txsim_attach_args *ta = aux;
    109 	struct tx39clock_softc *sc = (void*)self;
    110 	tx_chipset_tag_t tc;
    111 	txreg_t reg;
    112 
    113 	tc = sc->sc_tc = ta->ta_tc;
    114 
    115 	/* Reset timer module */
    116 	tx_conf_write(tc, TX39_TIMERCONTROL_REG, 0);
    117 
    118 	/* Enable periodic timer */
    119 	reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);
    120 	reg |= TX39_TIMERCONTROL_ENPERTIMER;
    121 	tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
    122 
    123 	sc->sc_enabled = 0;
    124 	/*
    125 	 * RTC and ALARM
    126 	 *    RTCINT    ... INTR5 bit 31  (roll over)
    127 	 *    ALARMINT  ... INTR5 bit 30
    128 	 *    PERINT    ... INTR5 bit 29
    129 	 */
    130 
    131 	clockattach(self, &tx39clockfns);
    132 
    133 #ifdef TX39CLKDEBUG
    134 	tx39clock_dump(tc);
    135 #endif /* TX39CLKDEBUG */
    136 }
    137 
    138 /*
    139  * cpuclock ... CPU clock (Hz)
    140  * cpuspeed ... instructions-per-microsecond
    141  */
    142 void
    143 tx39clock_cpuspeed(cpuclock, cpuspeed)
    144 	int *cpuclock;
    145 	int *cpuspeed;
    146 {
    147 	struct txtime t0, t1;
    148 	int elapsed;
    149 
    150 	__tx39timer_rtcget(&t0);
    151 	__asm __volatile("
    152 		.set	noreorder;
    153 		li	$8, 10000000;
    154 	1:	nop;
    155 		nop;
    156 		nop;
    157 		nop;
    158 		nop;
    159 		nop;
    160 		nop;
    161 		add	$8, $8, -1;
    162 		bnez	$8, 1b;
    163 		nop;
    164 		.set	reorder;
    165 	");
    166 	__tx39timer_rtcget(&t1);
    167 
    168 	elapsed = t1.t_lo - t0.t_lo;
    169 
    170 	*cpuclock = (100000000 / elapsed) * TX39_RTCLOCK;
    171 	*cpuspeed = *cpuclock / 1000000;
    172 
    173 }
    174 
    175 void
    176 __tx39timer_rtcfreeze(tc)
    177 	tx_chipset_tag_t tc;
    178 {
    179 	txreg_t reg;
    180 
    181 	reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);
    182 
    183 	/* Freeze RTC */
    184 	reg |= TX39_TIMERCONTROL_FREEZEPRE; /* Upper 8bit */
    185 	reg |= TX39_TIMERCONTROL_FREEZERTC; /* Lower 32bit */
    186 
    187 	/* Freeze periodic timer */
    188 	reg |= TX39_TIMERCONTROL_FREEZETIMER;
    189 	reg &= ~TX39_TIMERCONTROL_ENPERTIMER;
    190 	tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
    191 }
    192 
    193 __inline time_t
    194 __tx39timer_rtc2sec(t)
    195 	struct txtime *t;
    196 {
    197 	/* This rely on RTC is 32.768kHz */
    198 	return (t->t_lo >> 15) | (t->t_hi << 17);
    199 }
    200 
    201 __inline void
    202 __tx39timer_rtcget(t)
    203 	struct txtime *t;
    204 {
    205 	tx_chipset_tag_t tc;
    206 	txreg_t reghi, reglo, oreghi, oreglo;
    207 	int retry;
    208 
    209 	tc = tx_conf_get_tag();
    210 
    211 	retry = 10;
    212 
    213 	do {
    214 		oreglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG);
    215 		reglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG);
    216 
    217 		oreghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG);
    218 		reghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG);
    219 	} while ((reghi != oreghi || reglo != oreglo) && (--retry > 0));
    220 
    221 	if (retry < 0) {
    222 		printf("RTC timer read error.\n");
    223 	}
    224 
    225 	t->t_hi = TX39_TIMERRTCHI(reghi);
    226 	t->t_lo = reglo;
    227 }
    228 
    229 void
    230 __tx39timer_rtcreset(tc)
    231  	tx_chipset_tag_t tc;
    232 {
    233 	txreg_t reg;
    234 
    235 	reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);
    236 
    237 	/* Reset counter and stop */
    238 	reg |= TX39_TIMERCONTROL_RTCCLR;
    239 	tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
    240 
    241 	/* Count again */
    242 	reg &= ~TX39_TIMERCONTROL_RTCCLR;
    243 	tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
    244 }
    245 
    246 void
    247 tx39clock_init(dev)
    248 	struct device *dev;
    249 {
    250 	tx_chipset_tag_t tc;
    251 	txreg_t reg;
    252 	int pcnt;
    253 
    254 	tc = tx_conf_get_tag();
    255 
    256 	/*
    257 	 * Setup periodic timer (interrupting hz times per second.)
    258 	 */
    259 	pcnt = TX39_TIMERCLK / hz - 1;
    260 	reg = tx_conf_read(tc, TX39_TIMERPERIODIC_REG);
    261 	TX39_TIMERPERIODIC_PERVAL_CLR(reg);
    262 	reg = TX39_TIMERPERIODIC_PERVAL_SET(reg, pcnt);
    263 	tx_conf_write(tc, TX39_TIMERPERIODIC_REG, reg);
    264 
    265 	/*
    266 	 * Enable periodic timer
    267 	 */
    268 	reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);
    269 	reg |= TX39_INTRPRI13_TIMER_PERIODIC_BIT;
    270 	tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);
    271 
    272 	/*
    273 	 * number of microseconds between interrupts
    274 	 */
    275 	tick = 1000000 / hz;
    276 }
    277 
    278 void
    279 tx39clock_get(dev, base, ct)
    280 	struct device *dev;
    281 	time_t base;
    282 	struct clocktime *ct;
    283 {
    284 	struct clock_ymdhms dt;
    285 	struct tx39clock_softc *sc = (void*)dev;
    286 	struct txtime tt;
    287 	time_t sec;
    288 
    289 	__tx39timer_rtcget(&tt);
    290 	sec = __tx39timer_rtc2sec(&tt);
    291 
    292 	if (!sc->sc_enabled) {
    293 		DPRINTF(("bootstrap: %d sec from previous reboot\n",
    294 			 (int)sec));
    295 
    296 		sc->sc_enabled = 1;
    297 		base += sec;
    298 	} else {
    299 		dt.dt_year = sc->sc_year;
    300 		dt.dt_mon = sc->sc_epoch.mon;
    301 		dt.dt_day = sc->sc_epoch.day;
    302 		dt.dt_hour = sc->sc_epoch.hour;
    303 		dt.dt_min = sc->sc_epoch.min;
    304 		dt.dt_sec = sc->sc_epoch.sec;
    305 		dt.dt_wday = sc->sc_epoch.dow;
    306 		sec += clock_ymdhms_to_secs(&dt);
    307 	}
    308 
    309 	clock_secs_to_ymdhms(base, &dt);
    310 
    311 	ct->year = dt.dt_year % 100;
    312 	ct->mon = dt.dt_mon;
    313 	ct->day = dt.dt_day;
    314 	ct->hour = dt.dt_hour;
    315 	ct->min = dt.dt_min;
    316 	ct->sec = dt.dt_sec;
    317 	ct->dow = dt.dt_wday;
    318 
    319 	sc->sc_year = dt.dt_year;
    320 }
    321 
    322 void
    323 tx39clock_set(dev, ct)
    324 	struct device *dev;
    325 	struct clocktime *ct;
    326 {
    327 	struct tx39clock_softc *sc = (void*)dev;
    328 
    329 	if (sc->sc_enabled) {
    330 		sc->sc_epoch = *ct;
    331 		/* Reset RTC counter */
    332 		__tx39timer_rtcreset(sc->sc_tc);
    333 	}
    334 }
    335 
    336 void
    337 tx39clock_dump(tc)
    338 	tx_chipset_tag_t tc;
    339 {
    340 	txreg_t reg;
    341 
    342 	reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);
    343 
    344 	printf(" ");
    345 	ISSETPRINT(reg, CHIM);
    346 #ifdef TX391X
    347 	ISSETPRINT(reg, VID);
    348 	ISSETPRINT(reg, MBUS);
    349 #endif /* TX391X */
    350 #ifdef TX392X
    351 	ISSETPRINT(reg, IRDA);
    352 #endif /* TX392X */
    353 	ISSETPRINT(reg, SPI);
    354 	ISSETPRINT(reg, TIMER);
    355 	ISSETPRINT(reg, FASTTIMER);
    356 #ifdef TX392X
    357 	ISSETPRINT(reg, C48MOUT);
    358 #endif /* TX392X */
    359 	ISSETPRINT(reg, SIBM);
    360 	ISSETPRINT(reg, CSER);
    361 	ISSETPRINT(reg, IR);
    362 	ISSETPRINT(reg, UARTA);
    363 	ISSETPRINT(reg, UARTB);
    364 	printf("\n");
    365 }
    366