tx39clockreg.h revision 1.2.130.1
1 1.2.130.1 yamt /* $NetBSD: tx39clockreg.h,v 1.2.130.1 2008/05/18 12:32:04 yamt Exp $ */ 2 1.1 uch 3 1.2 uch /*- 4 1.2 uch * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.2 uch * This code is derived from software contributed to The NetBSD Foundation 8 1.2 uch * by UCHIYAMA Yasushi. 9 1.2 uch * 10 1.1 uch * Redistribution and use in source and binary forms, with or without 11 1.1 uch * modification, are permitted provided that the following conditions 12 1.1 uch * are met: 13 1.1 uch * 1. Redistributions of source code must retain the above copyright 14 1.1 uch * notice, this list of conditions and the following disclaimer. 15 1.2 uch * 2. Redistributions in binary form must reproduce the above copyright 16 1.2 uch * notice, this list of conditions and the following disclaimer in the 17 1.2 uch * documentation and/or other materials provided with the distribution. 18 1.1 uch * 19 1.2 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2 uch * POSSIBILITY OF SUCH DAMAGE. 30 1.1 uch */ 31 1.2 uch 32 1.1 uch /* 33 1.1 uch * Toshiba TX3912/3922 Clock module 34 1.1 uch */ 35 1.1 uch 36 1.2 uch #define TX39_CLOCKCTRL_REG 0x1c0 37 1.1 uch 38 1.1 uch /* 39 1.1 uch * Clock Control Register 40 1.1 uch */ 41 1.1 uch /* R/W */ 42 1.1 uch #define TX39_CLOCK_CHICLKDIV_SHIFT 24 43 1.1 uch #define TX39_CLOCK_CHICLKDIV_MASK 0xff 44 1.2 uch #define TX39_CLOCK_CHICLKDIV(cr) \ 45 1.2 uch (((cr) >> TX39_CLOCK_CHICLKDIV_SHIFT) & \ 46 1.1 uch TX39_CLOCK_CHICLKDIV_MASK) 47 1.2 uch #define TX39_CLOCK_CHICLKDIV_SET(cr, val) \ 48 1.2 uch ((cr) | (((val) << TX39_CLOCK_CHICLKDIV_SHIFT) & \ 49 1.1 uch (TX39_CLOCK_CHICLKDIV_MASK << TX39_CLOCK_CHICLKDIV_SHIFT))) 50 1.1 uch 51 1.2 uch #define TX39_CLOCK_ENCLKTEST 0x00800000 52 1.2 uch #define TX39_CLOCK_CCLKTESTSELSIB 0x00400000 53 1.2 uch #define TX39_CLOCK_CHIMCLKSEL 0x00200000 54 1.2 uch #define TX39_CLOCK_CHICLKDIR 0x00100000 55 1.2 uch #define TX39_CLOCK_ENCHIMCLK 0x00080000 56 1.1 uch #ifdef TX391X 57 1.2 uch #define TX39_CLOCK_ENVIDCLK 0x00040000 58 1.2 uch #define TX39_CLOCK_ENMBUSCLK 0x00020000 59 1.1 uch #endif /* TX391X */ 60 1.1 uch #ifdef TX392X 61 1.2 uch #define TX39_CLOCK_SPICLKDIR 0x00040000 62 1.2 uch #define TX39_CLOCK_ENIRDACLK 0x00020000 63 1.1 uch #endif /* TX392X */ 64 1.2 uch #define TX39_CLOCK_ENSPICLK 0x00010000 65 1.2 uch #define TX39_CLOCK_ENTIMERCLK 0x00008000 66 1.2 uch #define TX39_CLOCK_ENFASTTIMERCLK 0x00004000 67 1.2 uch #define TX39_CLOCK_SIBCLKDIR 0x00002000 68 1.1 uch #ifdef TX392X 69 1.2 uch #define TX39_CLOCK_ENC48MOUTCLK 0x00001000 70 1.1 uch #endif /* TX392X */ 71 1.2 uch #define TX39_CLOCK_ENSIBMCLK 0x00000800 72 1.1 uch 73 1.1 uch #define TX39_CLOCK_SIBMCLKDIV_SHIFT 8 74 1.1 uch #define TX39_CLOCK_SIBMCLKDIV_MASK 0x7 75 1.2 uch #define TX39_CLOCK_SIBMCLKDIV(cr) \ 76 1.2 uch (((cr) >> TX39_CLOCK_SIBMCLKDIV_SHIFT) & \ 77 1.1 uch TX39_CLOCK_SIBMCLKDIV_MASK) 78 1.2 uch #define TX39_CLOCK_SIBMCLKDIV_SET(cr, val) \ 79 1.2 uch ((cr) | (((val) << TX39_CLOCK_SIBMCLKDIV_SHIFT) & \ 80 1.1 uch (TX39_CLOCK_SIBMCLKDIV_MASK << TX39_CLOCK_SIBMCLKDIV_SHIFT))) 81 1.1 uch 82 1.1 uch #define TX39_CLOCK_CSERSEL 0x00000080 83 1.1 uch 84 1.1 uch #define TX39_CLOCK_CSERDIV_SHIFT 4 85 1.1 uch #define TX39_CLOCK_CSERDIV_MASK 0x7 86 1.2 uch #define TX39_CLOCK_CSERDIV(cr) \ 87 1.2 uch (((cr) >> TX39_CLOCK_CSERDIV_SHIFT) & \ 88 1.1 uch TX39_CLOCK_CSERDIV_MASK) 89 1.2 uch #define TX39_CLOCK_CSERDIV_SET(cr, val) \ 90 1.2 uch ((cr) | (((val) << TX39_CLOCK_CSERDIV_SHIFT) & \ 91 1.1 uch (TX39_CLOCK_CSERDIV_MASK << TX39_CLOCK_CSERDIV_SHIFT))) 92 1.1 uch 93 1.2 uch #define TX39_CLOCK_ENCSERCLK 0x00000008 94 1.2 uch #define TX39_CLOCK_ENIRCLK 0x00000004 95 1.2 uch #define TX39_CLOCK_ENUARTACLK 0x00000002 96 1.2 uch #define TX39_CLOCK_ENUARTBCLK 0x00000001 97
Indexes created Wed Nov 05 01:09:58 GMT 2025