tx39icu.c revision 1.1
1 /* $NetBSD: tx39icu.c,v 1.1 1999/11/20 19:56:33 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include "opt_tx39_debug.h" 29 #include "opt_use_poll.h" 30 #include "opt_tx39icudebug.h" 31 #include "opt_tx39_watchdogtimer.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/malloc.h> 37 #include <sys/queue.h> 38 #define TAILQ_FOREACH(var, head, field) \ 39 for (var = TAILQ_FIRST(head); var; var = TAILQ_NEXT(var, field)) 40 #define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) 41 42 #include <mips/cpuregs.h> 43 #include <machine/bus.h> 44 45 #include <hpcmips/tx/tx39var.h> 46 #include <hpcmips/tx/tx39icureg.h> 47 48 #include <machine/clock_machdep.h> 49 #include <machine/cpu.h> 50 #include <dev/dec/clockvar.h> 51 52 #undef TX39ICUDEBUG_PRINT_PENDING_INTERRUPT /* For explorer. good luck! */ 53 54 #ifdef TX39ICUDEBUG 55 #define DPRINTF(arg) printf arg 56 #else 57 #define DPRINTF(arg) 58 #endif 59 u_int32_t tx39intrvec; /* debug use */ 60 61 /* IRQHIGH lines list */ 62 static struct irqhigh_list { 63 int qh_pri; /* IRQHIGH priority */ 64 int qh_set; /* Register set */ 65 int qh_bit; /* bit offset in the register set */ 66 } irqhigh_list[] = { 67 {15, 5, 25}, /* POSPWROKINT */ 68 {15, 5, 24}, /* NEGPWROKINT */ 69 {14, 5, 30}, /* ALARMINT*/ 70 {13, 5, 29}, /* PERINT */ 71 #ifdef TX391X 72 {12, 2, 3}, /* MBUSPOSINT */ 73 {12, 2, 2}, /* MBUSNEGINT */ 74 {11, 2, 31}, /* UARTARXINT */ 75 {10, 2, 21}, /* UARTBRXINT */ 76 {9, 3, 19}, /* MFIOPOSINT19 */ 77 {9, 3, 18}, /* MFIOPOSINT18 */ 78 {9, 3, 17}, /* MFIOPOSINT17 */ 79 {9, 3, 16}, /* MFIOPOSINT16 */ 80 {8, 3, 1}, /* MFIOPOSINT1 */ 81 {8, 3, 0}, /* MFIOPOSINT0 */ 82 {8, 5, 13}, /* IOPOSINT6 */ 83 {8, 5, 12}, /* IOPOSINT5 */ 84 {7, 4, 19}, /* MFIONEGINT19 */ 85 {7, 4, 18}, /* MFIONEGINT18 */ 86 {7, 4, 17}, /* MFIONEGINT17 */ 87 {7, 4, 16}, /* MFIONEGINT16 */ 88 {6, 4, 1}, /* MFIONEGINT1 */ 89 {6, 4, 0}, /* MFIONEGINT0 */ 90 {6, 5, 6}, /* IONEGINT6 */ 91 {6, 5, 5}, /* IONEGINT5 */ 92 {5, 2, 5}, /* MBUSDMAFULLINT */ 93 #endif /* TX391X */ 94 #ifdef TX392X 95 {12, 2, 31}, /* UARTARXINT */ 96 {12, 2, 21}, /* UARTBRXINT */ 97 {11, 3, 19}, /* MFIOPOSINT19 */ 98 {11, 3, 18}, /* MFIOPOSINT18 */ 99 {11, 3, 17}, /* MFIOPOSINT17 */ 100 {11, 3, 16}, /* MFIOPOSINT16 */ 101 {10, 3, 1}, /* MFIOPOSINT1 */ 102 {10, 3, 0}, /* MFIOPOSINT0 */ 103 {10, 5, 13}, /* IOPOSINT6 */ 104 {10, 5, 12}, /* IOPOSINT5 */ 105 {9, 4, 19}, /* MFIONEGINT19 */ 106 {9, 4, 18}, /* MFIONEGINT18 */ 107 {9, 4, 17}, /* MFIONEGINT17 */ 108 {9, 4, 16}, /* MFIONEGINT16 */ 109 {8, 4, 1}, /* MFIONEGINT1 */ 110 {8, 4, 0}, /* MFIONEGINT0 */ 111 {8, 5, 6}, /* IONEGINT6 */ 112 {8, 5, 5}, /* IONEGINT5 */ 113 {5, 7, 19}, /* IRRXCINT */ 114 {5, 7, 17}, /* IRRXEINT */ 115 #endif /* TX392X */ 116 {4, 1, 18}, /* SNDDMACNTINT */ 117 {3, 1, 17}, /* TELDMACNTINT */ 118 {2, 1, 27}, /* CHIDMACNTINT */ 119 {1, 5, 7}, /* IOPOSINT0 */ 120 {1, 5, 0} /* IONEGINT0 */ 121 }; 122 123 struct txintr_high_entry { 124 int he_set; 125 txreg_t he_mask; 126 int (*he_fun) __P((void*)); 127 void *he_arg; 128 TAILQ_ENTRY(txintr_high_entry) he_link; 129 }; 130 131 #ifdef USE_POLL 132 struct txpoll_entry{ 133 int p_cnt; /* dispatch interval */ 134 int p_desc; 135 int (*p_fun) __P((void*)); 136 void *p_arg; 137 TAILQ_ENTRY(txpoll_entry) p_link; 138 }; 139 int tx39_poll_intr __P((void*)); 140 #endif /* USE_POLL */ 141 142 struct tx39icu_softc { 143 struct device sc_dev; 144 tx_chipset_tag_t sc_tc; 145 /* IRQLOW */ 146 txreg_t sc_le_mask[TX39_INTRSET_MAX + 1]; 147 int (*sc_le_fun[TX39_INTRSET_MAX + 1][32]) __P((void*)); 148 void *sc_le_arg[TX39_INTRSET_MAX + 1][32]; 149 /* IRQHIGH */ 150 TAILQ_HEAD(, txintr_high_entry) sc_he_head[TX39_IRQHIGH_MAX]; 151 /* Register */ 152 txreg_t sc_regs[TX39_INTRSET_MAX + 1]; 153 #ifdef USE_POLL 154 unsigned sc_pollcnt; 155 int sc_polling; 156 void *sc_poll_ih; 157 TAILQ_HEAD(, txpoll_entry) sc_p_head; 158 #endif /* USE_POLL */ 159 }; 160 161 int tx39icu_match __P((struct device*, struct cfdata*, void*)); 162 void tx39icu_attach __P((struct device*, struct device*, void*)); 163 int tx39icu_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t)); 164 165 void tx39_intr_dump __P((struct tx39icu_softc*)); 166 void tx39_intr_decode __P((int, int*, int*)); 167 void tx39_irqhigh_disestablish __P((tx_chipset_tag_t, int, int, int)); 168 void tx39_irqhigh_establish __P((tx_chipset_tag_t, int, int, int, int (*) __P((void*)), void*)); 169 void tx39_irqhigh_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t)); 170 int tx39_irqhigh __P((int, int)); 171 172 struct cfattach tx39icu_ca = { 173 sizeof(struct tx39icu_softc), tx39icu_match, tx39icu_attach 174 }; 175 176 int 177 tx39icu_match(parent, cf, aux) 178 struct device *parent; 179 struct cfdata *cf; 180 void *aux; 181 { 182 return 2; /* 1st attach group of txsim */ 183 } 184 185 void 186 tx39icu_attach(parent, self, aux) 187 struct device *parent; 188 struct device *self; 189 void *aux; 190 { 191 struct txsim_attach_args *ta = aux; 192 struct tx39icu_softc *sc = (void*)self; 193 tx_chipset_tag_t tc = ta->ta_tc; 194 txreg_t reg; 195 int i; 196 197 printf("\n"); 198 sc->sc_tc = ta->ta_tc; 199 200 201 printf("\t[Windows CE setting]\n"); 202 sc->sc_regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 203 sc->sc_regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 204 sc->sc_regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 205 sc->sc_regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 206 sc->sc_regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 207 sc->sc_regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 208 #ifdef TX392X 209 sc->sc_regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 210 sc->sc_regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 211 #endif 212 tx39_intr_dump(sc); 213 #ifdef WINCE_DEFAULT_SETTING 214 #warning WINCE_DEFAULT_SETTING 215 #else /* WINCE_DEFAULT_SETTING */ 216 /* Disable IRQLOW */ 217 tx_conf_write(tc, TX39_INTRENABLE1_REG, 0); 218 tx_conf_write(tc, TX39_INTRENABLE2_REG, 0); 219 tx_conf_write(tc, TX39_INTRENABLE3_REG, 0); 220 tx_conf_write(tc, TX39_INTRENABLE4_REG, 0); 221 tx_conf_write(tc, TX39_INTRENABLE5_REG, 0); 222 #ifdef TX392X 223 tx_conf_write(tc, TX39_INTRENABLE7_REG, 0); 224 tx_conf_write(tc, TX39_INTRENABLE8_REG, 0); 225 #endif /* TX392X */ 226 227 /* Disable IRQHIGH */ 228 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 229 reg &= ~TX39_INTRENABLE6_PRIORITYMASK_MASK; 230 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 231 #endif /* WINCE_DEFAULT_SETTING */ 232 233 /* Clear all pending interrupts */ 234 tx_conf_write(tc, TX39_INTRCLEAR1_REG, tx_conf_read(tc, TX39_INTRSTATUS1_REG)); 235 tx_conf_write(tc, TX39_INTRCLEAR2_REG, tx_conf_read(tc, TX39_INTRSTATUS2_REG)); 236 tx_conf_write(tc, TX39_INTRCLEAR3_REG, tx_conf_read(tc, TX39_INTRSTATUS3_REG)); 237 tx_conf_write(tc, TX39_INTRCLEAR4_REG, tx_conf_read(tc, TX39_INTRSTATUS4_REG)); 238 tx_conf_write(tc, TX39_INTRCLEAR5_REG, tx_conf_read(tc, TX39_INTRSTATUS5_REG)); 239 #ifdef TX392X 240 tx_conf_write(tc, TX39_INTRCLEAR7_REG, tx_conf_read(tc, TX39_INTRSTATUS7_REG)); 241 tx_conf_write(tc, TX39_INTRCLEAR8_REG, tx_conf_read(tc, TX39_INTRSTATUS8_REG)); 242 #endif /* TX392X */ 243 244 /* Enable global interrupts */ 245 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 246 reg |= TX39_INTRENABLE6_GLOBALEN; 247 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 248 249 /* Initialize IRQHIGH interrupt handler holder*/ 250 for (i = 0; i < TX39_IRQHIGH_MAX; i++) { 251 TAILQ_INIT(&sc->sc_he_head[i]); 252 } 253 #ifdef USE_POLL 254 /* Initialize polling handler holder */ 255 TAILQ_INIT(&sc->sc_p_head); 256 #endif /* USE_POLL */ 257 258 /* Register interrupt module myself */ 259 tx_conf_register_intr(tc, self); 260 } 261 262 int 263 tx39icu_intr(mask, pc, status, cause) 264 u_int32_t mask; 265 u_int32_t pc; 266 u_int32_t status; 267 u_int32_t cause; 268 { 269 struct tx39icu_softc *sc; 270 tx_chipset_tag_t tc; 271 txreg_t reg, pend; 272 int i, j; 273 274 tc = tx_conf_get_tag(); 275 sc = tc->tc_intrt; 276 /* 277 * Read regsiter ASAP 278 */ 279 sc->sc_regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 280 sc->sc_regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 281 sc->sc_regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 282 sc->sc_regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 283 sc->sc_regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 284 sc->sc_regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 285 #ifdef TX392X 286 sc->sc_regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 287 sc->sc_regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 288 #endif 289 290 #ifdef TX39ICUDEBUG 291 if (!(mask & MIPS_INT_MASK_4) && !(mask & MIPS_INT_MASK_2)) { 292 bitdisp(mask); 293 panic("bogus HwInt"); 294 } 295 #ifdef TX39_DEBUG 296 if (tx39debugflag) { 297 tx39_intr_dump(sc); 298 } 299 #endif 300 #endif /* TX39ICUDEBUG */ 301 302 /* IRQHIGH */ 303 if (mask & MIPS_INT_MASK_4) { 304 tx39_irqhigh_intr(mask, pc, status, cause); 305 } 306 307 /* IRQLOW */ 308 if (mask & MIPS_INT_MASK_2) { 309 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 310 int ofs; 311 #ifdef TX392X 312 if (i == 6) 313 continue; 314 #endif /* TX392X */ 315 ofs = TX39_INTRSTATUS_REG(i); 316 pend = sc->sc_regs[i]; 317 reg = sc->sc_le_mask[i] & pend; 318 /* Clear interrupts */ 319 tx_conf_write(tc, ofs, reg); 320 /* Dispatch handler */ 321 for (j = 0 ; j < 32; j++) { 322 if ((reg & (1 << j)) && 323 sc->sc_le_fun[i][j]) { 324 #ifdef TX39_DEBUG 325 tx39intrvec = (i << 16) | j; 326 if (tx39debugflag) { 327 DPRINTF(("IRQLOW %d:%d\n", 328 i, j)); 329 } 330 #endif /* TX39_DEBUG */ 331 (*sc->sc_le_fun[i][j]) 332 (sc->sc_le_arg[i][j]); 333 334 } 335 } 336 #ifdef TX39ICUDEBUG_PRINT_PENDING_INTERRUPT 337 pend &= ~reg; 338 if (pend) { 339 printf("%d pending:", i); 340 __bitdisp(pend, 0, 31, 0, 1); 341 } 342 #endif 343 344 } 345 } 346 #ifdef TX39_WATCHDOGTIMER 347 /* Bus error (If watch dog timer is enabled)*/ 348 if (mask & MIPS_INT_MASK_1) { 349 tx39biu_intr(0); /* Clear bus error */ 350 } 351 #endif 352 return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 353 } 354 355 int 356 tx39_irqhigh(set, bit) 357 int set, bit; 358 { 359 int i, n; 360 361 n = sizeof irqhigh_list / sizeof (struct irqhigh_list); 362 for (i = 0; i < n; i++) { 363 if (irqhigh_list[i].qh_set == set && 364 irqhigh_list[i].qh_bit == bit) 365 return irqhigh_list[i].qh_pri; 366 } 367 368 return 0; 369 } 370 371 void 372 tx39_irqhigh_intr(mask, pc, status, cause) 373 u_int32_t mask; 374 u_int32_t pc; 375 u_int32_t status; 376 u_int32_t cause; 377 { 378 struct txintr_high_entry *he; 379 struct tx39icu_softc *sc; 380 struct clockframe cf; 381 tx_chipset_tag_t tc; 382 int i, pri, ofs, set; 383 txreg_t he_mask; 384 385 tc = tx_conf_get_tag(); 386 sc = tc->tc_intrt; 387 pri = TX39_INTRSTATUS6_INTVECT(sc->sc_regs[0]); 388 389 if (pri == TX39_INTRPRI13_TIMER_PERIODIC) { 390 cf.pc = pc; 391 cf.sr = status; 392 hardclock(&cf); 393 tx_conf_write(tc, TX39_INTRCLEAR5_REG, 394 TX39_INTRSTATUS5_PERINT); 395 } 396 /* Handle all pending IRQHIGH interrupts */ 397 for (i = pri; i > 0; i--) { 398 TAILQ_FOREACH(he, &sc->sc_he_head[i], he_link) { 399 set = he->he_set; 400 he_mask = he->he_mask; 401 if (he_mask & (sc->sc_regs[set])) { 402 ofs = TX39_INTRSTATUS_REG(set); 403 /* Clear interrupt */ 404 tx_conf_write(tc, ofs, he_mask); 405 #ifdef TX39_DEBUG 406 tx39intrvec = (set << 16) | 407 (ffs(he_mask) - 1); 408 if (tx39debugflag) { 409 DPRINTF(("IRQHIGH: %d:%d\n", 410 set, ffs(he_mask) - 1)); 411 } 412 #endif /* TX39_DEBUG */ 413 /* Dispatch handler */ 414 (*he->he_fun)(he->he_arg); 415 } 416 } 417 } 418 } 419 420 void 421 tx39_intr_decode(intr, set, bit) 422 int intr; 423 int *set; 424 int *bit; 425 { 426 if (!intr || intr >= (TX39_INTRSET_MAX + 1) * 32 427 #ifdef TX392X 428 || intr == 6 429 #endif /* TX392X */ 430 ) { 431 panic("tx39icu_decode: bogus intrrupt line. %d", intr); 432 } 433 *set = intr / 32; 434 *bit = intr % 32; 435 } 436 437 void 438 tx39_irqhigh_establish(tc, set, bit, pri, ih_fun, ih_arg) 439 tx_chipset_tag_t tc; 440 int set; 441 int bit; 442 int pri; 443 int (*ih_fun) __P((void*)); 444 void *ih_arg; 445 { 446 struct tx39icu_softc *sc; 447 struct txintr_high_entry *he; 448 txreg_t reg; 449 450 sc = tc->tc_intrt; 451 /* 452 * Add new entry to `pri' priority. 453 */ 454 if (!(he = malloc(sizeof(struct txintr_high_entry), 455 M_DEVBUF, M_NOWAIT))) { 456 panic ("tx39_irqhigh_establish: no memory."); 457 } 458 memset(he, 0, sizeof(struct txintr_high_entry)); 459 he->he_set = set; 460 he->he_mask= (1 << bit); 461 he->he_fun = ih_fun; 462 he->he_arg = ih_arg; 463 TAILQ_INSERT_TAIL(&sc->sc_he_head[pri], he, he_link); 464 /* 465 * Enable interrupt on this priority. 466 */ 467 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 468 reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, (1 << pri)); 469 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 470 } 471 472 void 473 tx39_irqhigh_disestablish(tc, set, bit, pri) 474 tx_chipset_tag_t tc; 475 int set, bit, pri; 476 { 477 struct tx39icu_softc *sc; 478 struct txintr_high_entry *he; 479 txreg_t reg; 480 481 sc = tc->tc_intrt; 482 TAILQ_FOREACH(he, &sc->sc_he_head[pri], he_link) { 483 if (he->he_set == set && he->he_mask == (1 << bit)) { 484 TAILQ_REMOVE(&sc->sc_he_head[pri], he, he_link); 485 free(he, M_DEVBUF); 486 break; 487 } 488 } 489 490 if (TAILQ_EMPTY(&sc->sc_he_head[pri])) { 491 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 492 reg &= ~(1 << pri); 493 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 494 } 495 } 496 497 498 void* 499 tx_intr_establish(tc, line, mode, level, ih_fun, ih_arg) 500 tx_chipset_tag_t tc; 501 int line; 502 int mode; /* Trigger setting. but TX39 handles edge only. */ 503 int level; /* XXX not yet */ 504 int (*ih_fun) __P((void*)); 505 void *ih_arg; 506 { 507 struct tx39icu_softc *sc; 508 txreg_t reg; 509 int bit, set, highpri, ofs; 510 511 sc = tc->tc_intrt; 512 513 tx39_intr_decode(line, &set, &bit); 514 515 sc->sc_le_fun[set][bit] = ih_fun; 516 sc->sc_le_arg[set][bit] = ih_arg; 517 DPRINTF(("tx_intr_establish: %d:%d", set, bit)); 518 519 if ((highpri = tx39_irqhigh(set, bit))) { 520 tx39_irqhigh_establish(tc, set, bit, highpri, 521 ih_fun, ih_arg); 522 DPRINTF(("(high)\n")); 523 } else { 524 /* Set mask for acknowledge. */ 525 sc->sc_le_mask[set] |= (1 << bit); 526 /* Enable interrupt */ 527 ofs = TX39_INTRENABLE_REG(set); 528 reg = tx_conf_read(tc, ofs); 529 reg |= (1 << bit); 530 tx_conf_write(tc, ofs, reg); 531 DPRINTF(("(low)\n")); 532 } 533 534 return (void*)line; 535 } 536 537 void 538 tx_intr_disestablish(tc, arg) 539 tx_chipset_tag_t tc; 540 void *arg; 541 { 542 struct tx39icu_softc *sc; 543 int set, bit, highpri, ofs; 544 txreg_t reg; 545 546 sc = tc->tc_intrt; 547 548 tx39_intr_decode((int)arg, &set, &bit); 549 DPRINTF(("tx_intr_disestablish: %d:%d", set, bit)); 550 551 if ((highpri = tx39_irqhigh(set, bit))) { 552 tx39_irqhigh_disestablish(tc, set, bit, highpri); 553 DPRINTF(("(high)\n")); 554 } else { 555 sc->sc_le_fun[set][bit] = 0; 556 sc->sc_le_arg[set][bit] = 0; 557 sc->sc_le_mask[set] &= ~(1 << bit); 558 ofs = TX39_INTRENABLE_REG(set); 559 reg = tx_conf_read(tc, ofs); 560 reg &= ~(1 << bit); 561 tx_conf_write(tc, ofs, reg); 562 DPRINTF(("(low)\n")); 563 } 564 } 565 566 void 567 tx39_intr_dump(sc) 568 struct tx39icu_softc *sc; 569 { 570 tx_chipset_tag_t tc = sc->sc_tc; 571 int i, j, ofs; 572 txreg_t reg; 573 char msg[16]; 574 575 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 576 #ifdef TX392X 577 if (i == 6) 578 continue; 579 #endif /* TX392X */ 580 for (reg = j = 0; j < 32; j++) { 581 if (tx39_irqhigh(i, j)) { 582 reg |= (1 << j); 583 } 584 } 585 sprintf(msg, "%d high", i); 586 __bitdisp(reg, 32, 0, msg, 1); 587 sprintf(msg, "%d status", i); 588 __bitdisp(sc->sc_regs[i], 0, 31, msg, 1); 589 ofs = TX39_INTRENABLE_REG(i); 590 reg = tx_conf_read(tc, ofs); 591 sprintf(msg, "%d enable", i); 592 __bitdisp(reg, 0, 31, msg, 1); 593 } 594 reg = sc->sc_regs[0]; 595 printf("<%s><%s> vector=%2d\t\t[6 status]\n", 596 reg & TX39_INTRSTATUS6_IRQHIGH ? "HI" : "--", 597 reg & TX39_INTRSTATUS6_IRQLOW ? "LO" : "--", 598 TX39_INTRSTATUS6_INTVECT(reg)); 599 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 600 __bitdisp(reg, 0, 18, "6 enable", 1); 601 602 } 603 604 #ifdef USE_POLL 605 void* 606 tx39_poll_establish(tc, interval, mode, level, ih_fun, ih_arg) 607 tx_chipset_tag_t tc; 608 int interval; 609 int mode; /* Trigger setting. but TX39 handles edge only. */ 610 int level; /* XXX not yet */ 611 int (*ih_fun) __P((void*)); 612 void *ih_arg; 613 { 614 struct tx39icu_softc *sc; 615 struct txpoll_entry *p; 616 617 sc = tc->tc_intrt; 618 619 if (!(p = malloc(sizeof(struct txpoll_entry), 620 M_DEVBUF, M_NOWAIT))) { 621 panic ("tx39_poll_establish: no memory."); 622 } 623 memset(p, 0, sizeof(struct txpoll_entry)); 624 625 p->p_fun = ih_fun; 626 p->p_arg = ih_arg; 627 p->p_cnt = interval; 628 if (!sc->sc_polling) { 629 /* Hook VSync : TX39_INTRSTATUS1_LCDINT*/ 630 if (!(sc->sc_poll_ih = 631 tx_intr_establish( 632 tc, MAKEINTR(1, TX39_INTRSTATUS1_LCDINT), 633 mode, level, tx39_poll_intr, sc))) { 634 printf("tx39_poll_establish: can't hook\n"); 635 return 0; 636 } 637 } 638 sc->sc_polling++; 639 p->p_desc = sc->sc_polling; 640 TAILQ_INSERT_TAIL(&sc->sc_p_head, p, p_link); 641 642 return (void*)p->p_desc; 643 } 644 645 void 646 tx39_poll_disestablish(tc, arg) 647 tx_chipset_tag_t tc; 648 void *arg; 649 { 650 struct tx39icu_softc *sc; 651 struct txpoll_entry *p; 652 int desc; 653 sc = tc->tc_intrt; 654 655 desc = (int)arg; 656 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 657 if (p->p_desc == desc) { 658 TAILQ_REMOVE(&sc->sc_p_head, p, p_link); 659 free(p, M_DEVBUF); 660 break; 661 } 662 } 663 if (TAILQ_EMPTY(&sc->sc_p_head)) { 664 sc->sc_polling = 0; 665 tx_intr_disestablish(tc, sc->sc_poll_ih); 666 } 667 } 668 669 int 670 tx39_poll_intr(arg) 671 void *arg; 672 { 673 struct tx39icu_softc *sc = arg; 674 struct txpoll_entry *p; 675 676 if (!sc->sc_polling) { 677 return 0; 678 } 679 sc->sc_pollcnt++; 680 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 681 if (sc->sc_pollcnt % p->p_cnt == 0) { 682 (*p->p_fun)(p->p_arg); 683 } 684 } 685 return 0; 686 } 687 #endif /* USE_POLL */ 688
Indexes created Fri Oct 31 11:10:07 GMT 2025