tx39icu.c revision 1.14
1 /* $NetBSD: tx39icu.c,v 1.14 2001/09/23 14:32:53 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_vr41xx.h" 40 #include "opt_tx39xx.h" 41 42 #include "opt_tx39_debug.h" 43 #include "opt_use_poll.h" 44 #include "opt_tx39icudebug.h" 45 #include "opt_tx39_watchdogtimer.h" 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/device.h> 50 #include <sys/malloc.h> 51 #include <sys/queue.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #include <mips/cpuregs.h> 56 #include <machine/bus.h> 57 58 #include <hpcmips/tx/tx39var.h> 59 #include <hpcmips/tx/tx39icureg.h> 60 #include <hpcmips/tx/tx39clockvar.h> 61 62 #include <machine/cpu.h> 63 #include <dev/dec/clockvar.h> 64 65 #undef TX39ICUDEBUG_PRINT_PENDING_INTERRUPT /* For explorer. good luck! */ 66 67 #if defined(VR41XX) && defined(TX39XX) 68 #define TX_INTR tx_intr 69 #else 70 #define TX_INTR cpu_intr /* locore_mips3 directly call this */ 71 #endif 72 73 #ifdef TX39ICUDEBUG 74 #define DPRINTF(arg) printf arg 75 #else 76 #define DPRINTF(arg) 77 #endif 78 u_int32_t tx39intrvec; 79 80 /* 81 * This is a mask of bits to clear in the SR when we go to a 82 * given interrupt priority level. 83 */ 84 const u_int32_t __ipl_sr_bits_tx[_IPL_N] = { 85 0, /* IPL_NONE */ 86 87 MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */ 88 89 MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */ 90 91 MIPS_SOFT_INT_MASK_0| 92 MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */ 93 94 MIPS_SOFT_INT_MASK_0| 95 MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */ 96 97 MIPS_SOFT_INT_MASK_0| 98 MIPS_SOFT_INT_MASK_1| 99 MIPS_INT_MASK_2| 100 MIPS_INT_MASK_4, /* IPL_BIO */ 101 102 MIPS_SOFT_INT_MASK_0| 103 MIPS_SOFT_INT_MASK_1| 104 MIPS_INT_MASK_2| 105 MIPS_INT_MASK_4, /* IPL_NET */ 106 107 MIPS_SOFT_INT_MASK_0| 108 MIPS_SOFT_INT_MASK_1| 109 MIPS_INT_MASK_2| 110 MIPS_INT_MASK_4, /* IPL_{TTY,SERIAL} */ 111 112 MIPS_SOFT_INT_MASK_0| 113 MIPS_SOFT_INT_MASK_1| 114 MIPS_INT_MASK_2| 115 MIPS_INT_MASK_4, /* IPL_{CLOCK,HIGH} */ 116 }; 117 118 /* IRQHIGH lines list */ 119 static const struct irqhigh_list { 120 int qh_pri; /* IRQHIGH priority */ 121 int qh_set; /* Register set */ 122 int qh_bit; /* bit offset in the register set */ 123 } irqhigh_list[] = { 124 {15, 5, 25}, /* POSPWROKINT */ 125 {15, 5, 24}, /* NEGPWROKINT */ 126 {14, 5, 30}, /* ALARMINT*/ 127 {13, 5, 29}, /* PERINT */ 128 #ifdef TX391X 129 {12, 2, 3}, /* MBUSPOSINT */ 130 {12, 2, 2}, /* MBUSNEGINT */ 131 {11, 2, 31}, /* UARTARXINT */ 132 {10, 2, 21}, /* UARTBRXINT */ 133 {9, 3, 19}, /* MFIOPOSINT19 */ 134 {9, 3, 18}, /* MFIOPOSINT18 */ 135 {9, 3, 17}, /* MFIOPOSINT17 */ 136 {9, 3, 16}, /* MFIOPOSINT16 */ 137 {8, 3, 1}, /* MFIOPOSINT1 */ 138 {8, 3, 0}, /* MFIOPOSINT0 */ 139 {8, 5, 13}, /* IOPOSINT6 */ 140 {8, 5, 12}, /* IOPOSINT5 */ 141 {7, 4, 19}, /* MFIONEGINT19 */ 142 {7, 4, 18}, /* MFIONEGINT18 */ 143 {7, 4, 17}, /* MFIONEGINT17 */ 144 {7, 4, 16}, /* MFIONEGINT16 */ 145 {6, 4, 1}, /* MFIONEGINT1 */ 146 {6, 4, 0}, /* MFIONEGINT0 */ 147 {6, 5, 6}, /* IONEGINT6 */ 148 {6, 5, 5}, /* IONEGINT5 */ 149 {5, 2, 5}, /* MBUSDMAFULLINT */ 150 #endif /* TX391X */ 151 #ifdef TX392X 152 {12, 2, 31}, /* UARTARXINT */ 153 {12, 2, 21}, /* UARTBRXINT */ 154 {11, 3, 19}, /* MFIOPOSINT19 */ 155 {11, 3, 18}, /* MFIOPOSINT18 */ 156 {11, 3, 17}, /* MFIOPOSINT17 */ 157 {11, 3, 16}, /* MFIOPOSINT16 */ 158 {10, 3, 1}, /* MFIOPOSINT1 */ 159 {10, 3, 0}, /* MFIOPOSINT0 */ 160 {10, 5, 13}, /* IOPOSINT6 */ 161 {10, 5, 12}, /* IOPOSINT5 */ 162 {9, 4, 19}, /* MFIONEGINT19 */ 163 {9, 4, 18}, /* MFIONEGINT18 */ 164 {9, 4, 17}, /* MFIONEGINT17 */ 165 {9, 4, 16}, /* MFIONEGINT16 */ 166 {8, 4, 1}, /* MFIONEGINT1 */ 167 {8, 4, 0}, /* MFIONEGINT0 */ 168 {8, 5, 6}, /* IONEGINT6 */ 169 {8, 5, 5}, /* IONEGINT5 */ 170 {5, 7, 19}, /* IRRXCINT */ 171 {5, 7, 17}, /* IRRXEINT */ 172 #endif /* TX392X */ 173 {4, 1, 18}, /* SNDDMACNTINT */ 174 {3, 1, 17}, /* TELDMACNTINT */ 175 {2, 1, 27}, /* CHIDMACNTINT */ 176 {1, 5, 7}, /* IOPOSINT0 */ 177 {1, 5, 0} /* IONEGINT0 */ 178 }; 179 180 struct txintr_high_entry { 181 int he_set; 182 txreg_t he_mask; 183 int (*he_fun)(void *); 184 void *he_arg; 185 TAILQ_ENTRY(txintr_high_entry) he_link; 186 }; 187 188 #ifdef USE_POLL 189 struct txpoll_entry{ 190 int p_cnt; /* dispatch interval */ 191 int p_desc; 192 int (*p_fun)(void *); 193 void *p_arg; 194 TAILQ_ENTRY(txpoll_entry) p_link; 195 }; 196 int tx39_poll_intr(void *); 197 #endif /* USE_POLL */ 198 199 struct tx39icu_softc { 200 struct device sc_dev; 201 tx_chipset_tag_t sc_tc; 202 /* IRQLOW */ 203 txreg_t sc_le_mask[TX39_INTRSET_MAX + 1]; 204 int (*sc_le_fun[TX39_INTRSET_MAX + 1][32])(void *); 205 void *sc_le_arg[TX39_INTRSET_MAX + 1][32]; 206 /* IRQHIGH */ 207 TAILQ_HEAD(, txintr_high_entry) sc_he_head[TX39_IRQHIGH_MAX]; 208 /* Register */ 209 txreg_t sc_regs[TX39_INTRSET_MAX + 1]; 210 #ifdef USE_POLL 211 unsigned sc_pollcnt; 212 int sc_polling; 213 void *sc_poll_ih; 214 TAILQ_HEAD(, txpoll_entry) sc_p_head; 215 #endif /* USE_POLL */ 216 }; 217 218 int tx39icu_match(struct device *, struct cfdata *, void *); 219 void tx39icu_attach(struct device *, struct device *, void *); 220 int tx39icu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 221 222 void tx39_intr_dump(struct tx39icu_softc *); 223 void tx39_intr_decode(int, int *, int *); 224 void tx39_irqhigh_disestablish(tx_chipset_tag_t, int, int, int); 225 void tx39_irqhigh_establish(tx_chipset_tag_t, int, int, int, 226 int (*)(void *), void *); 227 void tx39_irqhigh_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 228 int tx39_irqhigh(int, int); 229 230 struct cfattach tx39icu_ca = { 231 sizeof(struct tx39icu_softc), tx39icu_match, tx39icu_attach 232 }; 233 234 int 235 tx39icu_match(struct device *parent, struct cfdata *cf, void *aux) 236 { 237 238 return (ATTACH_FIRST); 239 } 240 241 void 242 tx39icu_attach(struct device *parent, struct device *self, void *aux) 243 { 244 struct txsim_attach_args *ta = aux; 245 struct tx39icu_softc *sc = (void *)self; 246 tx_chipset_tag_t tc = ta->ta_tc; 247 txreg_t reg, *regs; 248 int i; 249 250 printf("\n"); 251 sc->sc_tc = ta->ta_tc; 252 253 regs = sc->sc_regs; 254 regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 255 regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 256 regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 257 regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 258 regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 259 regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 260 #ifdef TX392X 261 regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 262 regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 263 #endif 264 #ifdef TX39ICUDEBUG 265 printf("\t[Windows CE setting]\n"); 266 tx39_intr_dump(sc); 267 #endif /* TX39ICUDEBUG */ 268 269 #ifdef WINCE_DEFAULT_SETTING 270 #warning WINCE_DEFAULT_SETTING 271 #else /* WINCE_DEFAULT_SETTING */ 272 /* Disable IRQLOW */ 273 tx_conf_write(tc, TX39_INTRENABLE1_REG, 0); 274 tx_conf_write(tc, TX39_INTRENABLE2_REG, 0); 275 tx_conf_write(tc, TX39_INTRENABLE3_REG, 0); 276 tx_conf_write(tc, TX39_INTRENABLE4_REG, 0); 277 tx_conf_write(tc, TX39_INTRENABLE5_REG, 0); 278 #ifdef TX392X 279 tx_conf_write(tc, TX39_INTRENABLE7_REG, 0); 280 tx_conf_write(tc, TX39_INTRENABLE8_REG, 0); 281 #endif /* TX392X */ 282 283 /* Disable IRQHIGH */ 284 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 285 reg &= ~TX39_INTRENABLE6_PRIORITYMASK_MASK; 286 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 287 #endif /* WINCE_DEFAULT_SETTING */ 288 289 /* Clear all pending interrupts */ 290 tx_conf_write(tc, TX39_INTRCLEAR1_REG, 291 tx_conf_read(tc, TX39_INTRSTATUS1_REG)); 292 tx_conf_write(tc, TX39_INTRCLEAR2_REG, 293 tx_conf_read(tc, TX39_INTRSTATUS2_REG)); 294 tx_conf_write(tc, TX39_INTRCLEAR3_REG, 295 tx_conf_read(tc, TX39_INTRSTATUS3_REG)); 296 tx_conf_write(tc, TX39_INTRCLEAR4_REG, 297 tx_conf_read(tc, TX39_INTRSTATUS4_REG)); 298 tx_conf_write(tc, TX39_INTRCLEAR5_REG, 299 tx_conf_read(tc, TX39_INTRSTATUS5_REG)); 300 #ifdef TX392X 301 tx_conf_write(tc, TX39_INTRCLEAR7_REG, 302 tx_conf_read(tc, TX39_INTRSTATUS7_REG)); 303 tx_conf_write(tc, TX39_INTRCLEAR8_REG, 304 tx_conf_read(tc, TX39_INTRSTATUS8_REG)); 305 #endif /* TX392X */ 306 307 /* Enable global interrupts */ 308 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 309 reg |= TX39_INTRENABLE6_GLOBALEN; 310 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 311 312 /* Initialize IRQHIGH interrupt handler holder*/ 313 for (i = 0; i < TX39_IRQHIGH_MAX; i++) { 314 TAILQ_INIT(&sc->sc_he_head[i]); 315 } 316 #ifdef USE_POLL 317 /* Initialize polling handler holder */ 318 TAILQ_INIT(&sc->sc_p_head); 319 #endif /* USE_POLL */ 320 321 /* Register interrupt module myself */ 322 tx_conf_register_intr(tc, self); 323 } 324 325 void 326 TX_INTR(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending) 327 { 328 struct tx39icu_softc *sc; 329 tx_chipset_tag_t tc; 330 txreg_t reg, pend, *regs; 331 int i, j; 332 333 uvmexp.intrs++; 334 335 if ((ipending & MIPS_HARD_INT_MASK) == 0) 336 goto softintr; 337 338 tc = tx_conf_get_tag(); 339 sc = tc->tc_intrt; 340 /* 341 * Read regsiter ASAP 342 */ 343 regs = sc->sc_regs; 344 regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 345 regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 346 regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 347 regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 348 regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 349 regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 350 #ifdef TX392X 351 regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 352 regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 353 #endif 354 355 #ifdef TX39ICUDEBUG 356 if (!(ipending & MIPS_INT_MASK_4) && !(ipending & MIPS_INT_MASK_2)) { 357 bitdisp(ipending); 358 panic("bogus HwInt"); 359 } 360 #ifdef TX39_DEBUG 361 if (tx39debugflag) { 362 tx39_intr_dump(sc); 363 } 364 #endif 365 #endif /* TX39ICUDEBUG */ 366 367 /* IRQHIGH */ 368 if (ipending & MIPS_INT_MASK_4) { 369 tx39_irqhigh_intr(ipending, pc, status, cause); 370 371 goto softintr; 372 } 373 374 /* IRQLOW */ 375 if (ipending & MIPS_INT_MASK_2) { 376 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 377 int ofs; 378 #ifdef TX392X 379 if (i == 6) 380 continue; 381 #endif /* TX392X */ 382 ofs = TX39_INTRSTATUS_REG(i); 383 pend = sc->sc_regs[i]; 384 reg = sc->sc_le_mask[i] & pend; 385 /* Clear interrupts */ 386 tx_conf_write(tc, ofs, reg); 387 /* Dispatch handler */ 388 for (j = 0 ; j < 32; j++) { 389 if ((reg & (1 << j)) && 390 sc->sc_le_fun[i][j]) { 391 #ifdef TX39_DEBUG 392 tx39intrvec = (i << 16) | j; 393 if (tx39debugflag) { 394 DPRINTF(("IRQLOW %d:%d\n", 395 i, j)); 396 } 397 #endif /* TX39_DEBUG */ 398 (*sc->sc_le_fun[i][j]) 399 (sc->sc_le_arg[i][j]); 400 401 } 402 } 403 #ifdef TX39ICUDEBUG_PRINT_PENDING_INTERRUPT 404 pend &= ~reg; 405 if (pend) { 406 printf("%d pending:", i); 407 __bitdisp(pend, 0, 31, 0, 1); 408 } 409 #endif 410 411 } 412 } 413 #ifdef TX39_WATCHDOGTIMER 414 { 415 extern int tx39biu_intr(void *); 416 /* Bus error (If watch dog timer is enabled)*/ 417 if (ipending & MIPS_INT_MASK_1) { 418 tx39biu_intr(0); /* Clear bus error */ 419 } 420 } 421 #endif 422 #if 0 423 /* reset priority mask */ 424 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 425 reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, 0xffff); 426 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 427 #endif 428 429 softintr: 430 _splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE); 431 432 softintr(ipending); 433 } 434 435 int 436 tx39_irqhigh(int set, int bit) 437 { 438 int i, n; 439 440 n = sizeof irqhigh_list / sizeof (struct irqhigh_list); 441 for (i = 0; i < n; i++) { 442 if (irqhigh_list[i].qh_set == set && 443 irqhigh_list[i].qh_bit == bit) 444 return (irqhigh_list[i].qh_pri); 445 } 446 447 return (0); 448 } 449 450 void 451 tx39_irqhigh_intr(u_int32_t ipending, u_int32_t pc, u_int32_t status, 452 u_int32_t cause) 453 { 454 struct txintr_high_entry *he; 455 struct tx39icu_softc *sc; 456 struct clockframe cf; 457 tx_chipset_tag_t tc; 458 int i, pri, ofs, set; 459 txreg_t he_mask; 460 461 tc = tx_conf_get_tag(); 462 sc = tc->tc_intrt; 463 pri = TX39_INTRSTATUS6_INTVECT(sc->sc_regs[0]); 464 465 if (pri == TX39_INTRPRI13_TIMER_PERIODIC) { 466 tx_conf_write(tc, TX39_INTRCLEAR5_REG, 467 TX39_INTRSTATUS5_PERINT); 468 cf.pc = pc; 469 cf.sr = status; 470 hardclock(&cf); 471 intrcnt[HARDCLOCK]++; 472 473 return; 474 } 475 476 /* Handle all pending IRQHIGH interrupts */ 477 for (i = pri; i > 0; i--) { 478 TAILQ_FOREACH(he, &sc->sc_he_head[i], he_link) { 479 set = he->he_set; 480 he_mask = he->he_mask; 481 if (he_mask & (sc->sc_regs[set])) { 482 ofs = TX39_INTRSTATUS_REG(set); 483 /* Clear interrupt */ 484 tx_conf_write(tc, ofs, he_mask); 485 #ifdef TX39_DEBUG 486 tx39intrvec = (set << 16) | 487 (ffs(he_mask) - 1); 488 if (tx39debugflag) { 489 DPRINTF(("IRQHIGH: %d:%d\n", 490 set, ffs(he_mask) - 1)); 491 } 492 #endif /* TX39_DEBUG */ 493 /* Dispatch handler */ 494 (*he->he_fun)(he->he_arg); 495 } 496 } 497 } 498 } 499 500 void 501 tx39_intr_decode(int intr, int *set, int *bit) 502 { 503 if (!intr || intr >= (TX39_INTRSET_MAX + 1) * 32 504 #ifdef TX392X 505 || intr == 6 506 #endif /* TX392X */ 507 ) { 508 panic("tx39icu_decode: bogus intrrupt line. %d", intr); 509 } 510 *set = intr / 32; 511 *bit = intr % 32; 512 } 513 514 void 515 tx39_irqhigh_establish(tx_chipset_tag_t tc, int set, int bit, int pri, 516 int (*ih_fun)(void *), void *ih_arg) 517 { 518 struct tx39icu_softc *sc; 519 struct txintr_high_entry *he; 520 txreg_t reg; 521 522 sc = tc->tc_intrt; 523 /* 524 * Add new entry to `pri' priority 525 */ 526 if (!(he = malloc(sizeof(struct txintr_high_entry), 527 M_DEVBUF, M_NOWAIT))) { 528 panic ("tx39_irqhigh_establish: no memory."); 529 } 530 memset(he, 0, sizeof(struct txintr_high_entry)); 531 he->he_set = set; 532 he->he_mask= (1 << bit); 533 he->he_fun = ih_fun; 534 he->he_arg = ih_arg; 535 TAILQ_INSERT_TAIL(&sc->sc_he_head[pri], he, he_link); 536 /* 537 * Enable interrupt on this priority. 538 */ 539 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 540 reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, (1 << pri)); 541 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 542 } 543 544 void 545 tx39_irqhigh_disestablish(tx_chipset_tag_t tc, int set, int bit, int pri) 546 { 547 struct tx39icu_softc *sc; 548 struct txintr_high_entry *he; 549 txreg_t reg; 550 551 sc = tc->tc_intrt; 552 TAILQ_FOREACH(he, &sc->sc_he_head[pri], he_link) { 553 if (he->he_set == set && he->he_mask == (1 << bit)) { 554 TAILQ_REMOVE(&sc->sc_he_head[pri], he, he_link); 555 free(he, M_DEVBUF); 556 break; 557 } 558 } 559 560 if (TAILQ_EMPTY(&sc->sc_he_head[pri])) { 561 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 562 reg &= ~(1 << pri); 563 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 564 } 565 } 566 567 568 void * 569 tx_intr_establish(tx_chipset_tag_t tc, int line, int mode, int level, 570 int (*ih_fun)(void *), void *ih_arg) 571 { 572 struct tx39icu_softc *sc; 573 txreg_t reg; 574 int bit, set, highpri, ofs; 575 576 sc = tc->tc_intrt; 577 578 tx39_intr_decode(line, &set, &bit); 579 580 sc->sc_le_fun[set][bit] = ih_fun; 581 sc->sc_le_arg[set][bit] = ih_arg; 582 DPRINTF(("tx_intr_establish: %d:%d", set, bit)); 583 584 if ((highpri = tx39_irqhigh(set, bit))) { 585 tx39_irqhigh_establish(tc, set, bit, highpri, 586 ih_fun, ih_arg); 587 DPRINTF(("(high)\n")); 588 } else { 589 /* Set mask for acknowledge. */ 590 sc->sc_le_mask[set] |= (1 << bit); 591 /* Enable interrupt */ 592 ofs = TX39_INTRENABLE_REG(set); 593 reg = tx_conf_read(tc, ofs); 594 reg |= (1 << bit); 595 tx_conf_write(tc, ofs, reg); 596 DPRINTF(("(low)\n")); 597 } 598 599 return ((void *)line); 600 } 601 602 void 603 tx_intr_disestablish(tx_chipset_tag_t tc, void *arg) 604 { 605 struct tx39icu_softc *sc; 606 int set, bit, highpri, ofs; 607 txreg_t reg; 608 609 sc = tc->tc_intrt; 610 611 tx39_intr_decode((int)arg, &set, &bit); 612 DPRINTF(("tx_intr_disestablish: %d:%d", set, bit)); 613 614 if ((highpri = tx39_irqhigh(set, bit))) { 615 tx39_irqhigh_disestablish(tc, set, bit, highpri); 616 DPRINTF(("(high)\n")); 617 } else { 618 sc->sc_le_fun[set][bit] = 0; 619 sc->sc_le_arg[set][bit] = 0; 620 sc->sc_le_mask[set] &= ~(1 << bit); 621 ofs = TX39_INTRENABLE_REG(set); 622 reg = tx_conf_read(tc, ofs); 623 reg &= ~(1 << bit); 624 tx_conf_write(tc, ofs, reg); 625 DPRINTF(("(low)\n")); 626 } 627 } 628 629 u_int32_t 630 tx_intr_status(tx_chipset_tag_t tc, int r) 631 { 632 struct tx39icu_softc *sc = tc->tc_intrt; 633 634 if (r < 0 || r >= TX39_INTRSET_MAX + 1) 635 panic("tx_intr_status: invalid index %d", r); 636 637 return (u_int32_t)(sc->sc_regs[r]); 638 } 639 640 #ifdef USE_POLL 641 void * 642 tx39_poll_establish(tx_chipset_tag_t tc, int interval, int level, 643 int (*ih_fun)(void *), void *ih_arg) 644 { 645 struct tx39icu_softc *sc; 646 struct txpoll_entry *p; 647 int s; 648 void *ret; 649 650 s = splhigh(); 651 sc = tc->tc_intrt; 652 653 if (!(p = malloc(sizeof(struct txpoll_entry), 654 M_DEVBUF, M_NOWAIT))) { 655 panic ("tx39_poll_establish: no memory."); 656 } 657 memset(p, 0, sizeof(struct txpoll_entry)); 658 659 p->p_fun = ih_fun; 660 p->p_arg = ih_arg; 661 p->p_cnt = interval; 662 663 if (!sc->sc_polling) { 664 tx39clock_alarm_set(tc, 33); /* 33 msec */ 665 666 if (!(sc->sc_poll_ih = 667 tx_intr_establish( 668 tc, MAKEINTR(5, TX39_INTRSTATUS5_ALARMINT), 669 IST_EDGE, level, tx39_poll_intr, sc))) { 670 printf("tx39_poll_establish: can't hook\n"); 671 672 splx(s); 673 return (0); 674 } 675 } 676 677 sc->sc_polling++; 678 p->p_desc = sc->sc_polling; 679 TAILQ_INSERT_TAIL(&sc->sc_p_head, p, p_link); 680 ret = (void *)p->p_desc; 681 682 splx(s); 683 return (ret); 684 } 685 686 void 687 tx39_poll_disestablish(tx_chipset_tag_t tc, void *arg) 688 { 689 struct tx39icu_softc *sc; 690 struct txpoll_entry *p; 691 int s, desc; 692 693 s = splhigh(); 694 sc = tc->tc_intrt; 695 696 desc = (int)arg; 697 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 698 if (p->p_desc == desc) { 699 TAILQ_REMOVE(&sc->sc_p_head, p, p_link); 700 free(p, M_DEVBUF); 701 break; 702 } 703 } 704 705 if (TAILQ_EMPTY(&sc->sc_p_head)) { 706 sc->sc_polling = 0; 707 tx_intr_disestablish(tc, sc->sc_poll_ih); 708 } 709 710 splx(s); 711 return; 712 } 713 714 int 715 tx39_poll_intr(void *arg) 716 { 717 struct tx39icu_softc *sc = arg; 718 struct txpoll_entry *p; 719 720 tx39clock_alarm_refill(sc->sc_tc); 721 722 if (!sc->sc_polling) { 723 return (0); 724 } 725 sc->sc_pollcnt++; 726 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 727 if (sc->sc_pollcnt % p->p_cnt == 0) { 728 if ((*p->p_fun)(p->p_arg) == POLL_END) 729 goto disestablish; 730 } 731 } 732 733 return (0); 734 735 disestablish: 736 TAILQ_REMOVE(&sc->sc_p_head, p, p_link); 737 free(p, M_DEVBUF); 738 if (TAILQ_EMPTY(&sc->sc_p_head)) { 739 sc->sc_polling = 0; 740 tx_intr_disestablish(sc->sc_tc, sc->sc_poll_ih); 741 } 742 743 return (0); 744 } 745 #endif /* USE_POLL */ 746 747 void 748 tx39_intr_dump(struct tx39icu_softc *sc) 749 { 750 tx_chipset_tag_t tc = sc->sc_tc; 751 int i, j, ofs; 752 txreg_t reg; 753 char msg[16]; 754 755 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 756 #ifdef TX392X 757 if (i == 6) 758 continue; 759 #endif /* TX392X */ 760 for (reg = j = 0; j < 32; j++) { 761 if (tx39_irqhigh(i, j)) { 762 reg |= (1 << j); 763 } 764 } 765 sprintf(msg, "%d high", i); 766 __bitdisp(reg, 32, 0, msg, 1); 767 sprintf(msg, "%d status", i); 768 __bitdisp(sc->sc_regs[i], 0, 31, msg, 1); 769 ofs = TX39_INTRENABLE_REG(i); 770 reg = tx_conf_read(tc, ofs); 771 sprintf(msg, "%d enable", i); 772 __bitdisp(reg, 0, 31, msg, 1); 773 } 774 reg = sc->sc_regs[0]; 775 printf("<%s><%s> vector=%2d\t\t[6 status]\n", 776 reg & TX39_INTRSTATUS6_IRQHIGH ? "HI" : "--", 777 reg & TX39_INTRSTATUS6_IRQLOW ? "LO" : "--", 778 TX39_INTRSTATUS6_INTVECT(reg)); 779 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 780 __bitdisp(reg, 0, 18, "6 enable", 1); 781 782 } 783
Indexes created Wed Oct 29 12:09:47 GMT 2025