tx39icu.c revision 1.17
1 /* $NetBSD: tx39icu.c,v 1.17 2002/05/03 07:31:25 takemura Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_vr41xx.h" 40 #include "opt_tx39xx.h" 41 42 #include "opt_use_poll.h" 43 #include "opt_tx39icu_debug.h" 44 #include "opt_tx39_watchdogtimer.h" 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/malloc.h> 50 #include <sys/queue.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <mips/cpuregs.h> 55 #include <machine/bus.h> 56 57 #include <hpcmips/tx/tx39var.h> 58 #include <hpcmips/tx/tx39icureg.h> 59 #include <hpcmips/tx/tx39clockvar.h> 60 61 #include <machine/cpu.h> 62 #include <dev/dec/clockvar.h> 63 64 #undef TX39ICU_DEBUG_PRINT_PENDING_INTERRUPT /* For explorer. good luck! */ 65 66 #if defined(VR41XX) && defined(TX39XX) 67 #define TX_INTR tx_intr 68 #else 69 #define TX_INTR cpu_intr /* locore_mips3 directly call this */ 70 #endif 71 void TX_INTR(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 72 73 #ifdef TX39ICU_DEBUG 74 #define DPRINTF_ENABLE 75 #define DPRINTF_DEBUG tx39icu_debug 76 #endif 77 #include <machine/debug.h> 78 79 u_int32_t tx39intrvec; 80 81 /* 82 * This is a mask of bits to clear in the SR when we go to a 83 * given interrupt priority level. 84 */ 85 const u_int32_t __ipl_sr_bits_tx[_IPL_N] = { 86 0, /* IPL_NONE */ 87 88 MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */ 89 90 MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */ 91 92 MIPS_SOFT_INT_MASK_0| 93 MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */ 94 95 MIPS_SOFT_INT_MASK_0| 96 MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */ 97 98 MIPS_SOFT_INT_MASK_0| 99 MIPS_SOFT_INT_MASK_1| 100 MIPS_INT_MASK_2| 101 MIPS_INT_MASK_4, /* IPL_BIO */ 102 103 MIPS_SOFT_INT_MASK_0| 104 MIPS_SOFT_INT_MASK_1| 105 MIPS_INT_MASK_2| 106 MIPS_INT_MASK_4, /* IPL_NET */ 107 108 MIPS_SOFT_INT_MASK_0| 109 MIPS_SOFT_INT_MASK_1| 110 MIPS_INT_MASK_2| 111 MIPS_INT_MASK_4, /* IPL_{TTY,SERIAL} */ 112 113 MIPS_SOFT_INT_MASK_0| 114 MIPS_SOFT_INT_MASK_1| 115 MIPS_INT_MASK_2| 116 MIPS_INT_MASK_4, /* IPL_{CLOCK,HIGH} */ 117 }; 118 119 /* IRQHIGH lines list */ 120 static const struct irqhigh_list { 121 int qh_pri; /* IRQHIGH priority */ 122 int qh_set; /* Register set */ 123 int qh_bit; /* bit offset in the register set */ 124 } irqhigh_list[] = { 125 {15, 5, 25}, /* POSPWROKINT */ 126 {15, 5, 24}, /* NEGPWROKINT */ 127 {14, 5, 30}, /* ALARMINT*/ 128 {13, 5, 29}, /* PERINT */ 129 #ifdef TX391X 130 {12, 2, 3}, /* MBUSPOSINT */ 131 {12, 2, 2}, /* MBUSNEGINT */ 132 {11, 2, 31}, /* UARTARXINT */ 133 {10, 2, 21}, /* UARTBRXINT */ 134 {9, 3, 19}, /* MFIOPOSINT19 */ 135 {9, 3, 18}, /* MFIOPOSINT18 */ 136 {9, 3, 17}, /* MFIOPOSINT17 */ 137 {9, 3, 16}, /* MFIOPOSINT16 */ 138 {8, 3, 1}, /* MFIOPOSINT1 */ 139 {8, 3, 0}, /* MFIOPOSINT0 */ 140 {8, 5, 13}, /* IOPOSINT6 */ 141 {8, 5, 12}, /* IOPOSINT5 */ 142 {7, 4, 19}, /* MFIONEGINT19 */ 143 {7, 4, 18}, /* MFIONEGINT18 */ 144 {7, 4, 17}, /* MFIONEGINT17 */ 145 {7, 4, 16}, /* MFIONEGINT16 */ 146 {6, 4, 1}, /* MFIONEGINT1 */ 147 {6, 4, 0}, /* MFIONEGINT0 */ 148 {6, 5, 6}, /* IONEGINT6 */ 149 {6, 5, 5}, /* IONEGINT5 */ 150 {5, 2, 5}, /* MBUSDMAFULLINT */ 151 #endif /* TX391X */ 152 #ifdef TX392X 153 {12, 2, 31}, /* UARTARXINT */ 154 {12, 2, 21}, /* UARTBRXINT */ 155 {11, 3, 19}, /* MFIOPOSINT19 */ 156 {11, 3, 18}, /* MFIOPOSINT18 */ 157 {11, 3, 17}, /* MFIOPOSINT17 */ 158 {11, 3, 16}, /* MFIOPOSINT16 */ 159 {10, 3, 1}, /* MFIOPOSINT1 */ 160 {10, 3, 0}, /* MFIOPOSINT0 */ 161 {10, 5, 13}, /* IOPOSINT6 */ 162 {10, 5, 12}, /* IOPOSINT5 */ 163 {9, 4, 19}, /* MFIONEGINT19 */ 164 {9, 4, 18}, /* MFIONEGINT18 */ 165 {9, 4, 17}, /* MFIONEGINT17 */ 166 {9, 4, 16}, /* MFIONEGINT16 */ 167 {8, 4, 1}, /* MFIONEGINT1 */ 168 {8, 4, 0}, /* MFIONEGINT0 */ 169 {8, 5, 6}, /* IONEGINT6 */ 170 {8, 5, 5}, /* IONEGINT5 */ 171 {5, 7, 19}, /* IRRXCINT */ 172 {5, 7, 17}, /* IRRXEINT */ 173 #endif /* TX392X */ 174 {4, 1, 18}, /* SNDDMACNTINT */ 175 {3, 1, 17}, /* TELDMACNTINT */ 176 {2, 1, 27}, /* CHIDMACNTINT */ 177 {1, 5, 7}, /* IOPOSINT0 */ 178 {1, 5, 0} /* IONEGINT0 */ 179 }; 180 181 struct txintr_high_entry { 182 int he_set; 183 txreg_t he_mask; 184 int (*he_fun)(void *); 185 void *he_arg; 186 TAILQ_ENTRY(txintr_high_entry) he_link; 187 }; 188 189 #ifdef USE_POLL 190 struct txpoll_entry{ 191 int p_cnt; /* dispatch interval */ 192 int p_desc; 193 int (*p_fun)(void *); 194 void *p_arg; 195 TAILQ_ENTRY(txpoll_entry) p_link; 196 }; 197 int tx39_poll_intr(void *); 198 #endif /* USE_POLL */ 199 200 struct tx39icu_softc { 201 struct device sc_dev; 202 tx_chipset_tag_t sc_tc; 203 /* IRQLOW */ 204 txreg_t sc_le_mask[TX39_INTRSET_MAX + 1]; 205 int (*sc_le_fun[TX39_INTRSET_MAX + 1][32])(void *); 206 void *sc_le_arg[TX39_INTRSET_MAX + 1][32]; 207 /* IRQHIGH */ 208 TAILQ_HEAD(, txintr_high_entry) sc_he_head[TX39_IRQHIGH_MAX]; 209 /* Register */ 210 txreg_t sc_regs[TX39_INTRSET_MAX + 1]; 211 #ifdef USE_POLL 212 unsigned sc_pollcnt; 213 int sc_polling; 214 void *sc_poll_ih; 215 TAILQ_HEAD(, txpoll_entry) sc_p_head; 216 #endif /* USE_POLL */ 217 }; 218 219 int tx39icu_match(struct device *, struct cfdata *, void *); 220 void tx39icu_attach(struct device *, struct device *, void *); 221 int tx39icu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 222 223 void tx39_intr_dump(struct tx39icu_softc *); 224 void tx39_intr_decode(int, int *, int *); 225 void tx39_irqhigh_disestablish(tx_chipset_tag_t, int, int, int); 226 void tx39_irqhigh_establish(tx_chipset_tag_t, int, int, int, 227 int (*)(void *), void *); 228 void tx39_irqhigh_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 229 int tx39_irqhigh(int, int); 230 231 struct cfattach tx39icu_ca = { 232 sizeof(struct tx39icu_softc), tx39icu_match, tx39icu_attach 233 }; 234 235 int 236 tx39icu_match(struct device *parent, struct cfdata *cf, void *aux) 237 { 238 239 return (ATTACH_FIRST); 240 } 241 242 void 243 tx39icu_attach(struct device *parent, struct device *self, void *aux) 244 { 245 struct txsim_attach_args *ta = aux; 246 struct tx39icu_softc *sc = (void *)self; 247 tx_chipset_tag_t tc = ta->ta_tc; 248 txreg_t reg, *regs; 249 int i; 250 251 printf("\n"); 252 sc->sc_tc = ta->ta_tc; 253 254 regs = sc->sc_regs; 255 regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 256 regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 257 regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 258 regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 259 regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 260 regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 261 #ifdef TX392X 262 regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 263 regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 264 #endif 265 #ifdef TX39ICU_DEBUG 266 printf("\t[Windows CE setting]\n"); 267 tx39_intr_dump(sc); 268 #endif /* TX39ICU_DEBUG */ 269 270 #ifdef WINCE_DEFAULT_SETTING 271 #warning WINCE_DEFAULT_SETTING 272 #else /* WINCE_DEFAULT_SETTING */ 273 /* Disable IRQLOW */ 274 tx_conf_write(tc, TX39_INTRENABLE1_REG, 0); 275 tx_conf_write(tc, TX39_INTRENABLE2_REG, 0); 276 tx_conf_write(tc, TX39_INTRENABLE3_REG, 0); 277 tx_conf_write(tc, TX39_INTRENABLE4_REG, 0); 278 tx_conf_write(tc, TX39_INTRENABLE5_REG, 0); 279 #ifdef TX392X 280 tx_conf_write(tc, TX39_INTRENABLE7_REG, 0); 281 tx_conf_write(tc, TX39_INTRENABLE8_REG, 0); 282 #endif /* TX392X */ 283 284 /* Disable IRQHIGH */ 285 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 286 reg &= ~TX39_INTRENABLE6_PRIORITYMASK_MASK; 287 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 288 #endif /* WINCE_DEFAULT_SETTING */ 289 290 /* Clear all pending interrupts */ 291 tx_conf_write(tc, TX39_INTRCLEAR1_REG, 292 tx_conf_read(tc, TX39_INTRSTATUS1_REG)); 293 tx_conf_write(tc, TX39_INTRCLEAR2_REG, 294 tx_conf_read(tc, TX39_INTRSTATUS2_REG)); 295 tx_conf_write(tc, TX39_INTRCLEAR3_REG, 296 tx_conf_read(tc, TX39_INTRSTATUS3_REG)); 297 tx_conf_write(tc, TX39_INTRCLEAR4_REG, 298 tx_conf_read(tc, TX39_INTRSTATUS4_REG)); 299 tx_conf_write(tc, TX39_INTRCLEAR5_REG, 300 tx_conf_read(tc, TX39_INTRSTATUS5_REG)); 301 #ifdef TX392X 302 tx_conf_write(tc, TX39_INTRCLEAR7_REG, 303 tx_conf_read(tc, TX39_INTRSTATUS7_REG)); 304 tx_conf_write(tc, TX39_INTRCLEAR8_REG, 305 tx_conf_read(tc, TX39_INTRSTATUS8_REG)); 306 #endif /* TX392X */ 307 308 /* Enable global interrupts */ 309 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 310 reg |= TX39_INTRENABLE6_GLOBALEN; 311 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 312 313 /* Initialize IRQHIGH interrupt handler holder*/ 314 for (i = 0; i < TX39_IRQHIGH_MAX; i++) { 315 TAILQ_INIT(&sc->sc_he_head[i]); 316 } 317 #ifdef USE_POLL 318 /* Initialize polling handler holder */ 319 TAILQ_INIT(&sc->sc_p_head); 320 #endif /* USE_POLL */ 321 322 /* Register interrupt module myself */ 323 tx_conf_register_intr(tc, self); 324 } 325 326 void 327 TX_INTR(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending) 328 { 329 struct tx39icu_softc *sc; 330 tx_chipset_tag_t tc; 331 txreg_t reg, pend, *regs; 332 int i, j; 333 334 uvmexp.intrs++; 335 336 if ((ipending & MIPS_HARD_INT_MASK) == 0) 337 goto softintr; 338 339 tc = tx_conf_get_tag(); 340 sc = tc->tc_intrt; 341 /* 342 * Read regsiter ASAP 343 */ 344 regs = sc->sc_regs; 345 regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 346 regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 347 regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 348 regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 349 regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 350 regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 351 #ifdef TX392X 352 regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 353 regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 354 #endif 355 356 #ifdef TX39ICU_DEBUG 357 if (!(ipending & MIPS_INT_MASK_4) && !(ipending & MIPS_INT_MASK_2)) { 358 dbg_bit_print(ipending); 359 panic("bogus HwInt"); 360 } 361 if (tx39icu_debug > 1) { 362 tx39_intr_dump(sc); 363 } 364 #endif /* TX39ICU_DEBUG */ 365 366 /* IRQHIGH */ 367 if (ipending & MIPS_INT_MASK_4) { 368 tx39_irqhigh_intr(ipending, pc, status, cause); 369 370 goto softintr; 371 } 372 373 /* IRQLOW */ 374 if (ipending & MIPS_INT_MASK_2) { 375 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 376 int ofs; 377 #ifdef TX392X 378 if (i == 6) 379 continue; 380 #endif /* TX392X */ 381 ofs = TX39_INTRSTATUS_REG(i); 382 pend = sc->sc_regs[i]; 383 reg = sc->sc_le_mask[i] & pend; 384 /* Clear interrupts */ 385 tx_conf_write(tc, ofs, reg); 386 /* Dispatch handler */ 387 for (j = 0 ; j < 32; j++) { 388 if ((reg & (1 << j)) && 389 sc->sc_le_fun[i][j]) { 390 #ifdef TX39ICU_DEBUG 391 if (tx39icu_debug > 1) { 392 tx39intrvec = (i << 16) | j; 393 DPRINTF("IRQLOW %d:%d\n", i, j); 394 } 395 #endif /* TX39ICU_DEBUG */ 396 (*sc->sc_le_fun[i][j]) 397 (sc->sc_le_arg[i][j]); 398 399 } 400 } 401 #ifdef TX39ICU_DEBUG_PRINT_PENDING_INTERRUPT 402 pend &= ~reg; 403 if (pend) { 404 printf("%d pending:", i); 405 dbg_bit_print(pend); 406 } 407 #endif 408 409 } 410 } 411 #ifdef TX39_WATCHDOGTIMER 412 { 413 extern int tx39biu_intr(void *); 414 /* Bus error (If watch dog timer is enabled)*/ 415 if (ipending & MIPS_INT_MASK_1) { 416 tx39biu_intr(0); /* Clear bus error */ 417 } 418 } 419 #endif 420 #if 0 421 /* reset priority mask */ 422 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 423 reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, 0xffff); 424 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 425 #endif 426 427 softintr: 428 _splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE); 429 430 softintr(ipending); 431 } 432 433 int 434 tx39_irqhigh(int set, int bit) 435 { 436 int i, n; 437 438 n = sizeof irqhigh_list / sizeof (struct irqhigh_list); 439 for (i = 0; i < n; i++) { 440 if (irqhigh_list[i].qh_set == set && 441 irqhigh_list[i].qh_bit == bit) 442 return (irqhigh_list[i].qh_pri); 443 } 444 445 return (0); 446 } 447 448 void 449 tx39_irqhigh_intr(u_int32_t ipending, u_int32_t pc, u_int32_t status, 450 u_int32_t cause) 451 { 452 struct txintr_high_entry *he; 453 struct tx39icu_softc *sc; 454 struct clockframe cf; 455 tx_chipset_tag_t tc; 456 int i, pri, ofs, set; 457 txreg_t he_mask; 458 459 tc = tx_conf_get_tag(); 460 sc = tc->tc_intrt; 461 pri = TX39_INTRSTATUS6_INTVECT(sc->sc_regs[0]); 462 463 if (pri == TX39_INTRPRI13_TIMER_PERIODIC) { 464 tx_conf_write(tc, TX39_INTRCLEAR5_REG, 465 TX39_INTRSTATUS5_PERINT); 466 cf.pc = pc; 467 cf.sr = status; 468 hardclock(&cf); 469 intrcnt[HARDCLOCK]++; 470 471 return; 472 } 473 474 /* Handle all pending IRQHIGH interrupts */ 475 for (i = pri; i > 0; i--) { 476 TAILQ_FOREACH(he, &sc->sc_he_head[i], he_link) { 477 set = he->he_set; 478 he_mask = he->he_mask; 479 if (he_mask & (sc->sc_regs[set])) { 480 ofs = TX39_INTRSTATUS_REG(set); 481 /* Clear interrupt */ 482 tx_conf_write(tc, ofs, he_mask); 483 #ifdef TX39ICU_DEBUG 484 if (tx39icu_debug > 1) { 485 tx39intrvec = (set << 16) | 486 (ffs(he_mask) - 1); 487 DPRINTF("IRQHIGH: %d:%d\n", 488 set, ffs(he_mask) - 1); 489 } 490 #endif /* TX39ICU_DEBUG */ 491 /* Dispatch handler */ 492 (*he->he_fun)(he->he_arg); 493 } 494 } 495 } 496 } 497 498 void 499 tx39_intr_decode(int intr, int *set, int *bit) 500 { 501 if (!intr || intr >= (TX39_INTRSET_MAX + 1) * 32 502 #ifdef TX392X 503 || intr == 6 504 #endif /* TX392X */ 505 ) { 506 panic("tx39icu_decode: bogus intrrupt line. %d", intr); 507 } 508 *set = intr / 32; 509 *bit = intr % 32; 510 } 511 512 void 513 tx39_irqhigh_establish(tx_chipset_tag_t tc, int set, int bit, int pri, 514 int (*ih_fun)(void *), void *ih_arg) 515 { 516 struct tx39icu_softc *sc; 517 struct txintr_high_entry *he; 518 txreg_t reg; 519 520 sc = tc->tc_intrt; 521 /* 522 * Add new entry to `pri' priority 523 */ 524 if (!(he = malloc(sizeof(struct txintr_high_entry), 525 M_DEVBUF, M_NOWAIT))) { 526 panic ("tx39_irqhigh_establish: no memory."); 527 } 528 memset(he, 0, sizeof(struct txintr_high_entry)); 529 he->he_set = set; 530 he->he_mask= (1 << bit); 531 he->he_fun = ih_fun; 532 he->he_arg = ih_arg; 533 TAILQ_INSERT_TAIL(&sc->sc_he_head[pri], he, he_link); 534 /* 535 * Enable interrupt on this priority. 536 */ 537 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 538 reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, (1 << pri)); 539 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 540 } 541 542 void 543 tx39_irqhigh_disestablish(tx_chipset_tag_t tc, int set, int bit, int pri) 544 { 545 struct tx39icu_softc *sc; 546 struct txintr_high_entry *he; 547 txreg_t reg; 548 549 sc = tc->tc_intrt; 550 TAILQ_FOREACH(he, &sc->sc_he_head[pri], he_link) { 551 if (he->he_set == set && he->he_mask == (1 << bit)) { 552 TAILQ_REMOVE(&sc->sc_he_head[pri], he, he_link); 553 free(he, M_DEVBUF); 554 break; 555 } 556 } 557 558 if (TAILQ_EMPTY(&sc->sc_he_head[pri])) { 559 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 560 reg &= ~(1 << pri); 561 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 562 } 563 } 564 565 566 void * 567 tx_intr_establish(tx_chipset_tag_t tc, int line, int mode, int level, 568 int (*ih_fun)(void *), void *ih_arg) 569 { 570 struct tx39icu_softc *sc; 571 txreg_t reg; 572 int bit, set, highpri, ofs; 573 574 sc = tc->tc_intrt; 575 576 tx39_intr_decode(line, &set, &bit); 577 578 sc->sc_le_fun[set][bit] = ih_fun; 579 sc->sc_le_arg[set][bit] = ih_arg; 580 DPRINTF("tx_intr_establish: %d:%d", set, bit); 581 582 if ((highpri = tx39_irqhigh(set, bit))) { 583 tx39_irqhigh_establish(tc, set, bit, highpri, 584 ih_fun, ih_arg); 585 DPRINTF("(high)\n"); 586 } else { 587 /* Set mask for acknowledge. */ 588 sc->sc_le_mask[set] |= (1 << bit); 589 /* Enable interrupt */ 590 ofs = TX39_INTRENABLE_REG(set); 591 reg = tx_conf_read(tc, ofs); 592 reg |= (1 << bit); 593 tx_conf_write(tc, ofs, reg); 594 DPRINTF("(low)\n"); 595 } 596 597 return ((void *)line); 598 } 599 600 void 601 tx_intr_disestablish(tx_chipset_tag_t tc, void *arg) 602 { 603 struct tx39icu_softc *sc; 604 int set, bit, highpri, ofs; 605 txreg_t reg; 606 607 sc = tc->tc_intrt; 608 609 tx39_intr_decode((int)arg, &set, &bit); 610 DPRINTF("tx_intr_disestablish: %d:%d", set, bit); 611 612 if ((highpri = tx39_irqhigh(set, bit))) { 613 tx39_irqhigh_disestablish(tc, set, bit, highpri); 614 DPRINTF("(high)\n"); 615 } else { 616 sc->sc_le_fun[set][bit] = 0; 617 sc->sc_le_arg[set][bit] = 0; 618 sc->sc_le_mask[set] &= ~(1 << bit); 619 ofs = TX39_INTRENABLE_REG(set); 620 reg = tx_conf_read(tc, ofs); 621 reg &= ~(1 << bit); 622 tx_conf_write(tc, ofs, reg); 623 DPRINTF("(low)\n"); 624 } 625 } 626 627 u_int32_t 628 tx_intr_status(tx_chipset_tag_t tc, int r) 629 { 630 struct tx39icu_softc *sc = tc->tc_intrt; 631 632 if (r < 0 || r >= TX39_INTRSET_MAX + 1) 633 panic("tx_intr_status: invalid index %d", r); 634 635 return (u_int32_t)(sc->sc_regs[r]); 636 } 637 638 #ifdef USE_POLL 639 void * 640 tx39_poll_establish(tx_chipset_tag_t tc, int interval, int level, 641 int (*ih_fun)(void *), void *ih_arg) 642 { 643 struct tx39icu_softc *sc; 644 struct txpoll_entry *p; 645 int s; 646 void *ret; 647 648 s = splhigh(); 649 sc = tc->tc_intrt; 650 651 if (!(p = malloc(sizeof(struct txpoll_entry), 652 M_DEVBUF, M_NOWAIT))) { 653 panic ("tx39_poll_establish: no memory."); 654 } 655 memset(p, 0, sizeof(struct txpoll_entry)); 656 657 p->p_fun = ih_fun; 658 p->p_arg = ih_arg; 659 p->p_cnt = interval; 660 661 if (!sc->sc_polling) { 662 tx39clock_alarm_set(tc, 33); /* 33 msec */ 663 664 if (!(sc->sc_poll_ih = 665 tx_intr_establish( 666 tc, MAKEINTR(5, TX39_INTRSTATUS5_ALARMINT), 667 IST_EDGE, level, tx39_poll_intr, sc))) { 668 printf("tx39_poll_establish: can't hook\n"); 669 670 splx(s); 671 return (0); 672 } 673 } 674 675 sc->sc_polling++; 676 p->p_desc = sc->sc_polling; 677 TAILQ_INSERT_TAIL(&sc->sc_p_head, p, p_link); 678 ret = (void *)p->p_desc; 679 680 splx(s); 681 return (ret); 682 } 683 684 void 685 tx39_poll_disestablish(tx_chipset_tag_t tc, void *arg) 686 { 687 struct tx39icu_softc *sc; 688 struct txpoll_entry *p; 689 int s, desc; 690 691 s = splhigh(); 692 sc = tc->tc_intrt; 693 694 desc = (int)arg; 695 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 696 if (p->p_desc == desc) { 697 TAILQ_REMOVE(&sc->sc_p_head, p, p_link); 698 free(p, M_DEVBUF); 699 break; 700 } 701 } 702 703 if (TAILQ_EMPTY(&sc->sc_p_head)) { 704 sc->sc_polling = 0; 705 tx_intr_disestablish(tc, sc->sc_poll_ih); 706 } 707 708 splx(s); 709 return; 710 } 711 712 int 713 tx39_poll_intr(void *arg) 714 { 715 struct tx39icu_softc *sc = arg; 716 struct txpoll_entry *p; 717 718 tx39clock_alarm_refill(sc->sc_tc); 719 720 if (!sc->sc_polling) { 721 return (0); 722 } 723 sc->sc_pollcnt++; 724 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 725 if (sc->sc_pollcnt % p->p_cnt == 0) { 726 if ((*p->p_fun)(p->p_arg) == POLL_END) 727 goto disestablish; 728 } 729 } 730 731 return (0); 732 733 disestablish: 734 TAILQ_REMOVE(&sc->sc_p_head, p, p_link); 735 free(p, M_DEVBUF); 736 if (TAILQ_EMPTY(&sc->sc_p_head)) { 737 sc->sc_polling = 0; 738 tx_intr_disestablish(sc->sc_tc, sc->sc_poll_ih); 739 } 740 741 return (0); 742 } 743 #endif /* USE_POLL */ 744 745 void 746 tx39_intr_dump(struct tx39icu_softc *sc) 747 { 748 tx_chipset_tag_t tc = sc->sc_tc; 749 int i, j, ofs; 750 txreg_t reg; 751 char msg[16]; 752 753 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 754 #ifdef TX392X 755 if (i == 6) 756 continue; 757 #endif /* TX392X */ 758 for (reg = j = 0; j < 32; j++) { 759 if (tx39_irqhigh(i, j)) { 760 reg |= (1 << j); 761 } 762 } 763 sprintf(msg, "%d high", i); 764 dbg_bit_print_msg(reg, msg); 765 sprintf(msg, "%d status", i); 766 dbg_bit_print_msg(sc->sc_regs[i], msg); 767 ofs = TX39_INTRENABLE_REG(i); 768 reg = tx_conf_read(tc, ofs); 769 sprintf(msg, "%d enable", i); 770 dbg_bit_print_msg(reg, msg); 771 } 772 reg = sc->sc_regs[0]; 773 printf("<%s><%s> vector=%2d\t\t[6 status]\n", 774 reg & TX39_INTRSTATUS6_IRQHIGH ? "HI" : "--", 775 reg & TX39_INTRSTATUS6_IRQLOW ? "LO" : "--", 776 TX39_INTRSTATUS6_INTVECT(reg)); 777 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 778 __dbg_bit_print(reg, sizeof(reg), 0, 18, "6 enable", 779 DBG_BIT_PRINT_COUNT); 780 781 } 782
Indexes created Thu Oct 30 16:09:53 GMT 2025