tx39icu.c revision 1.2
1 /* $NetBSD: tx39icu.c,v 1.2 1999/12/07 17:11:05 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include "opt_tx39_debug.h" 29 #include "opt_use_poll.h" 30 #include "opt_tx39icudebug.h" 31 #include "opt_tx39_watchdogtimer.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/malloc.h> 37 #include <sys/queue.h> 38 #define TAILQ_FOREACH(var, head, field) \ 39 for (var = TAILQ_FIRST(head); var; var = TAILQ_NEXT(var, field)) 40 #define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) 41 42 #include <mips/cpuregs.h> 43 #include <machine/bus.h> 44 45 #include <hpcmips/tx/tx39var.h> 46 #include <hpcmips/tx/tx39icureg.h> 47 48 #include <machine/clock_machdep.h> 49 #include <machine/cpu.h> 50 #include <dev/dec/clockvar.h> 51 52 #undef TX39ICUDEBUG_PRINT_PENDING_INTERRUPT /* For explorer. good luck! */ 53 54 #ifdef TX39ICUDEBUG 55 #define DPRINTF(arg) printf arg 56 #else 57 #define DPRINTF(arg) 58 #endif 59 u_int32_t tx39intrvec; /* debug use */ 60 61 /* IRQHIGH lines list */ 62 static struct irqhigh_list { 63 int qh_pri; /* IRQHIGH priority */ 64 int qh_set; /* Register set */ 65 int qh_bit; /* bit offset in the register set */ 66 } irqhigh_list[] = { 67 {15, 5, 25}, /* POSPWROKINT */ 68 {15, 5, 24}, /* NEGPWROKINT */ 69 {14, 5, 30}, /* ALARMINT*/ 70 {13, 5, 29}, /* PERINT */ 71 #ifdef TX391X 72 {12, 2, 3}, /* MBUSPOSINT */ 73 {12, 2, 2}, /* MBUSNEGINT */ 74 {11, 2, 31}, /* UARTARXINT */ 75 {10, 2, 21}, /* UARTBRXINT */ 76 {9, 3, 19}, /* MFIOPOSINT19 */ 77 {9, 3, 18}, /* MFIOPOSINT18 */ 78 {9, 3, 17}, /* MFIOPOSINT17 */ 79 {9, 3, 16}, /* MFIOPOSINT16 */ 80 {8, 3, 1}, /* MFIOPOSINT1 */ 81 {8, 3, 0}, /* MFIOPOSINT0 */ 82 {8, 5, 13}, /* IOPOSINT6 */ 83 {8, 5, 12}, /* IOPOSINT5 */ 84 {7, 4, 19}, /* MFIONEGINT19 */ 85 {7, 4, 18}, /* MFIONEGINT18 */ 86 {7, 4, 17}, /* MFIONEGINT17 */ 87 {7, 4, 16}, /* MFIONEGINT16 */ 88 {6, 4, 1}, /* MFIONEGINT1 */ 89 {6, 4, 0}, /* MFIONEGINT0 */ 90 {6, 5, 6}, /* IONEGINT6 */ 91 {6, 5, 5}, /* IONEGINT5 */ 92 {5, 2, 5}, /* MBUSDMAFULLINT */ 93 #endif /* TX391X */ 94 #ifdef TX392X 95 {12, 2, 31}, /* UARTARXINT */ 96 {12, 2, 21}, /* UARTBRXINT */ 97 {11, 3, 19}, /* MFIOPOSINT19 */ 98 {11, 3, 18}, /* MFIOPOSINT18 */ 99 {11, 3, 17}, /* MFIOPOSINT17 */ 100 {11, 3, 16}, /* MFIOPOSINT16 */ 101 {10, 3, 1}, /* MFIOPOSINT1 */ 102 {10, 3, 0}, /* MFIOPOSINT0 */ 103 {10, 5, 13}, /* IOPOSINT6 */ 104 {10, 5, 12}, /* IOPOSINT5 */ 105 {9, 4, 19}, /* MFIONEGINT19 */ 106 {9, 4, 18}, /* MFIONEGINT18 */ 107 {9, 4, 17}, /* MFIONEGINT17 */ 108 {9, 4, 16}, /* MFIONEGINT16 */ 109 {8, 4, 1}, /* MFIONEGINT1 */ 110 {8, 4, 0}, /* MFIONEGINT0 */ 111 {8, 5, 6}, /* IONEGINT6 */ 112 {8, 5, 5}, /* IONEGINT5 */ 113 {5, 7, 19}, /* IRRXCINT */ 114 {5, 7, 17}, /* IRRXEINT */ 115 #endif /* TX392X */ 116 {4, 1, 18}, /* SNDDMACNTINT */ 117 {3, 1, 17}, /* TELDMACNTINT */ 118 {2, 1, 27}, /* CHIDMACNTINT */ 119 {1, 5, 7}, /* IOPOSINT0 */ 120 {1, 5, 0} /* IONEGINT0 */ 121 }; 122 123 struct txintr_high_entry { 124 int he_set; 125 txreg_t he_mask; 126 int (*he_fun) __P((void*)); 127 void *he_arg; 128 TAILQ_ENTRY(txintr_high_entry) he_link; 129 }; 130 131 #ifdef USE_POLL 132 struct txpoll_entry{ 133 int p_cnt; /* dispatch interval */ 134 int p_desc; 135 int (*p_fun) __P((void*)); 136 void *p_arg; 137 TAILQ_ENTRY(txpoll_entry) p_link; 138 }; 139 int tx39_poll_intr __P((void*)); 140 #endif /* USE_POLL */ 141 142 struct tx39icu_softc { 143 struct device sc_dev; 144 tx_chipset_tag_t sc_tc; 145 /* IRQLOW */ 146 txreg_t sc_le_mask[TX39_INTRSET_MAX + 1]; 147 int (*sc_le_fun[TX39_INTRSET_MAX + 1][32]) __P((void*)); 148 void *sc_le_arg[TX39_INTRSET_MAX + 1][32]; 149 /* IRQHIGH */ 150 TAILQ_HEAD(, txintr_high_entry) sc_he_head[TX39_IRQHIGH_MAX]; 151 /* Register */ 152 txreg_t sc_regs[TX39_INTRSET_MAX + 1]; 153 #ifdef USE_POLL 154 unsigned sc_pollcnt; 155 int sc_polling; 156 void *sc_poll_ih; 157 TAILQ_HEAD(, txpoll_entry) sc_p_head; 158 #endif /* USE_POLL */ 159 }; 160 161 int tx39icu_match __P((struct device*, struct cfdata*, void*)); 162 void tx39icu_attach __P((struct device*, struct device*, void*)); 163 int tx39icu_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t)); 164 165 void tx39_intr_dump __P((struct tx39icu_softc*)); 166 void tx39_intr_decode __P((int, int*, int*)); 167 void tx39_irqhigh_disestablish __P((tx_chipset_tag_t, int, int, int)); 168 void tx39_irqhigh_establish __P((tx_chipset_tag_t, int, int, int, int (*) __P((void*)), void*)); 169 void tx39_irqhigh_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t)); 170 int tx39_irqhigh __P((int, int)); 171 172 struct cfattach tx39icu_ca = { 173 sizeof(struct tx39icu_softc), tx39icu_match, tx39icu_attach 174 }; 175 176 int 177 tx39icu_match(parent, cf, aux) 178 struct device *parent; 179 struct cfdata *cf; 180 void *aux; 181 { 182 return 2; /* 1st attach group of txsim */ 183 } 184 185 void 186 tx39icu_attach(parent, self, aux) 187 struct device *parent; 188 struct device *self; 189 void *aux; 190 { 191 struct txsim_attach_args *ta = aux; 192 struct tx39icu_softc *sc = (void*)self; 193 tx_chipset_tag_t tc = ta->ta_tc; 194 txreg_t reg; 195 int i; 196 197 printf("\n"); 198 sc->sc_tc = ta->ta_tc; 199 200 sc->sc_regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 201 sc->sc_regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 202 sc->sc_regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 203 sc->sc_regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 204 sc->sc_regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 205 sc->sc_regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 206 #ifdef TX392X 207 sc->sc_regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 208 sc->sc_regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 209 #endif 210 #ifdef TX39ICUDEBUG 211 printf("\t[Windows CE setting]\n"); 212 tx39_intr_dump(sc); 213 #endif /* TX39ICUDEBUG */ 214 215 #ifdef WINCE_DEFAULT_SETTING 216 #warning WINCE_DEFAULT_SETTING 217 #else /* WINCE_DEFAULT_SETTING */ 218 /* Disable IRQLOW */ 219 tx_conf_write(tc, TX39_INTRENABLE1_REG, 0); 220 tx_conf_write(tc, TX39_INTRENABLE2_REG, 0); 221 tx_conf_write(tc, TX39_INTRENABLE3_REG, 0); 222 tx_conf_write(tc, TX39_INTRENABLE4_REG, 0); 223 tx_conf_write(tc, TX39_INTRENABLE5_REG, 0); 224 #ifdef TX392X 225 tx_conf_write(tc, TX39_INTRENABLE7_REG, 0); 226 tx_conf_write(tc, TX39_INTRENABLE8_REG, 0); 227 #endif /* TX392X */ 228 229 /* Disable IRQHIGH */ 230 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 231 reg &= ~TX39_INTRENABLE6_PRIORITYMASK_MASK; 232 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 233 #endif /* WINCE_DEFAULT_SETTING */ 234 235 /* Clear all pending interrupts */ 236 tx_conf_write(tc, TX39_INTRCLEAR1_REG, tx_conf_read(tc, TX39_INTRSTATUS1_REG)); 237 tx_conf_write(tc, TX39_INTRCLEAR2_REG, tx_conf_read(tc, TX39_INTRSTATUS2_REG)); 238 tx_conf_write(tc, TX39_INTRCLEAR3_REG, tx_conf_read(tc, TX39_INTRSTATUS3_REG)); 239 tx_conf_write(tc, TX39_INTRCLEAR4_REG, tx_conf_read(tc, TX39_INTRSTATUS4_REG)); 240 tx_conf_write(tc, TX39_INTRCLEAR5_REG, tx_conf_read(tc, TX39_INTRSTATUS5_REG)); 241 #ifdef TX392X 242 tx_conf_write(tc, TX39_INTRCLEAR7_REG, tx_conf_read(tc, TX39_INTRSTATUS7_REG)); 243 tx_conf_write(tc, TX39_INTRCLEAR8_REG, tx_conf_read(tc, TX39_INTRSTATUS8_REG)); 244 #endif /* TX392X */ 245 246 /* Enable global interrupts */ 247 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 248 reg |= TX39_INTRENABLE6_GLOBALEN; 249 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 250 251 /* Initialize IRQHIGH interrupt handler holder*/ 252 for (i = 0; i < TX39_IRQHIGH_MAX; i++) { 253 TAILQ_INIT(&sc->sc_he_head[i]); 254 } 255 #ifdef USE_POLL 256 /* Initialize polling handler holder */ 257 TAILQ_INIT(&sc->sc_p_head); 258 #endif /* USE_POLL */ 259 260 /* Register interrupt module myself */ 261 tx_conf_register_intr(tc, self); 262 } 263 264 int 265 tx39icu_intr(mask, pc, status, cause) 266 u_int32_t mask; 267 u_int32_t pc; 268 u_int32_t status; 269 u_int32_t cause; 270 { 271 struct tx39icu_softc *sc; 272 tx_chipset_tag_t tc; 273 txreg_t reg, pend; 274 int i, j; 275 276 tc = tx_conf_get_tag(); 277 sc = tc->tc_intrt; 278 /* 279 * Read regsiter ASAP 280 */ 281 sc->sc_regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 282 sc->sc_regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 283 sc->sc_regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 284 sc->sc_regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 285 sc->sc_regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 286 sc->sc_regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 287 #ifdef TX392X 288 sc->sc_regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 289 sc->sc_regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 290 #endif 291 292 #ifdef TX39ICUDEBUG 293 if (!(mask & MIPS_INT_MASK_4) && !(mask & MIPS_INT_MASK_2)) { 294 bitdisp(mask); 295 panic("bogus HwInt"); 296 } 297 #ifdef TX39_DEBUG 298 if (tx39debugflag) { 299 tx39_intr_dump(sc); 300 } 301 #endif 302 #endif /* TX39ICUDEBUG */ 303 304 /* IRQHIGH */ 305 if (mask & MIPS_INT_MASK_4) { 306 tx39_irqhigh_intr(mask, pc, status, cause); 307 } 308 309 /* IRQLOW */ 310 if (mask & MIPS_INT_MASK_2) { 311 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 312 int ofs; 313 #ifdef TX392X 314 if (i == 6) 315 continue; 316 #endif /* TX392X */ 317 ofs = TX39_INTRSTATUS_REG(i); 318 pend = sc->sc_regs[i]; 319 reg = sc->sc_le_mask[i] & pend; 320 /* Clear interrupts */ 321 tx_conf_write(tc, ofs, reg); 322 /* Dispatch handler */ 323 for (j = 0 ; j < 32; j++) { 324 if ((reg & (1 << j)) && 325 sc->sc_le_fun[i][j]) { 326 #ifdef TX39_DEBUG 327 tx39intrvec = (i << 16) | j; 328 if (tx39debugflag) { 329 DPRINTF(("IRQLOW %d:%d\n", 330 i, j)); 331 } 332 #endif /* TX39_DEBUG */ 333 (*sc->sc_le_fun[i][j]) 334 (sc->sc_le_arg[i][j]); 335 336 } 337 } 338 #ifdef TX39ICUDEBUG_PRINT_PENDING_INTERRUPT 339 pend &= ~reg; 340 if (pend) { 341 printf("%d pending:", i); 342 __bitdisp(pend, 0, 31, 0, 1); 343 } 344 #endif 345 346 } 347 } 348 #ifdef TX39_WATCHDOGTIMER 349 /* Bus error (If watch dog timer is enabled)*/ 350 if (mask & MIPS_INT_MASK_1) { 351 tx39biu_intr(0); /* Clear bus error */ 352 } 353 #endif 354 return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 355 } 356 357 int 358 tx39_irqhigh(set, bit) 359 int set, bit; 360 { 361 int i, n; 362 363 n = sizeof irqhigh_list / sizeof (struct irqhigh_list); 364 for (i = 0; i < n; i++) { 365 if (irqhigh_list[i].qh_set == set && 366 irqhigh_list[i].qh_bit == bit) 367 return irqhigh_list[i].qh_pri; 368 } 369 370 return 0; 371 } 372 373 void 374 tx39_irqhigh_intr(mask, pc, status, cause) 375 u_int32_t mask; 376 u_int32_t pc; 377 u_int32_t status; 378 u_int32_t cause; 379 { 380 struct txintr_high_entry *he; 381 struct tx39icu_softc *sc; 382 struct clockframe cf; 383 tx_chipset_tag_t tc; 384 int i, pri, ofs, set; 385 txreg_t he_mask; 386 387 tc = tx_conf_get_tag(); 388 sc = tc->tc_intrt; 389 pri = TX39_INTRSTATUS6_INTVECT(sc->sc_regs[0]); 390 391 if (pri == TX39_INTRPRI13_TIMER_PERIODIC) { 392 cf.pc = pc; 393 cf.sr = status; 394 hardclock(&cf); 395 tx_conf_write(tc, TX39_INTRCLEAR5_REG, 396 TX39_INTRSTATUS5_PERINT); 397 } 398 /* Handle all pending IRQHIGH interrupts */ 399 for (i = pri; i > 0; i--) { 400 TAILQ_FOREACH(he, &sc->sc_he_head[i], he_link) { 401 set = he->he_set; 402 he_mask = he->he_mask; 403 if (he_mask & (sc->sc_regs[set])) { 404 ofs = TX39_INTRSTATUS_REG(set); 405 /* Clear interrupt */ 406 tx_conf_write(tc, ofs, he_mask); 407 #ifdef TX39_DEBUG 408 tx39intrvec = (set << 16) | 409 (ffs(he_mask) - 1); 410 if (tx39debugflag) { 411 DPRINTF(("IRQHIGH: %d:%d\n", 412 set, ffs(he_mask) - 1)); 413 } 414 #endif /* TX39_DEBUG */ 415 /* Dispatch handler */ 416 (*he->he_fun)(he->he_arg); 417 } 418 } 419 } 420 } 421 422 void 423 tx39_intr_decode(intr, set, bit) 424 int intr; 425 int *set; 426 int *bit; 427 { 428 if (!intr || intr >= (TX39_INTRSET_MAX + 1) * 32 429 #ifdef TX392X 430 || intr == 6 431 #endif /* TX392X */ 432 ) { 433 panic("tx39icu_decode: bogus intrrupt line. %d", intr); 434 } 435 *set = intr / 32; 436 *bit = intr % 32; 437 } 438 439 void 440 tx39_irqhigh_establish(tc, set, bit, pri, ih_fun, ih_arg) 441 tx_chipset_tag_t tc; 442 int set; 443 int bit; 444 int pri; 445 int (*ih_fun) __P((void*)); 446 void *ih_arg; 447 { 448 struct tx39icu_softc *sc; 449 struct txintr_high_entry *he; 450 txreg_t reg; 451 452 sc = tc->tc_intrt; 453 /* 454 * Add new entry to `pri' priority. 455 */ 456 if (!(he = malloc(sizeof(struct txintr_high_entry), 457 M_DEVBUF, M_NOWAIT))) { 458 panic ("tx39_irqhigh_establish: no memory."); 459 } 460 memset(he, 0, sizeof(struct txintr_high_entry)); 461 he->he_set = set; 462 he->he_mask= (1 << bit); 463 he->he_fun = ih_fun; 464 he->he_arg = ih_arg; 465 TAILQ_INSERT_TAIL(&sc->sc_he_head[pri], he, he_link); 466 /* 467 * Enable interrupt on this priority. 468 */ 469 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 470 reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, (1 << pri)); 471 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 472 } 473 474 void 475 tx39_irqhigh_disestablish(tc, set, bit, pri) 476 tx_chipset_tag_t tc; 477 int set, bit, pri; 478 { 479 struct tx39icu_softc *sc; 480 struct txintr_high_entry *he; 481 txreg_t reg; 482 483 sc = tc->tc_intrt; 484 TAILQ_FOREACH(he, &sc->sc_he_head[pri], he_link) { 485 if (he->he_set == set && he->he_mask == (1 << bit)) { 486 TAILQ_REMOVE(&sc->sc_he_head[pri], he, he_link); 487 free(he, M_DEVBUF); 488 break; 489 } 490 } 491 492 if (TAILQ_EMPTY(&sc->sc_he_head[pri])) { 493 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 494 reg &= ~(1 << pri); 495 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 496 } 497 } 498 499 500 void* 501 tx_intr_establish(tc, line, mode, level, ih_fun, ih_arg) 502 tx_chipset_tag_t tc; 503 int line; 504 int mode; /* Trigger setting. but TX39 handles edge only. */ 505 int level; /* XXX not yet */ 506 int (*ih_fun) __P((void*)); 507 void *ih_arg; 508 { 509 struct tx39icu_softc *sc; 510 txreg_t reg; 511 int bit, set, highpri, ofs; 512 513 sc = tc->tc_intrt; 514 515 tx39_intr_decode(line, &set, &bit); 516 517 sc->sc_le_fun[set][bit] = ih_fun; 518 sc->sc_le_arg[set][bit] = ih_arg; 519 DPRINTF(("tx_intr_establish: %d:%d", set, bit)); 520 521 if ((highpri = tx39_irqhigh(set, bit))) { 522 tx39_irqhigh_establish(tc, set, bit, highpri, 523 ih_fun, ih_arg); 524 DPRINTF(("(high)\n")); 525 } else { 526 /* Set mask for acknowledge. */ 527 sc->sc_le_mask[set] |= (1 << bit); 528 /* Enable interrupt */ 529 ofs = TX39_INTRENABLE_REG(set); 530 reg = tx_conf_read(tc, ofs); 531 reg |= (1 << bit); 532 tx_conf_write(tc, ofs, reg); 533 DPRINTF(("(low)\n")); 534 } 535 536 return (void*)line; 537 } 538 539 void 540 tx_intr_disestablish(tc, arg) 541 tx_chipset_tag_t tc; 542 void *arg; 543 { 544 struct tx39icu_softc *sc; 545 int set, bit, highpri, ofs; 546 txreg_t reg; 547 548 sc = tc->tc_intrt; 549 550 tx39_intr_decode((int)arg, &set, &bit); 551 DPRINTF(("tx_intr_disestablish: %d:%d", set, bit)); 552 553 if ((highpri = tx39_irqhigh(set, bit))) { 554 tx39_irqhigh_disestablish(tc, set, bit, highpri); 555 DPRINTF(("(high)\n")); 556 } else { 557 sc->sc_le_fun[set][bit] = 0; 558 sc->sc_le_arg[set][bit] = 0; 559 sc->sc_le_mask[set] &= ~(1 << bit); 560 ofs = TX39_INTRENABLE_REG(set); 561 reg = tx_conf_read(tc, ofs); 562 reg &= ~(1 << bit); 563 tx_conf_write(tc, ofs, reg); 564 DPRINTF(("(low)\n")); 565 } 566 } 567 568 void 569 tx39_intr_dump(sc) 570 struct tx39icu_softc *sc; 571 { 572 tx_chipset_tag_t tc = sc->sc_tc; 573 int i, j, ofs; 574 txreg_t reg; 575 char msg[16]; 576 577 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 578 #ifdef TX392X 579 if (i == 6) 580 continue; 581 #endif /* TX392X */ 582 for (reg = j = 0; j < 32; j++) { 583 if (tx39_irqhigh(i, j)) { 584 reg |= (1 << j); 585 } 586 } 587 sprintf(msg, "%d high", i); 588 __bitdisp(reg, 32, 0, msg, 1); 589 sprintf(msg, "%d status", i); 590 __bitdisp(sc->sc_regs[i], 0, 31, msg, 1); 591 ofs = TX39_INTRENABLE_REG(i); 592 reg = tx_conf_read(tc, ofs); 593 sprintf(msg, "%d enable", i); 594 __bitdisp(reg, 0, 31, msg, 1); 595 } 596 reg = sc->sc_regs[0]; 597 printf("<%s><%s> vector=%2d\t\t[6 status]\n", 598 reg & TX39_INTRSTATUS6_IRQHIGH ? "HI" : "--", 599 reg & TX39_INTRSTATUS6_IRQLOW ? "LO" : "--", 600 TX39_INTRSTATUS6_INTVECT(reg)); 601 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 602 __bitdisp(reg, 0, 18, "6 enable", 1); 603 604 } 605 606 #ifdef USE_POLL 607 void* 608 tx39_poll_establish(tc, interval, mode, level, ih_fun, ih_arg) 609 tx_chipset_tag_t tc; 610 int interval; 611 int mode; /* Trigger setting. but TX39 handles edge only. */ 612 int level; /* XXX not yet */ 613 int (*ih_fun) __P((void*)); 614 void *ih_arg; 615 { 616 struct tx39icu_softc *sc; 617 struct txpoll_entry *p; 618 619 sc = tc->tc_intrt; 620 621 if (!(p = malloc(sizeof(struct txpoll_entry), 622 M_DEVBUF, M_NOWAIT))) { 623 panic ("tx39_poll_establish: no memory."); 624 } 625 memset(p, 0, sizeof(struct txpoll_entry)); 626 627 p->p_fun = ih_fun; 628 p->p_arg = ih_arg; 629 p->p_cnt = interval; 630 if (!sc->sc_polling) { 631 /* Hook VSync : TX39_INTRSTATUS1_LCDINT*/ 632 if (!(sc->sc_poll_ih = 633 tx_intr_establish( 634 #ifdef TX391X 635 tc, MAKEINTR(1, TX39_INTRSTATUS1_LCDINT), 636 #endif 637 #ifdef TX392X 638 tc, MAKEINTR(5, TX39_INTRSTATUS5_STPTIMERINT), 639 #endif 640 mode, level, tx39_poll_intr, sc))) { 641 printf("tx39_poll_establish: can't hook\n"); 642 return 0; 643 } 644 } 645 sc->sc_polling++; 646 p->p_desc = sc->sc_polling; 647 TAILQ_INSERT_TAIL(&sc->sc_p_head, p, p_link); 648 649 return (void*)p->p_desc; 650 } 651 652 void 653 tx39_poll_disestablish(tc, arg) 654 tx_chipset_tag_t tc; 655 void *arg; 656 { 657 struct tx39icu_softc *sc; 658 struct txpoll_entry *p; 659 int desc; 660 sc = tc->tc_intrt; 661 662 desc = (int)arg; 663 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 664 if (p->p_desc == desc) { 665 TAILQ_REMOVE(&sc->sc_p_head, p, p_link); 666 free(p, M_DEVBUF); 667 break; 668 } 669 } 670 if (TAILQ_EMPTY(&sc->sc_p_head)) { 671 sc->sc_polling = 0; 672 tx_intr_disestablish(tc, sc->sc_poll_ih); 673 } 674 } 675 676 int 677 tx39_poll_intr(arg) 678 void *arg; 679 { 680 struct tx39icu_softc *sc = arg; 681 struct txpoll_entry *p; 682 683 if (!sc->sc_polling) { 684 return 0; 685 } 686 sc->sc_pollcnt++; 687 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 688 if (sc->sc_pollcnt % p->p_cnt == 0) { 689 (*p->p_fun)(p->p_arg); 690 } 691 } 692 return 0; 693 } 694 #endif /* USE_POLL */ 695
Indexes created Wed Oct 29 03:09:52 GMT 2025