tx39icu.c revision 1.23
1 /* $NetBSD: tx39icu.c,v 1.23 2007/12/03 15:33:44 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1999-2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: tx39icu.c,v 1.23 2007/12/03 15:33:44 ad Exp $"); 41 42 #include "opt_vr41xx.h" 43 #include "opt_tx39xx.h" 44 45 #include "opt_use_poll.h" 46 #include "opt_tx39icu_debug.h" 47 #include "opt_tx39_watchdogtimer.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 #include <sys/malloc.h> 53 #include <sys/queue.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <mips/cpuregs.h> 58 #include <machine/bus.h> 59 60 #include <hpcmips/tx/tx39var.h> 61 #include <hpcmips/tx/tx39icureg.h> 62 #include <hpcmips/tx/tx39clockvar.h> 63 64 #include <machine/cpu.h> 65 #include <dev/dec/clockvar.h> 66 67 #undef TX39ICU_DEBUG_PRINT_PENDING_INTERRUPT /* For explorer. good luck! */ 68 69 #if defined(VR41XX) && defined(TX39XX) 70 #define TX_INTR tx_intr 71 #else 72 #define TX_INTR cpu_intr /* locore_mips3 directly call this */ 73 #endif 74 void TX_INTR(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 75 76 #ifdef TX39ICU_DEBUG 77 #define DPRINTF_ENABLE 78 #define DPRINTF_DEBUG tx39icu_debug 79 #endif 80 #include <machine/debug.h> 81 82 u_int32_t tx39intrvec; 83 84 /* 85 * This is a mask of bits to clear in the SR when we go to a 86 * given interrupt priority level. 87 */ 88 const u_int32_t __ipl_sr_bits_tx[_IPL_N] = { 89 0, /* IPL_NONE */ 90 91 MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */ 92 93 MIPS_SOFT_INT_MASK_0| 94 MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */ 95 96 MIPS_SOFT_INT_MASK_0| 97 MIPS_SOFT_INT_MASK_1| 98 MIPS_INT_MASK_2| 99 MIPS_INT_MASK_4, /* IPL_VM */ 100 101 MIPS_SOFT_INT_MASK_0| 102 MIPS_SOFT_INT_MASK_1| 103 MIPS_INT_MASK_2| 104 MIPS_INT_MASK_4, /* IPL_SCHED */ 105 }; 106 107 /* IRQHIGH lines list */ 108 static const struct irqhigh_list { 109 int qh_pri; /* IRQHIGH priority */ 110 int qh_set; /* Register set */ 111 int qh_bit; /* bit offset in the register set */ 112 } irqhigh_list[] = { 113 {15, 5, 25}, /* POSPWROKINT */ 114 {15, 5, 24}, /* NEGPWROKINT */ 115 {14, 5, 30}, /* ALARMINT*/ 116 {13, 5, 29}, /* PERINT */ 117 #ifdef TX391X 118 {12, 2, 3}, /* MBUSPOSINT */ 119 {12, 2, 2}, /* MBUSNEGINT */ 120 {11, 2, 31}, /* UARTARXINT */ 121 {10, 2, 21}, /* UARTBRXINT */ 122 {9, 3, 19}, /* MFIOPOSINT19 */ 123 {9, 3, 18}, /* MFIOPOSINT18 */ 124 {9, 3, 17}, /* MFIOPOSINT17 */ 125 {9, 3, 16}, /* MFIOPOSINT16 */ 126 {8, 3, 1}, /* MFIOPOSINT1 */ 127 {8, 3, 0}, /* MFIOPOSINT0 */ 128 {8, 5, 13}, /* IOPOSINT6 */ 129 {8, 5, 12}, /* IOPOSINT5 */ 130 {7, 4, 19}, /* MFIONEGINT19 */ 131 {7, 4, 18}, /* MFIONEGINT18 */ 132 {7, 4, 17}, /* MFIONEGINT17 */ 133 {7, 4, 16}, /* MFIONEGINT16 */ 134 {6, 4, 1}, /* MFIONEGINT1 */ 135 {6, 4, 0}, /* MFIONEGINT0 */ 136 {6, 5, 6}, /* IONEGINT6 */ 137 {6, 5, 5}, /* IONEGINT5 */ 138 {5, 2, 5}, /* MBUSDMAFULLINT */ 139 #endif /* TX391X */ 140 #ifdef TX392X 141 {12, 2, 31}, /* UARTARXINT */ 142 {12, 2, 21}, /* UARTBRXINT */ 143 {11, 3, 19}, /* MFIOPOSINT19 */ 144 {11, 3, 18}, /* MFIOPOSINT18 */ 145 {11, 3, 17}, /* MFIOPOSINT17 */ 146 {11, 3, 16}, /* MFIOPOSINT16 */ 147 {10, 3, 1}, /* MFIOPOSINT1 */ 148 {10, 3, 0}, /* MFIOPOSINT0 */ 149 {10, 5, 13}, /* IOPOSINT6 */ 150 {10, 5, 12}, /* IOPOSINT5 */ 151 {9, 4, 19}, /* MFIONEGINT19 */ 152 {9, 4, 18}, /* MFIONEGINT18 */ 153 {9, 4, 17}, /* MFIONEGINT17 */ 154 {9, 4, 16}, /* MFIONEGINT16 */ 155 {8, 4, 1}, /* MFIONEGINT1 */ 156 {8, 4, 0}, /* MFIONEGINT0 */ 157 {8, 5, 6}, /* IONEGINT6 */ 158 {8, 5, 5}, /* IONEGINT5 */ 159 {5, 7, 19}, /* IRRXCINT */ 160 {5, 7, 17}, /* IRRXEINT */ 161 #endif /* TX392X */ 162 {4, 1, 18}, /* SNDDMACNTINT */ 163 {3, 1, 17}, /* TELDMACNTINT */ 164 {2, 1, 27}, /* CHIDMACNTINT */ 165 {1, 5, 7}, /* IOPOSINT0 */ 166 {1, 5, 0} /* IONEGINT0 */ 167 }; 168 169 struct txintr_high_entry { 170 int he_set; 171 txreg_t he_mask; 172 int (*he_fun)(void *); 173 void *he_arg; 174 TAILQ_ENTRY(txintr_high_entry) he_link; 175 }; 176 177 #ifdef USE_POLL 178 struct txpoll_entry{ 179 int p_cnt; /* dispatch interval */ 180 int p_desc; 181 int (*p_fun)(void *); 182 void *p_arg; 183 TAILQ_ENTRY(txpoll_entry) p_link; 184 }; 185 int tx39_poll_intr(void *); 186 #endif /* USE_POLL */ 187 188 struct tx39icu_softc { 189 struct device sc_dev; 190 tx_chipset_tag_t sc_tc; 191 /* IRQLOW */ 192 txreg_t sc_le_mask[TX39_INTRSET_MAX + 1]; 193 int (*sc_le_fun[TX39_INTRSET_MAX + 1][32])(void *); 194 void *sc_le_arg[TX39_INTRSET_MAX + 1][32]; 195 /* IRQHIGH */ 196 TAILQ_HEAD(, txintr_high_entry) sc_he_head[TX39_IRQHIGH_MAX]; 197 /* Register */ 198 txreg_t sc_regs[TX39_INTRSET_MAX + 1]; 199 #ifdef USE_POLL 200 unsigned sc_pollcnt; 201 int sc_polling; 202 void *sc_poll_ih; 203 TAILQ_HEAD(, txpoll_entry) sc_p_head; 204 #endif /* USE_POLL */ 205 }; 206 207 int tx39icu_match(struct device *, struct cfdata *, void *); 208 void tx39icu_attach(struct device *, struct device *, void *); 209 int tx39icu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 210 211 void tx39_intr_dump(struct tx39icu_softc *); 212 void tx39_intr_decode(int, int *, int *); 213 void tx39_irqhigh_disestablish(tx_chipset_tag_t, int, int, int); 214 void tx39_irqhigh_establish(tx_chipset_tag_t, int, int, int, 215 int (*)(void *), void *); 216 void tx39_irqhigh_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 217 int tx39_irqhigh(int, int); 218 219 CFATTACH_DECL(tx39icu, sizeof(struct tx39icu_softc), 220 tx39icu_match, tx39icu_attach, NULL, NULL); 221 222 int 223 tx39icu_match(struct device *parent, struct cfdata *cf, void *aux) 224 { 225 226 return (ATTACH_FIRST); 227 } 228 229 void 230 tx39icu_attach(struct device *parent, struct device *self, void *aux) 231 { 232 struct txsim_attach_args *ta = aux; 233 struct tx39icu_softc *sc = (void *)self; 234 tx_chipset_tag_t tc = ta->ta_tc; 235 txreg_t reg, *regs; 236 int i; 237 238 printf("\n"); 239 sc->sc_tc = ta->ta_tc; 240 241 regs = sc->sc_regs; 242 regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 243 regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 244 regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 245 regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 246 regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 247 regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 248 #ifdef TX392X 249 regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 250 regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 251 #endif 252 #ifdef TX39ICU_DEBUG 253 printf("\t[Windows CE setting]\n"); 254 tx39_intr_dump(sc); 255 #endif /* TX39ICU_DEBUG */ 256 257 #ifdef WINCE_DEFAULT_SETTING 258 #warning WINCE_DEFAULT_SETTING 259 #else /* WINCE_DEFAULT_SETTING */ 260 /* Disable IRQLOW */ 261 tx_conf_write(tc, TX39_INTRENABLE1_REG, 0); 262 tx_conf_write(tc, TX39_INTRENABLE2_REG, 0); 263 tx_conf_write(tc, TX39_INTRENABLE3_REG, 0); 264 tx_conf_write(tc, TX39_INTRENABLE4_REG, 0); 265 tx_conf_write(tc, TX39_INTRENABLE5_REG, 0); 266 #ifdef TX392X 267 tx_conf_write(tc, TX39_INTRENABLE7_REG, 0); 268 tx_conf_write(tc, TX39_INTRENABLE8_REG, 0); 269 #endif /* TX392X */ 270 271 /* Disable IRQHIGH */ 272 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 273 reg &= ~TX39_INTRENABLE6_PRIORITYMASK_MASK; 274 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 275 #endif /* WINCE_DEFAULT_SETTING */ 276 277 /* Clear all pending interrupts */ 278 tx_conf_write(tc, TX39_INTRCLEAR1_REG, 279 tx_conf_read(tc, TX39_INTRSTATUS1_REG)); 280 tx_conf_write(tc, TX39_INTRCLEAR2_REG, 281 tx_conf_read(tc, TX39_INTRSTATUS2_REG)); 282 tx_conf_write(tc, TX39_INTRCLEAR3_REG, 283 tx_conf_read(tc, TX39_INTRSTATUS3_REG)); 284 tx_conf_write(tc, TX39_INTRCLEAR4_REG, 285 tx_conf_read(tc, TX39_INTRSTATUS4_REG)); 286 tx_conf_write(tc, TX39_INTRCLEAR5_REG, 287 tx_conf_read(tc, TX39_INTRSTATUS5_REG)); 288 #ifdef TX392X 289 tx_conf_write(tc, TX39_INTRCLEAR7_REG, 290 tx_conf_read(tc, TX39_INTRSTATUS7_REG)); 291 tx_conf_write(tc, TX39_INTRCLEAR8_REG, 292 tx_conf_read(tc, TX39_INTRSTATUS8_REG)); 293 #endif /* TX392X */ 294 295 /* Enable global interrupts */ 296 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 297 reg |= TX39_INTRENABLE6_GLOBALEN; 298 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 299 300 /* Initialize IRQHIGH interrupt handler holder*/ 301 for (i = 0; i < TX39_IRQHIGH_MAX; i++) { 302 TAILQ_INIT(&sc->sc_he_head[i]); 303 } 304 #ifdef USE_POLL 305 /* Initialize polling handler holder */ 306 TAILQ_INIT(&sc->sc_p_head); 307 #endif /* USE_POLL */ 308 309 /* Register interrupt module myself */ 310 tx_conf_register_intr(tc, self); 311 } 312 313 void 314 TX_INTR(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending) 315 { 316 struct tx39icu_softc *sc; 317 tx_chipset_tag_t tc; 318 txreg_t reg, pend, *regs; 319 int i, j; 320 321 uvmexp.intrs++; 322 323 #ifdef __HAVE_FAST_SOFTINTS 324 if ((ipending & MIPS_HARD_INT_MASK) == 0) 325 goto softintr; 326 #endif 327 328 tc = tx_conf_get_tag(); 329 sc = tc->tc_intrt; 330 /* 331 * Read regsiter ASAP 332 */ 333 regs = sc->sc_regs; 334 regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 335 regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 336 regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 337 regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 338 regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 339 regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 340 #ifdef TX392X 341 regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 342 regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 343 #endif 344 345 #ifdef TX39ICU_DEBUG 346 if (!(ipending & MIPS_INT_MASK_4) && !(ipending & MIPS_INT_MASK_2)) { 347 dbg_bit_print(ipending); 348 panic("bogus HwInt"); 349 } 350 if (tx39icu_debug > 1) { 351 tx39_intr_dump(sc); 352 } 353 #endif /* TX39ICU_DEBUG */ 354 355 /* IRQHIGH */ 356 if (ipending & MIPS_INT_MASK_4) { 357 tx39_irqhigh_intr(ipending, pc, status, cause); 358 359 #ifdef __HAVE_FAST_SOFTINTS 360 goto softintr; 361 #endif 362 } 363 364 /* IRQLOW */ 365 if (ipending & MIPS_INT_MASK_2) { 366 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 367 int ofs; 368 #ifdef TX392X 369 if (i == 6) 370 continue; 371 #endif /* TX392X */ 372 ofs = TX39_INTRSTATUS_REG(i); 373 pend = sc->sc_regs[i]; 374 reg = sc->sc_le_mask[i] & pend; 375 /* Clear interrupts */ 376 tx_conf_write(tc, ofs, reg); 377 /* Dispatch handler */ 378 for (j = 0 ; j < 32; j++) { 379 if ((reg & (1 << j)) && 380 sc->sc_le_fun[i][j]) { 381 #ifdef TX39ICU_DEBUG 382 if (tx39icu_debug > 1) { 383 tx39intrvec = (i << 16) | j; 384 DPRINTF("IRQLOW %d:%d\n", i, j); 385 } 386 #endif /* TX39ICU_DEBUG */ 387 (*sc->sc_le_fun[i][j]) 388 (sc->sc_le_arg[i][j]); 389 390 } 391 } 392 #ifdef TX39ICU_DEBUG_PRINT_PENDING_INTERRUPT 393 pend &= ~reg; 394 if (pend) { 395 printf("%d pending:", i); 396 dbg_bit_print(pend); 397 } 398 #endif 399 400 } 401 } 402 #ifdef TX39_WATCHDOGTIMER 403 { 404 extern int tx39biu_intr(void *); 405 /* Bus error (If watch dog timer is enabled)*/ 406 if (ipending & MIPS_INT_MASK_1) { 407 tx39biu_intr(0); /* Clear bus error */ 408 } 409 } 410 #endif 411 #if 0 412 /* reset priority mask */ 413 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 414 reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, 0xffff); 415 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 416 #endif 417 418 #ifdef __HAVE_FAST_SOFTINTS 419 softintr: 420 _splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE); 421 softintr(ipending); 422 #endif 423 } 424 425 int 426 tx39_irqhigh(int set, int bit) 427 { 428 int i, n; 429 430 n = sizeof irqhigh_list / sizeof (struct irqhigh_list); 431 for (i = 0; i < n; i++) { 432 if (irqhigh_list[i].qh_set == set && 433 irqhigh_list[i].qh_bit == bit) 434 return (irqhigh_list[i].qh_pri); 435 } 436 437 return (0); 438 } 439 440 void 441 tx39_irqhigh_intr(u_int32_t ipending, u_int32_t pc, u_int32_t status, 442 u_int32_t cause) 443 { 444 struct txintr_high_entry *he; 445 struct tx39icu_softc *sc; 446 struct clockframe cf; 447 tx_chipset_tag_t tc; 448 int i, pri, ofs, set; 449 txreg_t he_mask; 450 451 tc = tx_conf_get_tag(); 452 sc = tc->tc_intrt; 453 pri = TX39_INTRSTATUS6_INTVECT(sc->sc_regs[0]); 454 455 if (pri == TX39_INTRPRI13_TIMER_PERIODIC) { 456 tx_conf_write(tc, TX39_INTRCLEAR5_REG, 457 TX39_INTRSTATUS5_PERINT); 458 cf.pc = pc; 459 cf.sr = status; 460 hardclock(&cf); 461 462 return; 463 } 464 465 /* Handle all pending IRQHIGH interrupts */ 466 for (i = pri; i > 0; i--) { 467 TAILQ_FOREACH(he, &sc->sc_he_head[i], he_link) { 468 set = he->he_set; 469 he_mask = he->he_mask; 470 if (he_mask & (sc->sc_regs[set])) { 471 ofs = TX39_INTRSTATUS_REG(set); 472 /* Clear interrupt */ 473 tx_conf_write(tc, ofs, he_mask); 474 #ifdef TX39ICU_DEBUG 475 if (tx39icu_debug > 1) { 476 tx39intrvec = (set << 16) | 477 (ffs(he_mask) - 1); 478 DPRINTF("IRQHIGH: %d:%d\n", 479 set, ffs(he_mask) - 1); 480 } 481 #endif /* TX39ICU_DEBUG */ 482 /* Dispatch handler */ 483 (*he->he_fun)(he->he_arg); 484 } 485 } 486 } 487 } 488 489 void 490 tx39_intr_decode(int intr, int *set, int *bit) 491 { 492 if (!intr || intr >= (TX39_INTRSET_MAX + 1) * 32 493 #ifdef TX392X 494 || intr == 6 495 #endif /* TX392X */ 496 ) { 497 panic("tx39icu_decode: bogus intrrupt line. %d", intr); 498 } 499 *set = intr / 32; 500 *bit = intr % 32; 501 } 502 503 void 504 tx39_irqhigh_establish(tx_chipset_tag_t tc, int set, int bit, int pri, 505 int (*ih_fun)(void *), void *ih_arg) 506 { 507 struct tx39icu_softc *sc; 508 struct txintr_high_entry *he; 509 txreg_t reg; 510 511 sc = tc->tc_intrt; 512 /* 513 * Add new entry to `pri' priority 514 */ 515 if (!(he = malloc(sizeof(struct txintr_high_entry), 516 M_DEVBUF, M_NOWAIT))) { 517 panic ("tx39_irqhigh_establish: no memory."); 518 } 519 memset(he, 0, sizeof(struct txintr_high_entry)); 520 he->he_set = set; 521 he->he_mask= (1 << bit); 522 he->he_fun = ih_fun; 523 he->he_arg = ih_arg; 524 TAILQ_INSERT_TAIL(&sc->sc_he_head[pri], he, he_link); 525 /* 526 * Enable interrupt on this priority. 527 */ 528 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 529 reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, (1 << pri)); 530 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 531 } 532 533 void 534 tx39_irqhigh_disestablish(tx_chipset_tag_t tc, int set, int bit, int pri) 535 { 536 struct tx39icu_softc *sc; 537 struct txintr_high_entry *he; 538 txreg_t reg; 539 540 sc = tc->tc_intrt; 541 TAILQ_FOREACH(he, &sc->sc_he_head[pri], he_link) { 542 if (he->he_set == set && he->he_mask == (1 << bit)) { 543 TAILQ_REMOVE(&sc->sc_he_head[pri], he, he_link); 544 free(he, M_DEVBUF); 545 break; 546 } 547 } 548 549 if (TAILQ_EMPTY(&sc->sc_he_head[pri])) { 550 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 551 reg &= ~(1 << pri); 552 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 553 } 554 } 555 556 557 void * 558 tx_intr_establish(tx_chipset_tag_t tc, int line, int mode, int level, 559 int (*ih_fun)(void *), void *ih_arg) 560 { 561 struct tx39icu_softc *sc; 562 txreg_t reg; 563 int bit, set, highpri, ofs; 564 565 sc = tc->tc_intrt; 566 567 tx39_intr_decode(line, &set, &bit); 568 569 sc->sc_le_fun[set][bit] = ih_fun; 570 sc->sc_le_arg[set][bit] = ih_arg; 571 DPRINTF("tx_intr_establish: %d:%d", set, bit); 572 573 if ((highpri = tx39_irqhigh(set, bit))) { 574 tx39_irqhigh_establish(tc, set, bit, highpri, 575 ih_fun, ih_arg); 576 DPRINTF("(high)\n"); 577 } else { 578 /* Set mask for acknowledge. */ 579 sc->sc_le_mask[set] |= (1 << bit); 580 /* Enable interrupt */ 581 ofs = TX39_INTRENABLE_REG(set); 582 reg = tx_conf_read(tc, ofs); 583 reg |= (1 << bit); 584 tx_conf_write(tc, ofs, reg); 585 DPRINTF("(low)\n"); 586 } 587 588 return ((void *)line); 589 } 590 591 void 592 tx_intr_disestablish(tx_chipset_tag_t tc, void *arg) 593 { 594 struct tx39icu_softc *sc; 595 int set, bit, highpri, ofs; 596 txreg_t reg; 597 598 sc = tc->tc_intrt; 599 600 tx39_intr_decode((int)arg, &set, &bit); 601 DPRINTF("tx_intr_disestablish: %d:%d", set, bit); 602 603 if ((highpri = tx39_irqhigh(set, bit))) { 604 tx39_irqhigh_disestablish(tc, set, bit, highpri); 605 DPRINTF("(high)\n"); 606 } else { 607 sc->sc_le_fun[set][bit] = 0; 608 sc->sc_le_arg[set][bit] = 0; 609 sc->sc_le_mask[set] &= ~(1 << bit); 610 ofs = TX39_INTRENABLE_REG(set); 611 reg = tx_conf_read(tc, ofs); 612 reg &= ~(1 << bit); 613 tx_conf_write(tc, ofs, reg); 614 DPRINTF("(low)\n"); 615 } 616 } 617 618 u_int32_t 619 tx_intr_status(tx_chipset_tag_t tc, int r) 620 { 621 struct tx39icu_softc *sc = tc->tc_intrt; 622 623 if (r < 0 || r >= TX39_INTRSET_MAX + 1) 624 panic("tx_intr_status: invalid index %d", r); 625 626 return (u_int32_t)(sc->sc_regs[r]); 627 } 628 629 #ifdef USE_POLL 630 void * 631 tx39_poll_establish(tx_chipset_tag_t tc, int interval, int level, 632 int (*ih_fun)(void *), void *ih_arg) 633 { 634 struct tx39icu_softc *sc; 635 struct txpoll_entry *p; 636 int s; 637 void *ret; 638 639 s = splhigh(); 640 sc = tc->tc_intrt; 641 642 if (!(p = malloc(sizeof(struct txpoll_entry), 643 M_DEVBUF, M_NOWAIT))) { 644 panic ("tx39_poll_establish: no memory."); 645 } 646 memset(p, 0, sizeof(struct txpoll_entry)); 647 648 p->p_fun = ih_fun; 649 p->p_arg = ih_arg; 650 p->p_cnt = interval; 651 652 if (!sc->sc_polling) { 653 tx39clock_alarm_set(tc, 33); /* 33 msec */ 654 655 if (!(sc->sc_poll_ih = 656 tx_intr_establish( 657 tc, MAKEINTR(5, TX39_INTRSTATUS5_ALARMINT), 658 IST_EDGE, level, tx39_poll_intr, sc))) { 659 printf("tx39_poll_establish: can't hook\n"); 660 661 splx(s); 662 return (0); 663 } 664 } 665 666 sc->sc_polling++; 667 p->p_desc = sc->sc_polling; 668 TAILQ_INSERT_TAIL(&sc->sc_p_head, p, p_link); 669 ret = (void *)p->p_desc; 670 671 splx(s); 672 return (ret); 673 } 674 675 void 676 tx39_poll_disestablish(tx_chipset_tag_t tc, void *arg) 677 { 678 struct tx39icu_softc *sc; 679 struct txpoll_entry *p; 680 int s, desc; 681 682 s = splhigh(); 683 sc = tc->tc_intrt; 684 685 desc = (int)arg; 686 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 687 if (p->p_desc == desc) { 688 TAILQ_REMOVE(&sc->sc_p_head, p, p_link); 689 free(p, M_DEVBUF); 690 break; 691 } 692 } 693 694 if (TAILQ_EMPTY(&sc->sc_p_head)) { 695 sc->sc_polling = 0; 696 tx_intr_disestablish(tc, sc->sc_poll_ih); 697 } 698 699 splx(s); 700 return; 701 } 702 703 int 704 tx39_poll_intr(void *arg) 705 { 706 struct tx39icu_softc *sc = arg; 707 struct txpoll_entry *p; 708 709 tx39clock_alarm_refill(sc->sc_tc); 710 711 if (!sc->sc_polling) { 712 return (0); 713 } 714 sc->sc_pollcnt++; 715 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 716 if (sc->sc_pollcnt % p->p_cnt == 0) { 717 if ((*p->p_fun)(p->p_arg) == POLL_END) 718 goto disestablish; 719 } 720 } 721 722 return (0); 723 724 disestablish: 725 TAILQ_REMOVE(&sc->sc_p_head, p, p_link); 726 free(p, M_DEVBUF); 727 if (TAILQ_EMPTY(&sc->sc_p_head)) { 728 sc->sc_polling = 0; 729 tx_intr_disestablish(sc->sc_tc, sc->sc_poll_ih); 730 } 731 732 return (0); 733 } 734 #endif /* USE_POLL */ 735 736 void 737 tx39_intr_dump(struct tx39icu_softc *sc) 738 { 739 tx_chipset_tag_t tc = sc->sc_tc; 740 int i, j, ofs; 741 txreg_t reg; 742 char msg[16]; 743 744 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 745 #ifdef TX392X 746 if (i == 6) 747 continue; 748 #endif /* TX392X */ 749 for (reg = j = 0; j < 32; j++) { 750 if (tx39_irqhigh(i, j)) { 751 reg |= (1 << j); 752 } 753 } 754 sprintf(msg, "%d high", i); 755 dbg_bit_print_msg(reg, msg); 756 sprintf(msg, "%d status", i); 757 dbg_bit_print_msg(sc->sc_regs[i], msg); 758 ofs = TX39_INTRENABLE_REG(i); 759 reg = tx_conf_read(tc, ofs); 760 sprintf(msg, "%d enable", i); 761 dbg_bit_print_msg(reg, msg); 762 } 763 reg = sc->sc_regs[0]; 764 printf("<%s><%s> vector=%2d\t\t[6 status]\n", 765 reg & TX39_INTRSTATUS6_IRQHIGH ? "HI" : "--", 766 reg & TX39_INTRSTATUS6_IRQLOW ? "LO" : "--", 767 TX39_INTRSTATUS6_INTVECT(reg)); 768 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 769 __dbg_bit_print(reg, sizeof(reg), 0, 18, "6 enable", 770 DBG_BIT_PRINT_COUNT); 771 772 } 773
Indexes created Fri Oct 31 11:10:07 GMT 2025