tx39icu.c revision 1.3
1 /* $NetBSD: tx39icu.c,v 1.3 1999/12/22 15:35:35 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include "opt_tx39_debug.h" 29 #include "opt_use_poll.h" 30 #include "opt_tx39icudebug.h" 31 #include "opt_tx39_watchdogtimer.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/malloc.h> 37 #include <sys/queue.h> 38 #define TAILQ_FOREACH(var, head, field) \ 39 for (var = TAILQ_FIRST(head); var; var = TAILQ_NEXT(var, field)) 40 #define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) 41 42 #include <mips/cpuregs.h> 43 #include <machine/bus.h> 44 45 #include <hpcmips/tx/tx39var.h> 46 #include <hpcmips/tx/tx39icureg.h> 47 48 #include <machine/clock_machdep.h> 49 #include <machine/cpu.h> 50 #include <dev/dec/clockvar.h> 51 52 #undef TX39ICUDEBUG_PRINT_PENDING_INTERRUPT /* For explorer. good luck! */ 53 54 #ifdef TX39ICUDEBUG 55 #define DPRINTF(arg) printf arg 56 #else 57 #define DPRINTF(arg) 58 #endif 59 u_int32_t tx39intrvec; /* debug use */ 60 61 /* IRQHIGH lines list */ 62 static struct irqhigh_list { 63 int qh_pri; /* IRQHIGH priority */ 64 int qh_set; /* Register set */ 65 int qh_bit; /* bit offset in the register set */ 66 } irqhigh_list[] = { 67 {15, 5, 25}, /* POSPWROKINT */ 68 {15, 5, 24}, /* NEGPWROKINT */ 69 {14, 5, 30}, /* ALARMINT*/ 70 {13, 5, 29}, /* PERINT */ 71 #ifdef TX391X 72 {12, 2, 3}, /* MBUSPOSINT */ 73 {12, 2, 2}, /* MBUSNEGINT */ 74 {11, 2, 31}, /* UARTARXINT */ 75 {10, 2, 21}, /* UARTBRXINT */ 76 {9, 3, 19}, /* MFIOPOSINT19 */ 77 {9, 3, 18}, /* MFIOPOSINT18 */ 78 {9, 3, 17}, /* MFIOPOSINT17 */ 79 {9, 3, 16}, /* MFIOPOSINT16 */ 80 {8, 3, 1}, /* MFIOPOSINT1 */ 81 {8, 3, 0}, /* MFIOPOSINT0 */ 82 {8, 5, 13}, /* IOPOSINT6 */ 83 {8, 5, 12}, /* IOPOSINT5 */ 84 {7, 4, 19}, /* MFIONEGINT19 */ 85 {7, 4, 18}, /* MFIONEGINT18 */ 86 {7, 4, 17}, /* MFIONEGINT17 */ 87 {7, 4, 16}, /* MFIONEGINT16 */ 88 {6, 4, 1}, /* MFIONEGINT1 */ 89 {6, 4, 0}, /* MFIONEGINT0 */ 90 {6, 5, 6}, /* IONEGINT6 */ 91 {6, 5, 5}, /* IONEGINT5 */ 92 {5, 2, 5}, /* MBUSDMAFULLINT */ 93 #endif /* TX391X */ 94 #ifdef TX392X 95 {12, 2, 31}, /* UARTARXINT */ 96 {12, 2, 21}, /* UARTBRXINT */ 97 {11, 3, 19}, /* MFIOPOSINT19 */ 98 {11, 3, 18}, /* MFIOPOSINT18 */ 99 {11, 3, 17}, /* MFIOPOSINT17 */ 100 {11, 3, 16}, /* MFIOPOSINT16 */ 101 {10, 3, 1}, /* MFIOPOSINT1 */ 102 {10, 3, 0}, /* MFIOPOSINT0 */ 103 {10, 5, 13}, /* IOPOSINT6 */ 104 {10, 5, 12}, /* IOPOSINT5 */ 105 {9, 4, 19}, /* MFIONEGINT19 */ 106 {9, 4, 18}, /* MFIONEGINT18 */ 107 {9, 4, 17}, /* MFIONEGINT17 */ 108 {9, 4, 16}, /* MFIONEGINT16 */ 109 {8, 4, 1}, /* MFIONEGINT1 */ 110 {8, 4, 0}, /* MFIONEGINT0 */ 111 {8, 5, 6}, /* IONEGINT6 */ 112 {8, 5, 5}, /* IONEGINT5 */ 113 {5, 7, 19}, /* IRRXCINT */ 114 {5, 7, 17}, /* IRRXEINT */ 115 #endif /* TX392X */ 116 {4, 1, 18}, /* SNDDMACNTINT */ 117 {3, 1, 17}, /* TELDMACNTINT */ 118 {2, 1, 27}, /* CHIDMACNTINT */ 119 {1, 5, 7}, /* IOPOSINT0 */ 120 {1, 5, 0} /* IONEGINT0 */ 121 }; 122 123 struct txintr_high_entry { 124 int he_set; 125 txreg_t he_mask; 126 int (*he_fun) __P((void*)); 127 void *he_arg; 128 TAILQ_ENTRY(txintr_high_entry) he_link; 129 }; 130 131 #ifdef USE_POLL 132 struct txpoll_entry{ 133 int p_cnt; /* dispatch interval */ 134 int p_desc; 135 int (*p_fun) __P((void*)); 136 void *p_arg; 137 TAILQ_ENTRY(txpoll_entry) p_link; 138 }; 139 int tx39_poll_intr __P((void*)); 140 #endif /* USE_POLL */ 141 142 struct tx39icu_softc { 143 struct device sc_dev; 144 tx_chipset_tag_t sc_tc; 145 /* IRQLOW */ 146 txreg_t sc_le_mask[TX39_INTRSET_MAX + 1]; 147 int (*sc_le_fun[TX39_INTRSET_MAX + 1][32]) __P((void*)); 148 void *sc_le_arg[TX39_INTRSET_MAX + 1][32]; 149 /* IRQHIGH */ 150 TAILQ_HEAD(, txintr_high_entry) sc_he_head[TX39_IRQHIGH_MAX]; 151 /* Register */ 152 txreg_t sc_regs[TX39_INTRSET_MAX + 1]; 153 #ifdef USE_POLL 154 unsigned sc_pollcnt; 155 int sc_polling; 156 void *sc_poll_ih; 157 TAILQ_HEAD(, txpoll_entry) sc_p_head; 158 #endif /* USE_POLL */ 159 }; 160 161 int tx39icu_match __P((struct device*, struct cfdata*, void*)); 162 void tx39icu_attach __P((struct device*, struct device*, void*)); 163 int tx39icu_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t)); 164 165 void tx39_intr_dump __P((struct tx39icu_softc*)); 166 void tx39_intr_decode __P((int, int*, int*)); 167 void tx39_irqhigh_disestablish __P((tx_chipset_tag_t, int, int, int)); 168 void tx39_irqhigh_establish __P((tx_chipset_tag_t, int, int, int, int (*) __P((void*)), void*)); 169 void tx39_irqhigh_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t)); 170 int tx39_irqhigh __P((int, int)); 171 172 struct cfattach tx39icu_ca = { 173 sizeof(struct tx39icu_softc), tx39icu_match, tx39icu_attach 174 }; 175 176 int 177 tx39icu_match(parent, cf, aux) 178 struct device *parent; 179 struct cfdata *cf; 180 void *aux; 181 { 182 return 2; /* 1st attach group of txsim */ 183 } 184 185 void 186 tx39icu_attach(parent, self, aux) 187 struct device *parent; 188 struct device *self; 189 void *aux; 190 { 191 struct txsim_attach_args *ta = aux; 192 struct tx39icu_softc *sc = (void*)self; 193 tx_chipset_tag_t tc = ta->ta_tc; 194 txreg_t reg; 195 int i; 196 197 printf("\n"); 198 sc->sc_tc = ta->ta_tc; 199 200 sc->sc_regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 201 sc->sc_regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 202 sc->sc_regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 203 sc->sc_regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 204 sc->sc_regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 205 sc->sc_regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 206 #ifdef TX392X 207 sc->sc_regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 208 sc->sc_regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 209 #endif 210 #ifdef TX39ICUDEBUG 211 printf("\t[Windows CE setting]\n"); 212 tx39_intr_dump(sc); 213 #endif /* TX39ICUDEBUG */ 214 215 #ifdef WINCE_DEFAULT_SETTING 216 #warning WINCE_DEFAULT_SETTING 217 #else /* WINCE_DEFAULT_SETTING */ 218 /* Disable IRQLOW */ 219 tx_conf_write(tc, TX39_INTRENABLE1_REG, 0); 220 tx_conf_write(tc, TX39_INTRENABLE2_REG, 0); 221 tx_conf_write(tc, TX39_INTRENABLE3_REG, 0); 222 tx_conf_write(tc, TX39_INTRENABLE4_REG, 0); 223 tx_conf_write(tc, TX39_INTRENABLE5_REG, 0); 224 #ifdef TX392X 225 tx_conf_write(tc, TX39_INTRENABLE7_REG, 0); 226 tx_conf_write(tc, TX39_INTRENABLE8_REG, 0); 227 #endif /* TX392X */ 228 229 /* Disable IRQHIGH */ 230 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 231 reg &= ~TX39_INTRENABLE6_PRIORITYMASK_MASK; 232 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 233 #endif /* WINCE_DEFAULT_SETTING */ 234 235 /* Clear all pending interrupts */ 236 tx_conf_write(tc, TX39_INTRCLEAR1_REG, tx_conf_read(tc, TX39_INTRSTATUS1_REG)); 237 tx_conf_write(tc, TX39_INTRCLEAR2_REG, tx_conf_read(tc, TX39_INTRSTATUS2_REG)); 238 tx_conf_write(tc, TX39_INTRCLEAR3_REG, tx_conf_read(tc, TX39_INTRSTATUS3_REG)); 239 tx_conf_write(tc, TX39_INTRCLEAR4_REG, tx_conf_read(tc, TX39_INTRSTATUS4_REG)); 240 tx_conf_write(tc, TX39_INTRCLEAR5_REG, tx_conf_read(tc, TX39_INTRSTATUS5_REG)); 241 #ifdef TX392X 242 tx_conf_write(tc, TX39_INTRCLEAR7_REG, tx_conf_read(tc, TX39_INTRSTATUS7_REG)); 243 tx_conf_write(tc, TX39_INTRCLEAR8_REG, tx_conf_read(tc, TX39_INTRSTATUS8_REG)); 244 #endif /* TX392X */ 245 246 /* Enable global interrupts */ 247 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 248 reg |= TX39_INTRENABLE6_GLOBALEN; 249 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 250 251 /* Initialize IRQHIGH interrupt handler holder*/ 252 for (i = 0; i < TX39_IRQHIGH_MAX; i++) { 253 TAILQ_INIT(&sc->sc_he_head[i]); 254 } 255 #ifdef USE_POLL 256 /* Initialize polling handler holder */ 257 TAILQ_INIT(&sc->sc_p_head); 258 #endif /* USE_POLL */ 259 260 /* Register interrupt module myself */ 261 tx_conf_register_intr(tc, self); 262 } 263 264 int 265 tx39icu_intr(mask, pc, status, cause) 266 u_int32_t mask; 267 u_int32_t pc; 268 u_int32_t status; 269 u_int32_t cause; 270 { 271 struct tx39icu_softc *sc; 272 tx_chipset_tag_t tc; 273 txreg_t reg, pend; 274 int i, j; 275 276 tc = tx_conf_get_tag(); 277 sc = tc->tc_intrt; 278 /* 279 * Read regsiter ASAP 280 */ 281 sc->sc_regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 282 sc->sc_regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 283 sc->sc_regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 284 sc->sc_regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 285 sc->sc_regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 286 sc->sc_regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 287 #ifdef TX392X 288 sc->sc_regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 289 sc->sc_regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 290 #endif 291 292 #ifdef TX39ICUDEBUG 293 if (!(mask & MIPS_INT_MASK_4) && !(mask & MIPS_INT_MASK_2)) { 294 bitdisp(mask); 295 panic("bogus HwInt"); 296 } 297 #ifdef TX39_DEBUG 298 if (tx39debugflag) { 299 tx39_intr_dump(sc); 300 } 301 #endif 302 #endif /* TX39ICUDEBUG */ 303 304 /* IRQHIGH */ 305 if (mask & MIPS_INT_MASK_4) { 306 tx39_irqhigh_intr(mask, pc, status, cause); 307 308 return 0; 309 } 310 311 /* IRQLOW */ 312 if (mask & MIPS_INT_MASK_2) { 313 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 314 int ofs; 315 #ifdef TX392X 316 if (i == 6) 317 continue; 318 #endif /* TX392X */ 319 ofs = TX39_INTRSTATUS_REG(i); 320 pend = sc->sc_regs[i]; 321 reg = sc->sc_le_mask[i] & pend; 322 /* Clear interrupts */ 323 tx_conf_write(tc, ofs, reg); 324 /* Dispatch handler */ 325 for (j = 0 ; j < 32; j++) { 326 if ((reg & (1 << j)) && 327 sc->sc_le_fun[i][j]) { 328 #ifdef TX39_DEBUG 329 tx39intrvec = (i << 16) | j; 330 if (tx39debugflag) { 331 DPRINTF(("IRQLOW %d:%d\n", 332 i, j)); 333 } 334 #endif /* TX39_DEBUG */ 335 (*sc->sc_le_fun[i][j]) 336 (sc->sc_le_arg[i][j]); 337 338 } 339 } 340 #ifdef TX39ICUDEBUG_PRINT_PENDING_INTERRUPT 341 pend &= ~reg; 342 if (pend) { 343 printf("%d pending:", i); 344 __bitdisp(pend, 0, 31, 0, 1); 345 } 346 #endif 347 348 } 349 } 350 #ifdef TX39_WATCHDOGTIMER 351 /* Bus error (If watch dog timer is enabled)*/ 352 if (mask & MIPS_INT_MASK_1) { 353 tx39biu_intr(0); /* Clear bus error */ 354 } 355 #endif 356 return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 357 } 358 359 int 360 tx39_irqhigh(set, bit) 361 int set, bit; 362 { 363 int i, n; 364 365 n = sizeof irqhigh_list / sizeof (struct irqhigh_list); 366 for (i = 0; i < n; i++) { 367 if (irqhigh_list[i].qh_set == set && 368 irqhigh_list[i].qh_bit == bit) 369 return irqhigh_list[i].qh_pri; 370 } 371 372 return 0; 373 } 374 375 void 376 tx39_irqhigh_intr(mask, pc, status, cause) 377 u_int32_t mask; 378 u_int32_t pc; 379 u_int32_t status; 380 u_int32_t cause; 381 { 382 struct txintr_high_entry *he; 383 struct tx39icu_softc *sc; 384 struct clockframe cf; 385 tx_chipset_tag_t tc; 386 int i, pri, ofs, set; 387 txreg_t he_mask; 388 389 tc = tx_conf_get_tag(); 390 sc = tc->tc_intrt; 391 pri = TX39_INTRSTATUS6_INTVECT(sc->sc_regs[0]); 392 393 if (pri == TX39_INTRPRI13_TIMER_PERIODIC) { 394 tx_conf_write(tc, TX39_INTRCLEAR5_REG, 395 TX39_INTRSTATUS5_PERINT); 396 cf.pc = pc; 397 cf.sr = status; 398 hardclock(&cf); 399 intrcnt[HARDCLOCK]++; 400 401 return; 402 } 403 404 /* Handle all pending IRQHIGH interrupts */ 405 for (i = pri; i > 0; i--) { 406 TAILQ_FOREACH(he, &sc->sc_he_head[i], he_link) { 407 set = he->he_set; 408 he_mask = he->he_mask; 409 if (he_mask & (sc->sc_regs[set])) { 410 ofs = TX39_INTRSTATUS_REG(set); 411 /* Clear interrupt */ 412 tx_conf_write(tc, ofs, he_mask); 413 #ifdef TX39_DEBUG 414 tx39intrvec = (set << 16) | 415 (ffs(he_mask) - 1); 416 if (tx39debugflag) { 417 DPRINTF(("IRQHIGH: %d:%d\n", 418 set, ffs(he_mask) - 1)); 419 } 420 #endif /* TX39_DEBUG */ 421 /* Dispatch handler */ 422 (*he->he_fun)(he->he_arg); 423 } 424 } 425 } 426 } 427 428 void 429 tx39_intr_decode(intr, set, bit) 430 int intr; 431 int *set; 432 int *bit; 433 { 434 if (!intr || intr >= (TX39_INTRSET_MAX + 1) * 32 435 #ifdef TX392X 436 || intr == 6 437 #endif /* TX392X */ 438 ) { 439 panic("tx39icu_decode: bogus intrrupt line. %d", intr); 440 } 441 *set = intr / 32; 442 *bit = intr % 32; 443 } 444 445 void 446 tx39_irqhigh_establish(tc, set, bit, pri, ih_fun, ih_arg) 447 tx_chipset_tag_t tc; 448 int set; 449 int bit; 450 int pri; 451 int (*ih_fun) __P((void*)); 452 void *ih_arg; 453 { 454 struct tx39icu_softc *sc; 455 struct txintr_high_entry *he; 456 txreg_t reg; 457 458 sc = tc->tc_intrt; 459 /* 460 * Add new entry to `pri' priority. 461 */ 462 if (!(he = malloc(sizeof(struct txintr_high_entry), 463 M_DEVBUF, M_NOWAIT))) { 464 panic ("tx39_irqhigh_establish: no memory."); 465 } 466 memset(he, 0, sizeof(struct txintr_high_entry)); 467 he->he_set = set; 468 he->he_mask= (1 << bit); 469 he->he_fun = ih_fun; 470 he->he_arg = ih_arg; 471 TAILQ_INSERT_TAIL(&sc->sc_he_head[pri], he, he_link); 472 /* 473 * Enable interrupt on this priority. 474 */ 475 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 476 reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, (1 << pri)); 477 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 478 } 479 480 void 481 tx39_irqhigh_disestablish(tc, set, bit, pri) 482 tx_chipset_tag_t tc; 483 int set, bit, pri; 484 { 485 struct tx39icu_softc *sc; 486 struct txintr_high_entry *he; 487 txreg_t reg; 488 489 sc = tc->tc_intrt; 490 TAILQ_FOREACH(he, &sc->sc_he_head[pri], he_link) { 491 if (he->he_set == set && he->he_mask == (1 << bit)) { 492 TAILQ_REMOVE(&sc->sc_he_head[pri], he, he_link); 493 free(he, M_DEVBUF); 494 break; 495 } 496 } 497 498 if (TAILQ_EMPTY(&sc->sc_he_head[pri])) { 499 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 500 reg &= ~(1 << pri); 501 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 502 } 503 } 504 505 506 void* 507 tx_intr_establish(tc, line, mode, level, ih_fun, ih_arg) 508 tx_chipset_tag_t tc; 509 int line; 510 int mode; /* Trigger setting. but TX39 handles edge only. */ 511 int level; /* XXX not yet */ 512 int (*ih_fun) __P((void*)); 513 void *ih_arg; 514 { 515 struct tx39icu_softc *sc; 516 txreg_t reg; 517 int bit, set, highpri, ofs; 518 519 sc = tc->tc_intrt; 520 521 tx39_intr_decode(line, &set, &bit); 522 523 sc->sc_le_fun[set][bit] = ih_fun; 524 sc->sc_le_arg[set][bit] = ih_arg; 525 DPRINTF(("tx_intr_establish: %d:%d", set, bit)); 526 527 if ((highpri = tx39_irqhigh(set, bit))) { 528 tx39_irqhigh_establish(tc, set, bit, highpri, 529 ih_fun, ih_arg); 530 DPRINTF(("(high)\n")); 531 } else { 532 /* Set mask for acknowledge. */ 533 sc->sc_le_mask[set] |= (1 << bit); 534 /* Enable interrupt */ 535 ofs = TX39_INTRENABLE_REG(set); 536 reg = tx_conf_read(tc, ofs); 537 reg |= (1 << bit); 538 tx_conf_write(tc, ofs, reg); 539 DPRINTF(("(low)\n")); 540 } 541 542 return (void*)line; 543 } 544 545 void 546 tx_intr_disestablish(tc, arg) 547 tx_chipset_tag_t tc; 548 void *arg; 549 { 550 struct tx39icu_softc *sc; 551 int set, bit, highpri, ofs; 552 txreg_t reg; 553 554 sc = tc->tc_intrt; 555 556 tx39_intr_decode((int)arg, &set, &bit); 557 DPRINTF(("tx_intr_disestablish: %d:%d", set, bit)); 558 559 if ((highpri = tx39_irqhigh(set, bit))) { 560 tx39_irqhigh_disestablish(tc, set, bit, highpri); 561 DPRINTF(("(high)\n")); 562 } else { 563 sc->sc_le_fun[set][bit] = 0; 564 sc->sc_le_arg[set][bit] = 0; 565 sc->sc_le_mask[set] &= ~(1 << bit); 566 ofs = TX39_INTRENABLE_REG(set); 567 reg = tx_conf_read(tc, ofs); 568 reg &= ~(1 << bit); 569 tx_conf_write(tc, ofs, reg); 570 DPRINTF(("(low)\n")); 571 } 572 } 573 574 void 575 tx39_intr_dump(sc) 576 struct tx39icu_softc *sc; 577 { 578 tx_chipset_tag_t tc = sc->sc_tc; 579 int i, j, ofs; 580 txreg_t reg; 581 char msg[16]; 582 583 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 584 #ifdef TX392X 585 if (i == 6) 586 continue; 587 #endif /* TX392X */ 588 for (reg = j = 0; j < 32; j++) { 589 if (tx39_irqhigh(i, j)) { 590 reg |= (1 << j); 591 } 592 } 593 sprintf(msg, "%d high", i); 594 __bitdisp(reg, 32, 0, msg, 1); 595 sprintf(msg, "%d status", i); 596 __bitdisp(sc->sc_regs[i], 0, 31, msg, 1); 597 ofs = TX39_INTRENABLE_REG(i); 598 reg = tx_conf_read(tc, ofs); 599 sprintf(msg, "%d enable", i); 600 __bitdisp(reg, 0, 31, msg, 1); 601 } 602 reg = sc->sc_regs[0]; 603 printf("<%s><%s> vector=%2d\t\t[6 status]\n", 604 reg & TX39_INTRSTATUS6_IRQHIGH ? "HI" : "--", 605 reg & TX39_INTRSTATUS6_IRQLOW ? "LO" : "--", 606 TX39_INTRSTATUS6_INTVECT(reg)); 607 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 608 __bitdisp(reg, 0, 18, "6 enable", 1); 609 610 } 611 612 #ifdef USE_POLL 613 void* 614 tx39_poll_establish(tc, interval, mode, level, ih_fun, ih_arg) 615 tx_chipset_tag_t tc; 616 int interval; 617 int mode; /* Trigger setting. but TX39 handles edge only. */ 618 int level; /* XXX not yet */ 619 int (*ih_fun) __P((void*)); 620 void *ih_arg; 621 { 622 struct tx39icu_softc *sc; 623 struct txpoll_entry *p; 624 625 sc = tc->tc_intrt; 626 627 if (!(p = malloc(sizeof(struct txpoll_entry), 628 M_DEVBUF, M_NOWAIT))) { 629 panic ("tx39_poll_establish: no memory."); 630 } 631 memset(p, 0, sizeof(struct txpoll_entry)); 632 633 p->p_fun = ih_fun; 634 p->p_arg = ih_arg; 635 p->p_cnt = interval; 636 if (!sc->sc_polling) { 637 /* Hook VSync : TX39_INTRSTATUS1_LCDINT*/ 638 if (!(sc->sc_poll_ih = 639 tx_intr_establish( 640 #ifdef TX391X 641 tc, MAKEINTR(1, TX39_INTRSTATUS1_LCDINT), 642 #endif 643 #ifdef TX392X 644 tc, MAKEINTR(5, TX39_INTRSTATUS5_STPTIMERINT), 645 #endif 646 mode, level, tx39_poll_intr, sc))) { 647 printf("tx39_poll_establish: can't hook\n"); 648 return 0; 649 } 650 } 651 sc->sc_polling++; 652 p->p_desc = sc->sc_polling; 653 TAILQ_INSERT_TAIL(&sc->sc_p_head, p, p_link); 654 655 return (void*)p->p_desc; 656 } 657 658 void 659 tx39_poll_disestablish(tc, arg) 660 tx_chipset_tag_t tc; 661 void *arg; 662 { 663 struct tx39icu_softc *sc; 664 struct txpoll_entry *p; 665 int desc; 666 sc = tc->tc_intrt; 667 668 desc = (int)arg; 669 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 670 if (p->p_desc == desc) { 671 TAILQ_REMOVE(&sc->sc_p_head, p, p_link); 672 free(p, M_DEVBUF); 673 break; 674 } 675 } 676 if (TAILQ_EMPTY(&sc->sc_p_head)) { 677 sc->sc_polling = 0; 678 tx_intr_disestablish(tc, sc->sc_poll_ih); 679 } 680 } 681 682 int 683 tx39_poll_intr(arg) 684 void *arg; 685 { 686 struct tx39icu_softc *sc = arg; 687 struct txpoll_entry *p; 688 689 if (!sc->sc_polling) { 690 return 0; 691 } 692 sc->sc_pollcnt++; 693 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 694 if (sc->sc_pollcnt % p->p_cnt == 0) { 695 (*p->p_fun)(p->p_arg); 696 } 697 } 698 return 0; 699 } 700 #endif /* USE_POLL */ 701
Indexes created Thu Oct 30 23:09:54 GMT 2025