tx39icu.c revision 1.6
1 /* $NetBSD: tx39icu.c,v 1.6 2000/01/16 21:47:00 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include "opt_tx39_debug.h" 29 #include "opt_use_poll.h" 30 #include "opt_tx39icudebug.h" 31 #include "opt_tx39_watchdogtimer.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/malloc.h> 37 #include <sys/queue.h> 38 #define TAILQ_FOREACH(var, head, field) \ 39 for (var = TAILQ_FIRST(head); var; var = TAILQ_NEXT(var, field)) 40 #define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) 41 42 #include <mips/cpuregs.h> 43 #include <machine/bus.h> 44 45 #include <hpcmips/tx/tx39var.h> 46 #include <hpcmips/tx/tx39icureg.h> 47 #include <hpcmips/tx/tx39clockvar.h> 48 49 #include <machine/clock_machdep.h> 50 #include <machine/cpu.h> 51 #include <dev/dec/clockvar.h> 52 53 #undef TX39ICUDEBUG_PRINT_PENDING_INTERRUPT /* For explorer. good luck! */ 54 55 #ifdef TX39ICUDEBUG 56 #define DPRINTF(arg) printf arg 57 #else 58 #define DPRINTF(arg) 59 #endif 60 u_int32_t tx39intrvec; 61 62 /* IRQHIGH lines list */ 63 static const struct irqhigh_list { 64 int qh_pri; /* IRQHIGH priority */ 65 int qh_set; /* Register set */ 66 int qh_bit; /* bit offset in the register set */ 67 } irqhigh_list[] = { 68 {15, 5, 25}, /* POSPWROKINT */ 69 {15, 5, 24}, /* NEGPWROKINT */ 70 {14, 5, 30}, /* ALARMINT*/ 71 {13, 5, 29}, /* PERINT */ 72 #ifdef TX391X 73 {12, 2, 3}, /* MBUSPOSINT */ 74 {12, 2, 2}, /* MBUSNEGINT */ 75 {11, 2, 31}, /* UARTARXINT */ 76 {10, 2, 21}, /* UARTBRXINT */ 77 {9, 3, 19}, /* MFIOPOSINT19 */ 78 {9, 3, 18}, /* MFIOPOSINT18 */ 79 {9, 3, 17}, /* MFIOPOSINT17 */ 80 {9, 3, 16}, /* MFIOPOSINT16 */ 81 {8, 3, 1}, /* MFIOPOSINT1 */ 82 {8, 3, 0}, /* MFIOPOSINT0 */ 83 {8, 5, 13}, /* IOPOSINT6 */ 84 {8, 5, 12}, /* IOPOSINT5 */ 85 {7, 4, 19}, /* MFIONEGINT19 */ 86 {7, 4, 18}, /* MFIONEGINT18 */ 87 {7, 4, 17}, /* MFIONEGINT17 */ 88 {7, 4, 16}, /* MFIONEGINT16 */ 89 {6, 4, 1}, /* MFIONEGINT1 */ 90 {6, 4, 0}, /* MFIONEGINT0 */ 91 {6, 5, 6}, /* IONEGINT6 */ 92 {6, 5, 5}, /* IONEGINT5 */ 93 {5, 2, 5}, /* MBUSDMAFULLINT */ 94 #endif /* TX391X */ 95 #ifdef TX392X 96 {12, 2, 31}, /* UARTARXINT */ 97 {12, 2, 21}, /* UARTBRXINT */ 98 {11, 3, 19}, /* MFIOPOSINT19 */ 99 {11, 3, 18}, /* MFIOPOSINT18 */ 100 {11, 3, 17}, /* MFIOPOSINT17 */ 101 {11, 3, 16}, /* MFIOPOSINT16 */ 102 {10, 3, 1}, /* MFIOPOSINT1 */ 103 {10, 3, 0}, /* MFIOPOSINT0 */ 104 {10, 5, 13}, /* IOPOSINT6 */ 105 {10, 5, 12}, /* IOPOSINT5 */ 106 {9, 4, 19}, /* MFIONEGINT19 */ 107 {9, 4, 18}, /* MFIONEGINT18 */ 108 {9, 4, 17}, /* MFIONEGINT17 */ 109 {9, 4, 16}, /* MFIONEGINT16 */ 110 {8, 4, 1}, /* MFIONEGINT1 */ 111 {8, 4, 0}, /* MFIONEGINT0 */ 112 {8, 5, 6}, /* IONEGINT6 */ 113 {8, 5, 5}, /* IONEGINT5 */ 114 {5, 7, 19}, /* IRRXCINT */ 115 {5, 7, 17}, /* IRRXEINT */ 116 #endif /* TX392X */ 117 {4, 1, 18}, /* SNDDMACNTINT */ 118 {3, 1, 17}, /* TELDMACNTINT */ 119 {2, 1, 27}, /* CHIDMACNTINT */ 120 {1, 5, 7}, /* IOPOSINT0 */ 121 {1, 5, 0} /* IONEGINT0 */ 122 }; 123 124 struct txintr_high_entry { 125 int he_set; 126 txreg_t he_mask; 127 int (*he_fun) __P((void*)); 128 void *he_arg; 129 TAILQ_ENTRY(txintr_high_entry) he_link; 130 }; 131 132 #ifdef USE_POLL 133 struct txpoll_entry{ 134 int p_cnt; /* dispatch interval */ 135 int p_desc; 136 int (*p_fun) __P((void*)); 137 void *p_arg; 138 TAILQ_ENTRY(txpoll_entry) p_link; 139 }; 140 int tx39_poll_intr __P((void*)); 141 #endif /* USE_POLL */ 142 143 struct tx39icu_softc { 144 struct device sc_dev; 145 tx_chipset_tag_t sc_tc; 146 /* IRQLOW */ 147 txreg_t sc_le_mask[TX39_INTRSET_MAX + 1]; 148 int (*sc_le_fun[TX39_INTRSET_MAX + 1][32]) __P((void*)); 149 void *sc_le_arg[TX39_INTRSET_MAX + 1][32]; 150 /* IRQHIGH */ 151 TAILQ_HEAD(, txintr_high_entry) sc_he_head[TX39_IRQHIGH_MAX]; 152 /* Register */ 153 txreg_t sc_regs[TX39_INTRSET_MAX + 1]; 154 #ifdef USE_POLL 155 unsigned sc_pollcnt; 156 int sc_polling; 157 void *sc_poll_ih; 158 TAILQ_HEAD(, txpoll_entry) sc_p_head; 159 #endif /* USE_POLL */ 160 }; 161 162 int tx39icu_match __P((struct device*, struct cfdata*, void*)); 163 void tx39icu_attach __P((struct device*, struct device*, void*)); 164 int tx39icu_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t)); 165 166 void tx39_intr_dump __P((struct tx39icu_softc*)); 167 void tx39_intr_decode __P((int, int*, int*)); 168 void tx39_irqhigh_disestablish __P((tx_chipset_tag_t, int, int, int)); 169 void tx39_irqhigh_establish __P((tx_chipset_tag_t, int, int, int, 170 int (*) __P((void*)), void*)); 171 void tx39_irqhigh_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t)); 172 int tx39_irqhigh __P((int, int)); 173 174 struct cfattach tx39icu_ca = { 175 sizeof(struct tx39icu_softc), tx39icu_match, tx39icu_attach 176 }; 177 178 int 179 tx39icu_match(parent, cf, aux) 180 struct device *parent; 181 struct cfdata *cf; 182 void *aux; 183 { 184 return 2; /* 1st attach group of txsim */ 185 } 186 187 void 188 tx39icu_attach(parent, self, aux) 189 struct device *parent; 190 struct device *self; 191 void *aux; 192 { 193 struct txsim_attach_args *ta = aux; 194 struct tx39icu_softc *sc = (void*)self; 195 tx_chipset_tag_t tc = ta->ta_tc; 196 txreg_t reg; 197 int i; 198 199 printf("\n"); 200 sc->sc_tc = ta->ta_tc; 201 202 sc->sc_regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 203 sc->sc_regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 204 sc->sc_regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 205 sc->sc_regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 206 sc->sc_regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 207 sc->sc_regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 208 #ifdef TX392X 209 sc->sc_regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 210 sc->sc_regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 211 #endif 212 #ifdef TX39ICUDEBUG 213 printf("\t[Windows CE setting]\n"); 214 tx39_intr_dump(sc); 215 #endif /* TX39ICUDEBUG */ 216 217 #ifdef WINCE_DEFAULT_SETTING 218 #warning WINCE_DEFAULT_SETTING 219 #else /* WINCE_DEFAULT_SETTING */ 220 /* Disable IRQLOW */ 221 tx_conf_write(tc, TX39_INTRENABLE1_REG, 0); 222 tx_conf_write(tc, TX39_INTRENABLE2_REG, 0); 223 tx_conf_write(tc, TX39_INTRENABLE3_REG, 0); 224 tx_conf_write(tc, TX39_INTRENABLE4_REG, 0); 225 tx_conf_write(tc, TX39_INTRENABLE5_REG, 0); 226 #ifdef TX392X 227 tx_conf_write(tc, TX39_INTRENABLE7_REG, 0); 228 tx_conf_write(tc, TX39_INTRENABLE8_REG, 0); 229 #endif /* TX392X */ 230 231 /* Disable IRQHIGH */ 232 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 233 reg &= ~TX39_INTRENABLE6_PRIORITYMASK_MASK; 234 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 235 #endif /* WINCE_DEFAULT_SETTING */ 236 237 /* Clear all pending interrupts */ 238 tx_conf_write(tc, TX39_INTRCLEAR1_REG, 239 tx_conf_read(tc, TX39_INTRSTATUS1_REG)); 240 tx_conf_write(tc, TX39_INTRCLEAR2_REG, 241 tx_conf_read(tc, TX39_INTRSTATUS2_REG)); 242 tx_conf_write(tc, TX39_INTRCLEAR3_REG, 243 tx_conf_read(tc, TX39_INTRSTATUS3_REG)); 244 tx_conf_write(tc, TX39_INTRCLEAR4_REG, 245 tx_conf_read(tc, TX39_INTRSTATUS4_REG)); 246 tx_conf_write(tc, TX39_INTRCLEAR5_REG, 247 tx_conf_read(tc, TX39_INTRSTATUS5_REG)); 248 #ifdef TX392X 249 tx_conf_write(tc, TX39_INTRCLEAR7_REG, 250 tx_conf_read(tc, TX39_INTRSTATUS7_REG)); 251 tx_conf_write(tc, TX39_INTRCLEAR8_REG, 252 tx_conf_read(tc, TX39_INTRSTATUS8_REG)); 253 #endif /* TX392X */ 254 255 /* Enable global interrupts */ 256 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 257 reg |= TX39_INTRENABLE6_GLOBALEN; 258 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 259 260 /* Initialize IRQHIGH interrupt handler holder*/ 261 for (i = 0; i < TX39_IRQHIGH_MAX; i++) { 262 TAILQ_INIT(&sc->sc_he_head[i]); 263 } 264 #ifdef USE_POLL 265 /* Initialize polling handler holder */ 266 TAILQ_INIT(&sc->sc_p_head); 267 #endif /* USE_POLL */ 268 269 /* Register interrupt module myself */ 270 tx_conf_register_intr(tc, self); 271 } 272 273 int 274 tx39icu_intr(mask, pc, status, cause) 275 u_int32_t mask; 276 u_int32_t pc; 277 u_int32_t status; 278 u_int32_t cause; 279 { 280 struct tx39icu_softc *sc; 281 tx_chipset_tag_t tc; 282 txreg_t reg, pend; 283 int i, j; 284 285 tc = tx_conf_get_tag(); 286 sc = tc->tc_intrt; 287 /* 288 * Read regsiter ASAP 289 */ 290 sc->sc_regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 291 sc->sc_regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 292 sc->sc_regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 293 sc->sc_regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 294 sc->sc_regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 295 sc->sc_regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 296 #ifdef TX392X 297 sc->sc_regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 298 sc->sc_regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 299 #endif 300 301 #ifdef TX39ICUDEBUG 302 if (!(mask & MIPS_INT_MASK_4) && !(mask & MIPS_INT_MASK_2)) { 303 bitdisp(mask); 304 panic("bogus HwInt"); 305 } 306 #ifdef TX39_DEBUG 307 if (tx39debugflag) { 308 tx39_intr_dump(sc); 309 } 310 #endif 311 #endif /* TX39ICUDEBUG */ 312 313 /* IRQHIGH */ 314 if (mask & MIPS_INT_MASK_4) { 315 tx39_irqhigh_intr(mask, pc, status, cause); 316 317 return 0; 318 } 319 320 /* IRQLOW */ 321 if (mask & MIPS_INT_MASK_2) { 322 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 323 int ofs; 324 #ifdef TX392X 325 if (i == 6) 326 continue; 327 #endif /* TX392X */ 328 ofs = TX39_INTRSTATUS_REG(i); 329 pend = sc->sc_regs[i]; 330 reg = sc->sc_le_mask[i] & pend; 331 /* Clear interrupts */ 332 tx_conf_write(tc, ofs, reg); 333 /* Dispatch handler */ 334 for (j = 0 ; j < 32; j++) { 335 if ((reg & (1 << j)) && 336 sc->sc_le_fun[i][j]) { 337 #ifdef TX39_DEBUG 338 tx39intrvec = (i << 16) | j; 339 if (tx39debugflag) { 340 DPRINTF(("IRQLOW %d:%d\n", 341 i, j)); 342 } 343 #endif /* TX39_DEBUG */ 344 (*sc->sc_le_fun[i][j]) 345 (sc->sc_le_arg[i][j]); 346 347 } 348 } 349 #ifdef TX39ICUDEBUG_PRINT_PENDING_INTERRUPT 350 pend &= ~reg; 351 if (pend) { 352 printf("%d pending:", i); 353 __bitdisp(pend, 0, 31, 0, 1); 354 } 355 #endif 356 357 } 358 } 359 #ifdef TX39_WATCHDOGTIMER 360 { 361 extern int tx39biu_intr __P((void*)); 362 /* Bus error (If watch dog timer is enabled)*/ 363 if (mask & MIPS_INT_MASK_1) { 364 tx39biu_intr(0); /* Clear bus error */ 365 } 366 } 367 #endif 368 #if 0 369 /* reset priority mask */ 370 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 371 reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, 0xffff); 372 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 373 #endif 374 return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 375 } 376 377 int 378 tx39_irqhigh(set, bit) 379 int set, bit; 380 { 381 int i, n; 382 383 n = sizeof irqhigh_list / sizeof (struct irqhigh_list); 384 for (i = 0; i < n; i++) { 385 if (irqhigh_list[i].qh_set == set && 386 irqhigh_list[i].qh_bit == bit) 387 return irqhigh_list[i].qh_pri; 388 } 389 390 return 0; 391 } 392 393 void 394 tx39_irqhigh_intr(mask, pc, status, cause) 395 u_int32_t mask; 396 u_int32_t pc; 397 u_int32_t status; 398 u_int32_t cause; 399 { 400 struct txintr_high_entry *he; 401 struct tx39icu_softc *sc; 402 struct clockframe cf; 403 tx_chipset_tag_t tc; 404 int i, pri, ofs, set; 405 txreg_t he_mask; 406 407 tc = tx_conf_get_tag(); 408 sc = tc->tc_intrt; 409 pri = TX39_INTRSTATUS6_INTVECT(sc->sc_regs[0]); 410 411 if (pri == TX39_INTRPRI13_TIMER_PERIODIC) { 412 tx_conf_write(tc, TX39_INTRCLEAR5_REG, 413 TX39_INTRSTATUS5_PERINT); 414 cf.pc = pc; 415 cf.sr = status; 416 hardclock(&cf); 417 intrcnt[HARDCLOCK]++; 418 419 return; 420 } 421 422 /* Handle all pending IRQHIGH interrupts */ 423 for (i = pri; i > 0; i--) { 424 TAILQ_FOREACH(he, &sc->sc_he_head[i], he_link) { 425 set = he->he_set; 426 he_mask = he->he_mask; 427 if (he_mask & (sc->sc_regs[set])) { 428 ofs = TX39_INTRSTATUS_REG(set); 429 /* Clear interrupt */ 430 tx_conf_write(tc, ofs, he_mask); 431 #ifdef TX39_DEBUG 432 tx39intrvec = (set << 16) | 433 (ffs(he_mask) - 1); 434 if (tx39debugflag) { 435 DPRINTF(("IRQHIGH: %d:%d\n", 436 set, ffs(he_mask) - 1)); 437 } 438 #endif /* TX39_DEBUG */ 439 /* Dispatch handler */ 440 (*he->he_fun)(he->he_arg); 441 } 442 } 443 } 444 } 445 446 void 447 tx39_intr_decode(intr, set, bit) 448 int intr; 449 int *set; 450 int *bit; 451 { 452 if (!intr || intr >= (TX39_INTRSET_MAX + 1) * 32 453 #ifdef TX392X 454 || intr == 6 455 #endif /* TX392X */ 456 ) { 457 panic("tx39icu_decode: bogus intrrupt line. %d", intr); 458 } 459 *set = intr / 32; 460 *bit = intr % 32; 461 } 462 463 void 464 tx39_irqhigh_establish(tc, set, bit, pri, ih_fun, ih_arg) 465 tx_chipset_tag_t tc; 466 int set; 467 int bit; 468 int pri; 469 int (*ih_fun) __P((void*)); 470 void *ih_arg; 471 { 472 struct tx39icu_softc *sc; 473 struct txintr_high_entry *he; 474 txreg_t reg; 475 476 sc = tc->tc_intrt; 477 /* 478 * Add new entry to `pri' priority 479 */ 480 if (!(he = malloc(sizeof(struct txintr_high_entry), 481 M_DEVBUF, M_NOWAIT))) { 482 panic ("tx39_irqhigh_establish: no memory."); 483 } 484 memset(he, 0, sizeof(struct txintr_high_entry)); 485 he->he_set = set; 486 he->he_mask= (1 << bit); 487 he->he_fun = ih_fun; 488 he->he_arg = ih_arg; 489 TAILQ_INSERT_TAIL(&sc->sc_he_head[pri], he, he_link); 490 /* 491 * Enable interrupt on this priority. 492 */ 493 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 494 reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, (1 << pri)); 495 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 496 } 497 498 void 499 tx39_irqhigh_disestablish(tc, set, bit, pri) 500 tx_chipset_tag_t tc; 501 int set, bit, pri; 502 { 503 struct tx39icu_softc *sc; 504 struct txintr_high_entry *he; 505 txreg_t reg; 506 507 sc = tc->tc_intrt; 508 TAILQ_FOREACH(he, &sc->sc_he_head[pri], he_link) { 509 if (he->he_set == set && he->he_mask == (1 << bit)) { 510 TAILQ_REMOVE(&sc->sc_he_head[pri], he, he_link); 511 free(he, M_DEVBUF); 512 break; 513 } 514 } 515 516 if (TAILQ_EMPTY(&sc->sc_he_head[pri])) { 517 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 518 reg &= ~(1 << pri); 519 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 520 } 521 } 522 523 524 void* 525 tx_intr_establish(tc, line, mode, level, ih_fun, ih_arg) 526 tx_chipset_tag_t tc; 527 int line; 528 int mode; /* Trigger setting. but TX39 handles edge only. */ 529 int level; /* XXX not yet */ 530 int (*ih_fun) __P((void*)); 531 void *ih_arg; 532 { 533 struct tx39icu_softc *sc; 534 txreg_t reg; 535 int bit, set, highpri, ofs; 536 537 sc = tc->tc_intrt; 538 539 tx39_intr_decode(line, &set, &bit); 540 541 sc->sc_le_fun[set][bit] = ih_fun; 542 sc->sc_le_arg[set][bit] = ih_arg; 543 DPRINTF(("tx_intr_establish: %d:%d", set, bit)); 544 545 if ((highpri = tx39_irqhigh(set, bit))) { 546 tx39_irqhigh_establish(tc, set, bit, highpri, 547 ih_fun, ih_arg); 548 DPRINTF(("(high)\n")); 549 } else { 550 /* Set mask for acknowledge. */ 551 sc->sc_le_mask[set] |= (1 << bit); 552 /* Enable interrupt */ 553 ofs = TX39_INTRENABLE_REG(set); 554 reg = tx_conf_read(tc, ofs); 555 reg |= (1 << bit); 556 tx_conf_write(tc, ofs, reg); 557 DPRINTF(("(low)\n")); 558 } 559 560 return (void*)line; 561 } 562 563 void 564 tx_intr_disestablish(tc, arg) 565 tx_chipset_tag_t tc; 566 void *arg; 567 { 568 struct tx39icu_softc *sc; 569 int set, bit, highpri, ofs; 570 txreg_t reg; 571 572 sc = tc->tc_intrt; 573 574 tx39_intr_decode((int)arg, &set, &bit); 575 DPRINTF(("tx_intr_disestablish: %d:%d", set, bit)); 576 577 if ((highpri = tx39_irqhigh(set, bit))) { 578 tx39_irqhigh_disestablish(tc, set, bit, highpri); 579 DPRINTF(("(high)\n")); 580 } else { 581 sc->sc_le_fun[set][bit] = 0; 582 sc->sc_le_arg[set][bit] = 0; 583 sc->sc_le_mask[set] &= ~(1 << bit); 584 ofs = TX39_INTRENABLE_REG(set); 585 reg = tx_conf_read(tc, ofs); 586 reg &= ~(1 << bit); 587 tx_conf_write(tc, ofs, reg); 588 DPRINTF(("(low)\n")); 589 } 590 } 591 592 u_int32_t 593 tx_intr_status(tc, r) 594 tx_chipset_tag_t tc; 595 int r; 596 { 597 struct tx39icu_softc *sc = tc->tc_intrt; 598 599 if (r < 0 || r >= TX39_INTRSET_MAX + 1) 600 panic("tx_intr_status: invalid index %d", r); 601 602 return (u_int32_t)(sc->sc_regs[r]); 603 } 604 605 #ifdef USE_POLL 606 void* 607 tx39_poll_establish(tc, interval, level, ih_fun, ih_arg) 608 tx_chipset_tag_t tc; 609 int interval; 610 int level; /* XXX not yet */ 611 int (*ih_fun) __P((void*)); 612 void *ih_arg; 613 { 614 struct tx39icu_softc *sc; 615 struct txpoll_entry *p; 616 int s; 617 void *ret; 618 619 s = splhigh(); 620 sc = tc->tc_intrt; 621 622 if (!(p = malloc(sizeof(struct txpoll_entry), 623 M_DEVBUF, M_NOWAIT))) { 624 panic ("tx39_poll_establish: no memory."); 625 } 626 memset(p, 0, sizeof(struct txpoll_entry)); 627 628 p->p_fun = ih_fun; 629 p->p_arg = ih_arg; 630 p->p_cnt = interval; 631 632 if (!sc->sc_polling) { 633 tx39clock_alarm_set(tc, 33); /* 33 msec */ 634 635 if (!(sc->sc_poll_ih = 636 tx_intr_establish( 637 tc, MAKEINTR(5, TX39_INTRSTATUS5_ALARMINT), 638 IST_EDGE, level, tx39_poll_intr, sc))) { 639 printf("tx39_poll_establish: can't hook\n"); 640 641 splx(s); 642 return 0; 643 } 644 } 645 646 sc->sc_polling++; 647 p->p_desc = sc->sc_polling; 648 TAILQ_INSERT_TAIL(&sc->sc_p_head, p, p_link); 649 ret = (void*)p->p_desc; 650 651 splx(s); 652 return ret; 653 } 654 655 void 656 tx39_poll_disestablish(tc, arg) 657 tx_chipset_tag_t tc; 658 void *arg; 659 { 660 struct tx39icu_softc *sc; 661 struct txpoll_entry *p; 662 int s, desc; 663 664 s = splhigh(); 665 sc = tc->tc_intrt; 666 667 desc = (int)arg; 668 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 669 if (p->p_desc == desc) { 670 TAILQ_REMOVE(&sc->sc_p_head, p, p_link); 671 free(p, M_DEVBUF); 672 break; 673 } 674 } 675 676 if (TAILQ_EMPTY(&sc->sc_p_head)) { 677 sc->sc_polling = 0; 678 tx_intr_disestablish(tc, sc->sc_poll_ih); 679 } 680 681 splx(s); 682 return; 683 } 684 685 int 686 tx39_poll_intr(arg) 687 void *arg; 688 { 689 struct tx39icu_softc *sc = arg; 690 struct txpoll_entry *p; 691 692 tx39clock_alarm_refill(sc->sc_tc); 693 694 if (!sc->sc_polling) { 695 return 0; 696 } 697 sc->sc_pollcnt++; 698 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 699 if (sc->sc_pollcnt % p->p_cnt == 0) { 700 if ((*p->p_fun)(p->p_arg) == POLL_END) 701 goto disestablish; 702 } 703 } 704 705 return 0; 706 707 disestablish: 708 TAILQ_REMOVE(&sc->sc_p_head, p, p_link); 709 free(p, M_DEVBUF); 710 if (TAILQ_EMPTY(&sc->sc_p_head)) { 711 sc->sc_polling = 0; 712 tx_intr_disestablish(sc->sc_tc, sc->sc_poll_ih); 713 } 714 715 return 0; 716 } 717 #endif /* USE_POLL */ 718 719 void 720 tx39_intr_dump(sc) 721 struct tx39icu_softc *sc; 722 { 723 tx_chipset_tag_t tc = sc->sc_tc; 724 int i, j, ofs; 725 txreg_t reg; 726 char msg[16]; 727 728 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 729 #ifdef TX392X 730 if (i == 6) 731 continue; 732 #endif /* TX392X */ 733 for (reg = j = 0; j < 32; j++) { 734 if (tx39_irqhigh(i, j)) { 735 reg |= (1 << j); 736 } 737 } 738 sprintf(msg, "%d high", i); 739 __bitdisp(reg, 32, 0, msg, 1); 740 sprintf(msg, "%d status", i); 741 __bitdisp(sc->sc_regs[i], 0, 31, msg, 1); 742 ofs = TX39_INTRENABLE_REG(i); 743 reg = tx_conf_read(tc, ofs); 744 sprintf(msg, "%d enable", i); 745 __bitdisp(reg, 0, 31, msg, 1); 746 } 747 reg = sc->sc_regs[0]; 748 printf("<%s><%s> vector=%2d\t\t[6 status]\n", 749 reg & TX39_INTRSTATUS6_IRQHIGH ? "HI" : "--", 750 reg & TX39_INTRSTATUS6_IRQLOW ? "LO" : "--", 751 TX39_INTRSTATUS6_INTVECT(reg)); 752 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 753 __bitdisp(reg, 0, 18, "6 enable", 1); 754 755 } 756
Indexes created Tue Oct 28 12:10:06 GMT 2025