tx39icu.c revision 1.9
1 /* $NetBSD: tx39icu.c,v 1.9 2000/10/04 13:53:55 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_tx39_debug.h" 40 #include "opt_use_poll.h" 41 #include "opt_tx39icudebug.h" 42 #include "opt_tx39_watchdogtimer.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 #include <sys/queue.h> 49 #define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) 50 51 #include <mips/cpuregs.h> 52 #include <machine/bus.h> 53 54 #include <hpcmips/tx/tx39var.h> 55 #include <hpcmips/tx/tx39icureg.h> 56 #include <hpcmips/tx/tx39clockvar.h> 57 58 #include <machine/clock_machdep.h> 59 #include <machine/cpu.h> 60 #include <dev/dec/clockvar.h> 61 62 #undef TX39ICUDEBUG_PRINT_PENDING_INTERRUPT /* For explorer. good luck! */ 63 64 #ifdef TX39ICUDEBUG 65 #define DPRINTF(arg) printf arg 66 #else 67 #define DPRINTF(arg) 68 #endif 69 u_int32_t tx39intrvec; 70 71 /* IRQHIGH lines list */ 72 static const struct irqhigh_list { 73 int qh_pri; /* IRQHIGH priority */ 74 int qh_set; /* Register set */ 75 int qh_bit; /* bit offset in the register set */ 76 } irqhigh_list[] = { 77 {15, 5, 25}, /* POSPWROKINT */ 78 {15, 5, 24}, /* NEGPWROKINT */ 79 {14, 5, 30}, /* ALARMINT*/ 80 {13, 5, 29}, /* PERINT */ 81 #ifdef TX391X 82 {12, 2, 3}, /* MBUSPOSINT */ 83 {12, 2, 2}, /* MBUSNEGINT */ 84 {11, 2, 31}, /* UARTARXINT */ 85 {10, 2, 21}, /* UARTBRXINT */ 86 {9, 3, 19}, /* MFIOPOSINT19 */ 87 {9, 3, 18}, /* MFIOPOSINT18 */ 88 {9, 3, 17}, /* MFIOPOSINT17 */ 89 {9, 3, 16}, /* MFIOPOSINT16 */ 90 {8, 3, 1}, /* MFIOPOSINT1 */ 91 {8, 3, 0}, /* MFIOPOSINT0 */ 92 {8, 5, 13}, /* IOPOSINT6 */ 93 {8, 5, 12}, /* IOPOSINT5 */ 94 {7, 4, 19}, /* MFIONEGINT19 */ 95 {7, 4, 18}, /* MFIONEGINT18 */ 96 {7, 4, 17}, /* MFIONEGINT17 */ 97 {7, 4, 16}, /* MFIONEGINT16 */ 98 {6, 4, 1}, /* MFIONEGINT1 */ 99 {6, 4, 0}, /* MFIONEGINT0 */ 100 {6, 5, 6}, /* IONEGINT6 */ 101 {6, 5, 5}, /* IONEGINT5 */ 102 {5, 2, 5}, /* MBUSDMAFULLINT */ 103 #endif /* TX391X */ 104 #ifdef TX392X 105 {12, 2, 31}, /* UARTARXINT */ 106 {12, 2, 21}, /* UARTBRXINT */ 107 {11, 3, 19}, /* MFIOPOSINT19 */ 108 {11, 3, 18}, /* MFIOPOSINT18 */ 109 {11, 3, 17}, /* MFIOPOSINT17 */ 110 {11, 3, 16}, /* MFIOPOSINT16 */ 111 {10, 3, 1}, /* MFIOPOSINT1 */ 112 {10, 3, 0}, /* MFIOPOSINT0 */ 113 {10, 5, 13}, /* IOPOSINT6 */ 114 {10, 5, 12}, /* IOPOSINT5 */ 115 {9, 4, 19}, /* MFIONEGINT19 */ 116 {9, 4, 18}, /* MFIONEGINT18 */ 117 {9, 4, 17}, /* MFIONEGINT17 */ 118 {9, 4, 16}, /* MFIONEGINT16 */ 119 {8, 4, 1}, /* MFIONEGINT1 */ 120 {8, 4, 0}, /* MFIONEGINT0 */ 121 {8, 5, 6}, /* IONEGINT6 */ 122 {8, 5, 5}, /* IONEGINT5 */ 123 {5, 7, 19}, /* IRRXCINT */ 124 {5, 7, 17}, /* IRRXEINT */ 125 #endif /* TX392X */ 126 {4, 1, 18}, /* SNDDMACNTINT */ 127 {3, 1, 17}, /* TELDMACNTINT */ 128 {2, 1, 27}, /* CHIDMACNTINT */ 129 {1, 5, 7}, /* IOPOSINT0 */ 130 {1, 5, 0} /* IONEGINT0 */ 131 }; 132 133 struct txintr_high_entry { 134 int he_set; 135 txreg_t he_mask; 136 int (*he_fun) __P((void*)); 137 void *he_arg; 138 TAILQ_ENTRY(txintr_high_entry) he_link; 139 }; 140 141 #ifdef USE_POLL 142 struct txpoll_entry{ 143 int p_cnt; /* dispatch interval */ 144 int p_desc; 145 int (*p_fun) __P((void*)); 146 void *p_arg; 147 TAILQ_ENTRY(txpoll_entry) p_link; 148 }; 149 int tx39_poll_intr __P((void*)); 150 #endif /* USE_POLL */ 151 152 struct tx39icu_softc { 153 struct device sc_dev; 154 tx_chipset_tag_t sc_tc; 155 /* IRQLOW */ 156 txreg_t sc_le_mask[TX39_INTRSET_MAX + 1]; 157 int (*sc_le_fun[TX39_INTRSET_MAX + 1][32]) __P((void*)); 158 void *sc_le_arg[TX39_INTRSET_MAX + 1][32]; 159 /* IRQHIGH */ 160 TAILQ_HEAD(, txintr_high_entry) sc_he_head[TX39_IRQHIGH_MAX]; 161 /* Register */ 162 txreg_t sc_regs[TX39_INTRSET_MAX + 1]; 163 #ifdef USE_POLL 164 unsigned sc_pollcnt; 165 int sc_polling; 166 void *sc_poll_ih; 167 TAILQ_HEAD(, txpoll_entry) sc_p_head; 168 #endif /* USE_POLL */ 169 }; 170 171 int tx39icu_match __P((struct device*, struct cfdata*, void*)); 172 void tx39icu_attach __P((struct device*, struct device*, void*)); 173 int tx39icu_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t)); 174 175 void tx39_intr_dump __P((struct tx39icu_softc*)); 176 void tx39_intr_decode __P((int, int*, int*)); 177 void tx39_irqhigh_disestablish __P((tx_chipset_tag_t, int, int, int)); 178 void tx39_irqhigh_establish __P((tx_chipset_tag_t, int, int, int, 179 int (*) __P((void*)), void*)); 180 void tx39_irqhigh_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t)); 181 int tx39_irqhigh __P((int, int)); 182 183 struct cfattach tx39icu_ca = { 184 sizeof(struct tx39icu_softc), tx39icu_match, tx39icu_attach 185 }; 186 187 int 188 tx39icu_match(parent, cf, aux) 189 struct device *parent; 190 struct cfdata *cf; 191 void *aux; 192 { 193 return 2; /* 1st attach group of txsim */ 194 } 195 196 void 197 tx39icu_attach(parent, self, aux) 198 struct device *parent; 199 struct device *self; 200 void *aux; 201 { 202 struct txsim_attach_args *ta = aux; 203 struct tx39icu_softc *sc = (void*)self; 204 tx_chipset_tag_t tc = ta->ta_tc; 205 txreg_t reg, *regs; 206 int i; 207 208 printf("\n"); 209 sc->sc_tc = ta->ta_tc; 210 211 regs = sc->sc_regs; 212 regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 213 regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 214 regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 215 regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 216 regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 217 regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 218 #ifdef TX392X 219 regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 220 regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 221 #endif 222 #ifdef TX39ICUDEBUG 223 printf("\t[Windows CE setting]\n"); 224 tx39_intr_dump(sc); 225 #endif /* TX39ICUDEBUG */ 226 227 #ifdef WINCE_DEFAULT_SETTING 228 #warning WINCE_DEFAULT_SETTING 229 #else /* WINCE_DEFAULT_SETTING */ 230 /* Disable IRQLOW */ 231 tx_conf_write(tc, TX39_INTRENABLE1_REG, 0); 232 tx_conf_write(tc, TX39_INTRENABLE2_REG, 0); 233 tx_conf_write(tc, TX39_INTRENABLE3_REG, 0); 234 tx_conf_write(tc, TX39_INTRENABLE4_REG, 0); 235 tx_conf_write(tc, TX39_INTRENABLE5_REG, 0); 236 #ifdef TX392X 237 tx_conf_write(tc, TX39_INTRENABLE7_REG, 0); 238 tx_conf_write(tc, TX39_INTRENABLE8_REG, 0); 239 #endif /* TX392X */ 240 241 /* Disable IRQHIGH */ 242 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 243 reg &= ~TX39_INTRENABLE6_PRIORITYMASK_MASK; 244 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 245 #endif /* WINCE_DEFAULT_SETTING */ 246 247 /* Clear all pending interrupts */ 248 tx_conf_write(tc, TX39_INTRCLEAR1_REG, 249 tx_conf_read(tc, TX39_INTRSTATUS1_REG)); 250 tx_conf_write(tc, TX39_INTRCLEAR2_REG, 251 tx_conf_read(tc, TX39_INTRSTATUS2_REG)); 252 tx_conf_write(tc, TX39_INTRCLEAR3_REG, 253 tx_conf_read(tc, TX39_INTRSTATUS3_REG)); 254 tx_conf_write(tc, TX39_INTRCLEAR4_REG, 255 tx_conf_read(tc, TX39_INTRSTATUS4_REG)); 256 tx_conf_write(tc, TX39_INTRCLEAR5_REG, 257 tx_conf_read(tc, TX39_INTRSTATUS5_REG)); 258 #ifdef TX392X 259 tx_conf_write(tc, TX39_INTRCLEAR7_REG, 260 tx_conf_read(tc, TX39_INTRSTATUS7_REG)); 261 tx_conf_write(tc, TX39_INTRCLEAR8_REG, 262 tx_conf_read(tc, TX39_INTRSTATUS8_REG)); 263 #endif /* TX392X */ 264 265 /* Enable global interrupts */ 266 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 267 reg |= TX39_INTRENABLE6_GLOBALEN; 268 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 269 270 /* Initialize IRQHIGH interrupt handler holder*/ 271 for (i = 0; i < TX39_IRQHIGH_MAX; i++) { 272 TAILQ_INIT(&sc->sc_he_head[i]); 273 } 274 #ifdef USE_POLL 275 /* Initialize polling handler holder */ 276 TAILQ_INIT(&sc->sc_p_head); 277 #endif /* USE_POLL */ 278 279 /* Register interrupt module myself */ 280 tx_conf_register_intr(tc, self); 281 } 282 283 int 284 tx39icu_intr(status, cause, pc, ipending) 285 u_int32_t status, cause, pc, ipending; 286 { 287 struct tx39icu_softc *sc; 288 tx_chipset_tag_t tc; 289 txreg_t reg, pend, *regs; 290 int i, j; 291 292 tc = tx_conf_get_tag(); 293 sc = tc->tc_intrt; 294 /* 295 * Read regsiter ASAP 296 */ 297 regs = sc->sc_regs; 298 regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 299 regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 300 regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 301 regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 302 regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 303 regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 304 #ifdef TX392X 305 regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 306 regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 307 #endif 308 309 #ifdef TX39ICUDEBUG 310 if (!(ipending & MIPS_INT_MASK_4) && !(ipending & MIPS_INT_MASK_2)) { 311 bitdisp(ipending); 312 panic("bogus HwInt"); 313 } 314 #ifdef TX39_DEBUG 315 if (tx39debugflag) { 316 tx39_intr_dump(sc); 317 } 318 #endif 319 #endif /* TX39ICUDEBUG */ 320 321 /* IRQHIGH */ 322 if (ipending & MIPS_INT_MASK_4) { 323 tx39_irqhigh_intr(ipending, pc, status, cause); 324 325 return 0; 326 } 327 328 /* IRQLOW */ 329 if (ipending & MIPS_INT_MASK_2) { 330 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 331 int ofs; 332 #ifdef TX392X 333 if (i == 6) 334 continue; 335 #endif /* TX392X */ 336 ofs = TX39_INTRSTATUS_REG(i); 337 pend = sc->sc_regs[i]; 338 reg = sc->sc_le_mask[i] & pend; 339 /* Clear interrupts */ 340 tx_conf_write(tc, ofs, reg); 341 /* Dispatch handler */ 342 for (j = 0 ; j < 32; j++) { 343 if ((reg & (1 << j)) && 344 sc->sc_le_fun[i][j]) { 345 #ifdef TX39_DEBUG 346 tx39intrvec = (i << 16) | j; 347 if (tx39debugflag) { 348 DPRINTF(("IRQLOW %d:%d\n", 349 i, j)); 350 } 351 #endif /* TX39_DEBUG */ 352 (*sc->sc_le_fun[i][j]) 353 (sc->sc_le_arg[i][j]); 354 355 } 356 } 357 #ifdef TX39ICUDEBUG_PRINT_PENDING_INTERRUPT 358 pend &= ~reg; 359 if (pend) { 360 printf("%d pending:", i); 361 __bitdisp(pend, 0, 31, 0, 1); 362 } 363 #endif 364 365 } 366 } 367 #ifdef TX39_WATCHDOGTIMER 368 { 369 extern int tx39biu_intr __P((void*)); 370 /* Bus error (If watch dog timer is enabled)*/ 371 if (ipending & MIPS_INT_MASK_1) { 372 tx39biu_intr(0); /* Clear bus error */ 373 } 374 } 375 #endif 376 #if 0 377 /* reset priority mask */ 378 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 379 reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, 0xffff); 380 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 381 #endif 382 return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 383 } 384 385 int 386 tx39_irqhigh(set, bit) 387 int set, bit; 388 { 389 int i, n; 390 391 n = sizeof irqhigh_list / sizeof (struct irqhigh_list); 392 for (i = 0; i < n; i++) { 393 if (irqhigh_list[i].qh_set == set && 394 irqhigh_list[i].qh_bit == bit) 395 return irqhigh_list[i].qh_pri; 396 } 397 398 return 0; 399 } 400 401 void 402 tx39_irqhigh_intr(ipending, pc, status, cause) 403 u_int32_t ipending; 404 u_int32_t pc; 405 u_int32_t status; 406 u_int32_t cause; 407 { 408 struct txintr_high_entry *he; 409 struct tx39icu_softc *sc; 410 struct clockframe cf; 411 tx_chipset_tag_t tc; 412 int i, pri, ofs, set; 413 txreg_t he_mask; 414 415 tc = tx_conf_get_tag(); 416 sc = tc->tc_intrt; 417 pri = TX39_INTRSTATUS6_INTVECT(sc->sc_regs[0]); 418 419 if (pri == TX39_INTRPRI13_TIMER_PERIODIC) { 420 tx_conf_write(tc, TX39_INTRCLEAR5_REG, 421 TX39_INTRSTATUS5_PERINT); 422 cf.pc = pc; 423 cf.sr = status; 424 hardclock(&cf); 425 intrcnt[HARDCLOCK]++; 426 427 return; 428 } 429 430 /* Handle all pending IRQHIGH interrupts */ 431 for (i = pri; i > 0; i--) { 432 TAILQ_FOREACH(he, &sc->sc_he_head[i], he_link) { 433 set = he->he_set; 434 he_mask = he->he_mask; 435 if (he_mask & (sc->sc_regs[set])) { 436 ofs = TX39_INTRSTATUS_REG(set); 437 /* Clear interrupt */ 438 tx_conf_write(tc, ofs, he_mask); 439 #ifdef TX39_DEBUG 440 tx39intrvec = (set << 16) | 441 (ffs(he_mask) - 1); 442 if (tx39debugflag) { 443 DPRINTF(("IRQHIGH: %d:%d\n", 444 set, ffs(he_mask) - 1)); 445 } 446 #endif /* TX39_DEBUG */ 447 /* Dispatch handler */ 448 (*he->he_fun)(he->he_arg); 449 } 450 } 451 } 452 } 453 454 void 455 tx39_intr_decode(intr, set, bit) 456 int intr; 457 int *set; 458 int *bit; 459 { 460 if (!intr || intr >= (TX39_INTRSET_MAX + 1) * 32 461 #ifdef TX392X 462 || intr == 6 463 #endif /* TX392X */ 464 ) { 465 panic("tx39icu_decode: bogus intrrupt line. %d", intr); 466 } 467 *set = intr / 32; 468 *bit = intr % 32; 469 } 470 471 void 472 tx39_irqhigh_establish(tc, set, bit, pri, ih_fun, ih_arg) 473 tx_chipset_tag_t tc; 474 int set; 475 int bit; 476 int pri; 477 int (*ih_fun) __P((void*)); 478 void *ih_arg; 479 { 480 struct tx39icu_softc *sc; 481 struct txintr_high_entry *he; 482 txreg_t reg; 483 484 sc = tc->tc_intrt; 485 /* 486 * Add new entry to `pri' priority 487 */ 488 if (!(he = malloc(sizeof(struct txintr_high_entry), 489 M_DEVBUF, M_NOWAIT))) { 490 panic ("tx39_irqhigh_establish: no memory."); 491 } 492 memset(he, 0, sizeof(struct txintr_high_entry)); 493 he->he_set = set; 494 he->he_mask= (1 << bit); 495 he->he_fun = ih_fun; 496 he->he_arg = ih_arg; 497 TAILQ_INSERT_TAIL(&sc->sc_he_head[pri], he, he_link); 498 /* 499 * Enable interrupt on this priority. 500 */ 501 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 502 reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, (1 << pri)); 503 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 504 } 505 506 void 507 tx39_irqhigh_disestablish(tc, set, bit, pri) 508 tx_chipset_tag_t tc; 509 int set, bit, pri; 510 { 511 struct tx39icu_softc *sc; 512 struct txintr_high_entry *he; 513 txreg_t reg; 514 515 sc = tc->tc_intrt; 516 TAILQ_FOREACH(he, &sc->sc_he_head[pri], he_link) { 517 if (he->he_set == set && he->he_mask == (1 << bit)) { 518 TAILQ_REMOVE(&sc->sc_he_head[pri], he, he_link); 519 free(he, M_DEVBUF); 520 break; 521 } 522 } 523 524 if (TAILQ_EMPTY(&sc->sc_he_head[pri])) { 525 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 526 reg &= ~(1 << pri); 527 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 528 } 529 } 530 531 532 void* 533 tx_intr_establish(tc, line, mode, level, ih_fun, ih_arg) 534 tx_chipset_tag_t tc; 535 int line; 536 int mode; /* Trigger setting. but TX39 handles edge only. */ 537 int level; /* XXX not yet */ 538 int (*ih_fun) __P((void*)); 539 void *ih_arg; 540 { 541 struct tx39icu_softc *sc; 542 txreg_t reg; 543 int bit, set, highpri, ofs; 544 545 sc = tc->tc_intrt; 546 547 tx39_intr_decode(line, &set, &bit); 548 549 sc->sc_le_fun[set][bit] = ih_fun; 550 sc->sc_le_arg[set][bit] = ih_arg; 551 DPRINTF(("tx_intr_establish: %d:%d", set, bit)); 552 553 if ((highpri = tx39_irqhigh(set, bit))) { 554 tx39_irqhigh_establish(tc, set, bit, highpri, 555 ih_fun, ih_arg); 556 DPRINTF(("(high)\n")); 557 } else { 558 /* Set mask for acknowledge. */ 559 sc->sc_le_mask[set] |= (1 << bit); 560 /* Enable interrupt */ 561 ofs = TX39_INTRENABLE_REG(set); 562 reg = tx_conf_read(tc, ofs); 563 reg |= (1 << bit); 564 tx_conf_write(tc, ofs, reg); 565 DPRINTF(("(low)\n")); 566 } 567 568 return (void*)line; 569 } 570 571 void 572 tx_intr_disestablish(tc, arg) 573 tx_chipset_tag_t tc; 574 void *arg; 575 { 576 struct tx39icu_softc *sc; 577 int set, bit, highpri, ofs; 578 txreg_t reg; 579 580 sc = tc->tc_intrt; 581 582 tx39_intr_decode((int)arg, &set, &bit); 583 DPRINTF(("tx_intr_disestablish: %d:%d", set, bit)); 584 585 if ((highpri = tx39_irqhigh(set, bit))) { 586 tx39_irqhigh_disestablish(tc, set, bit, highpri); 587 DPRINTF(("(high)\n")); 588 } else { 589 sc->sc_le_fun[set][bit] = 0; 590 sc->sc_le_arg[set][bit] = 0; 591 sc->sc_le_mask[set] &= ~(1 << bit); 592 ofs = TX39_INTRENABLE_REG(set); 593 reg = tx_conf_read(tc, ofs); 594 reg &= ~(1 << bit); 595 tx_conf_write(tc, ofs, reg); 596 DPRINTF(("(low)\n")); 597 } 598 } 599 600 u_int32_t 601 tx_intr_status(tc, r) 602 tx_chipset_tag_t tc; 603 int r; 604 { 605 struct tx39icu_softc *sc = tc->tc_intrt; 606 607 if (r < 0 || r >= TX39_INTRSET_MAX + 1) 608 panic("tx_intr_status: invalid index %d", r); 609 610 return (u_int32_t)(sc->sc_regs[r]); 611 } 612 613 #ifdef USE_POLL 614 void* 615 tx39_poll_establish(tc, interval, level, ih_fun, ih_arg) 616 tx_chipset_tag_t tc; 617 int interval; 618 int level; /* XXX not yet */ 619 int (*ih_fun) __P((void*)); 620 void *ih_arg; 621 { 622 struct tx39icu_softc *sc; 623 struct txpoll_entry *p; 624 int s; 625 void *ret; 626 627 s = splhigh(); 628 sc = tc->tc_intrt; 629 630 if (!(p = malloc(sizeof(struct txpoll_entry), 631 M_DEVBUF, M_NOWAIT))) { 632 panic ("tx39_poll_establish: no memory."); 633 } 634 memset(p, 0, sizeof(struct txpoll_entry)); 635 636 p->p_fun = ih_fun; 637 p->p_arg = ih_arg; 638 p->p_cnt = interval; 639 640 if (!sc->sc_polling) { 641 tx39clock_alarm_set(tc, 33); /* 33 msec */ 642 643 if (!(sc->sc_poll_ih = 644 tx_intr_establish( 645 tc, MAKEINTR(5, TX39_INTRSTATUS5_ALARMINT), 646 IST_EDGE, level, tx39_poll_intr, sc))) { 647 printf("tx39_poll_establish: can't hook\n"); 648 649 splx(s); 650 return 0; 651 } 652 } 653 654 sc->sc_polling++; 655 p->p_desc = sc->sc_polling; 656 TAILQ_INSERT_TAIL(&sc->sc_p_head, p, p_link); 657 ret = (void*)p->p_desc; 658 659 splx(s); 660 return ret; 661 } 662 663 void 664 tx39_poll_disestablish(tc, arg) 665 tx_chipset_tag_t tc; 666 void *arg; 667 { 668 struct tx39icu_softc *sc; 669 struct txpoll_entry *p; 670 int s, desc; 671 672 s = splhigh(); 673 sc = tc->tc_intrt; 674 675 desc = (int)arg; 676 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 677 if (p->p_desc == desc) { 678 TAILQ_REMOVE(&sc->sc_p_head, p, p_link); 679 free(p, M_DEVBUF); 680 break; 681 } 682 } 683 684 if (TAILQ_EMPTY(&sc->sc_p_head)) { 685 sc->sc_polling = 0; 686 tx_intr_disestablish(tc, sc->sc_poll_ih); 687 } 688 689 splx(s); 690 return; 691 } 692 693 int 694 tx39_poll_intr(arg) 695 void *arg; 696 { 697 struct tx39icu_softc *sc = arg; 698 struct txpoll_entry *p; 699 700 tx39clock_alarm_refill(sc->sc_tc); 701 702 if (!sc->sc_polling) { 703 return 0; 704 } 705 sc->sc_pollcnt++; 706 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 707 if (sc->sc_pollcnt % p->p_cnt == 0) { 708 if ((*p->p_fun)(p->p_arg) == POLL_END) 709 goto disestablish; 710 } 711 } 712 713 return 0; 714 715 disestablish: 716 TAILQ_REMOVE(&sc->sc_p_head, p, p_link); 717 free(p, M_DEVBUF); 718 if (TAILQ_EMPTY(&sc->sc_p_head)) { 719 sc->sc_polling = 0; 720 tx_intr_disestablish(sc->sc_tc, sc->sc_poll_ih); 721 } 722 723 return 0; 724 } 725 #endif /* USE_POLL */ 726 727 void 728 tx39_intr_dump(sc) 729 struct tx39icu_softc *sc; 730 { 731 tx_chipset_tag_t tc = sc->sc_tc; 732 int i, j, ofs; 733 txreg_t reg; 734 char msg[16]; 735 736 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 737 #ifdef TX392X 738 if (i == 6) 739 continue; 740 #endif /* TX392X */ 741 for (reg = j = 0; j < 32; j++) { 742 if (tx39_irqhigh(i, j)) { 743 reg |= (1 << j); 744 } 745 } 746 sprintf(msg, "%d high", i); 747 __bitdisp(reg, 32, 0, msg, 1); 748 sprintf(msg, "%d status", i); 749 __bitdisp(sc->sc_regs[i], 0, 31, msg, 1); 750 ofs = TX39_INTRENABLE_REG(i); 751 reg = tx_conf_read(tc, ofs); 752 sprintf(msg, "%d enable", i); 753 __bitdisp(reg, 0, 31, msg, 1); 754 } 755 reg = sc->sc_regs[0]; 756 printf("<%s><%s> vector=%2d\t\t[6 status]\n", 757 reg & TX39_INTRSTATUS6_IRQHIGH ? "HI" : "--", 758 reg & TX39_INTRSTATUS6_IRQLOW ? "LO" : "--", 759 TX39_INTRSTATUS6_INTVECT(reg)); 760 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 761 __bitdisp(reg, 0, 18, "6 enable", 1); 762 763 } 764
Indexes created Wed Oct 29 12:09:47 GMT 2025