tx39icureg.h revision 1.1
1 /* $NetBSD: tx39icureg.h,v 1.1 1999/11/20 19:56:34 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 /* 29 * TOSHIBA TMPR3912/3922 interrupt module. 30 */ 31 #ifdef TX391X 32 #define TX39_INTRSET_MAX 5 33 #endif /* TX391X */ 34 #ifdef TX392X 35 #define TX39_INTRSET_MAX 8 36 #endif /* TX391X */ 37 38 #define TX39_IRQHIGH_MAX 16 39 /* R */ 40 #define TX39_INTRSTATUS1_REG 0x100 41 #define TX39_INTRSTATUS2_REG 0x104 42 #define TX39_INTRSTATUS3_REG 0x108 43 #define TX39_INTRSTATUS4_REG 0x10c 44 #define TX39_INTRSTATUS5_REG 0x110 45 #define TX39_INTRSTATUS6_REG 0x114 46 #ifdef TX392X 47 #define TX39_INTRSTATUS7_REG 0x130 48 #define TX39_INTRSTATUS8_REG 0x138 49 #endif /* TX392X */ 50 #ifdef TX391X 51 #define TX39_INTRSTATUS_REG(x) (((x) - 1) * 4 + TX39_INTRSTATUS1_REG) 52 #endif /* TX391X */ 53 #ifdef TX392X 54 #define TX39_INTRSTATUS_REG(x) (((x) <= 6) ? \ 55 (((x) - 1) * 4 + TX39_INTRSTATUS1_REG) : \ 56 (((x) - 7) * 8 + TX39_INTRSTATUS7_REG)) 57 #endif /* TX392X */ 58 59 /* W */ 60 #define TX39_INTRCLEAR1_REG 0x100 61 #define TX39_INTRCLEAR2_REG 0x104 62 #define TX39_INTRCLEAR3_REG 0x108 63 #define TX39_INTRCLEAR4_REG 0x10c 64 #define TX39_INTRCLEAR5_REG 0x110 65 #ifdef TX392X 66 #define TX39_INTRCLEAR7_REG 0x130 67 #define TX39_INTRCLEAR8_REG 0x138 68 #endif /* TX392X */ 69 #ifdef TX391X 70 #define TX39_INTRCLEAR_REG(x) (((x) - 1) * 4 + TX39_INTRCLEAR1_REG) 71 #endif /* TX391X */ 72 #ifdef TX392X 73 #define TX39_INTRCLEAR_REG(x) (((x) <= 6) ? \ 74 (((x) - 1) * 4 + TX39_INTRCLEAR1_REG) : \ 75 (((x) - 7) * 8 + TX39_INTRCLEAR7_REG)) 76 #endif /* TX392X */ 77 78 /* R/W */ 79 #define TX39_INTRENABLE1_REG 0x118 80 #define TX39_INTRENABLE2_REG 0x11c 81 #define TX39_INTRENABLE3_REG 0x120 82 #define TX39_INTRENABLE4_REG 0x124 83 #define TX39_INTRENABLE5_REG 0x128 84 #define TX39_INTRENABLE6_REG 0x12c 85 #ifdef TX392X 86 #define TX39_INTRENABLE7_REG 0x134 87 #define TX39_INTRENABLE8_REG 0x13c 88 #endif /* TX392X */ 89 #ifdef TX391X 90 #define TX39_INTRENABLE_REG(x) (((x) - 1) * 4 + TX39_INTRENABLE1_REG) 91 #endif /* TX391X */ 92 #ifdef TX392X 93 #define TX39_INTRENABLE_REG(x) (((x) <= 6) ? \ 94 (((x) - 1) * 4 + TX39_INTRENABLE1_REG) : \ 95 (((x) - 7) * 8 + TX39_INTRENABLE7_REG)) 96 #endif /* TX392X */ 97 /* 98 * IRQLOW 99 */ 100 /* 101 * Interrupt status/clear 1 register. 102 * -> Enable 1 register 103 */ 104 /* R/W */ 105 #ifdef TX391X 106 #define TX39_INTRSTATUS1_LCDINT 0x80000000 107 #define TX39_INTRSTATUS1_DFINT 0x40000000 108 #endif /* TX391X */ 109 #define TX39_INTRSTATUS1_CHI0_5INT 0x20000000 110 #define TX39_INTRSTATUS1_CHI1_0INT 0x10000000 111 #define TX39_INTRSTATUS1_CHIDMACNTINT 0x08000000 112 #define TX39_INTRSTATUS1_CHININTA 0x04000000 113 #define TX39_INTRSTATUS1_CHININTB 0x02000000 114 #define TX39_INTRSTATUS1_CHIACTINT 0x01000000 115 #define TX39_INTRSTATUS1_CHIERRINT 0x00800000 116 #define TX39_INTRSTATUS1_SND0_5INT 0x00400000 117 #define TX39_INTRSTATUS1_SND1_0INT 0x00200000 118 #define TX39_INTRSTATUS1_TEL0_5INT 0x00100000 119 #define TX39_INTRSTATUS1_TEL1_0INT 0x00080000 120 #define TX39_INTRSTATUS1_SNDDMACNTINT 0x00040000 121 #define TX39_INTRSTATUS1_TELDMACNTINT 0x00020000 122 #define TX39_INTRSTATUS1_LSNDCLIPINT 0x00010000 123 #define TX39_INTRSTATUS1_RSNDCLIPINT 0x00008000 124 #define TX39_INTRSTATUS1_VALSNDPOSINT 0x00004000 125 #define TX39_INTRSTATUS1_VALSNDNEGINT 0x00002000 126 #define TX39_INTRSTATUS1_VALTELPOSINT 0x00001000 127 #define TX39_INTRSTATUS1_VALTELNEGINT 0x00000800 128 #define TX39_INTRSTATUS1_SNDININT 0x00000400 129 #define TX39_INTRSTATUS1_TELININT 0x00000200 130 #define TX39_INTRSTATUS1_SIBSF0INT 0x00000100 131 #define TX39_INTRSTATUS1_SIBSF1INT 0x00000080 132 #define TX39_INTRSTATUS1_SIBIRQPOSINT 0x00000040 133 #define TX39_INTRSTATUS1_SIBIRQNEGINT 0x00000020 134 135 #ifdef TX391X 136 #define TX39_INTRSTATUS1_VIDEO 0xc0000000 137 #endif /* TX391X */ 138 #define TX39_INTRSTATUS1_CHI 0x3f800000 139 #define TX39_INTRSTATUS1_SND 0x007ffe00 140 #define TX39_INTRSTATUS1_SIB 0x000001e0 141 142 /* 143 * Interrupt status/clear 2 register. 144 * -> Enable 2 register 145 */ 146 /* R/W */ 147 #define TX39_INTRSTATUS2_UARTARXINT 0x80000000 148 #define TX39_INTRSTATUS2_UARTARXOVERRUNINT 0x40000000 149 #define TX39_INTRSTATUS2_UARTAFRAMEERRINT 0x20000000 150 #define TX39_INTRSTATUS2_UARTABREAKINT 0x10000000 151 #define TX39_INTRSTATUS2_UARTAPARITYERRINT 0x08000000 152 #define TX39_INTRSTATUS2_UARTATXINT 0x04000000 153 #define TX39_INTRSTATUS2_UARTATXOVERRUNINT 0x02000000 154 #define TX39_INTRSTATUS2_UARTAEMPTYINT 0x01000000 155 #define TX39_INTRSTATUS2_UARTADMAFULLINT 0x00800000 156 #define TX39_INTRSTATUS2_UARTADMAHALFINT 0x00400000 157 #define TX39_INTRSTATUS2_UARTBRXINT 0x00200000 158 #define TX39_INTRSTATUS2_UARTBRXOVERRUNINT 0x00100000 159 #define TX39_INTRSTATUS2_UARTBFRAMEERRINT 0x00080000 160 #define TX39_INTRSTATUS2_UARTBBREAKINT 0x00040000 161 #define TX39_INTRSTATUS2_UARTBPARITYERRINT 0x00020000 162 #define TX39_INTRSTATUS2_UARTBTXINT 0x00010000 163 #define TX39_INTRSTATUS2_UARTBTXOVERRUNINT 0x00008000 164 #define TX39_INTRSTATUS2_UARTBEMPTYINT 0x00004000 165 #define TX39_INTRSTATUS2_UARTBDMAFULLINT 0x00002000 166 #define TX39_INTRSTATUS2_UARTBDMAHALFINT 0x00001000 167 #ifdef TX391X 168 #define TX39_INTRSTATUS2_MBUSTXBUFAVAILINT 0x00000800 169 #define TX39_INTRSTATUS2_MBUSTXERRINT 0x00000400 170 #define TX39_INTRSTATUS2_MBUSEMPTYINT 0x00000200 171 #define TX39_INTRSTATUS2_MBUSRXBUFAVAILINT 0x00000100 172 #define TX39_INTRSTATUS2_MBUSRXERRINT 0x00000080 173 #define TX39_INTRSTATUS2_MBUSDETINT 0x00000040 174 #define TX39_INTRSTATUS2_MBUSDMAFULLINT 0x00000020 175 #define TX39_INTRSTATUS2_MBUSDMAHALFINT 0x00000010 176 #define TX39_INTRSTATUS2_MBUSPOSINT 0x00000008 177 #define TX39_INTRSTATUS2_MBUSNEGINT 0x00000004 178 #endif /* TX391X */ 179 180 #define TX39_INTRSTATUS2_UARTA 0xffc00000 181 #define TX39_INTRSTATUS2_UARTB 0x003ff000 182 #ifdef TX391X 183 #define TX39_INTRSTATUS2_MBUS 0x00000ffc 184 #endif /* TX391X */ 185 /* 186 * Interrupt status/clear 3 register. (Multifunction I/O pin) 187 * -> Enable 3 register 188 */ 189 /* R/W */ 190 #define TX39_INTRSTATUS3_MFIOPOSINT(r) ((r) << 1) 191 192 #define TX39_INTRSTATUS3_CHIFSPOSINT 0x80000000 193 #define TX39_INTRSTATUS3_CHICLKPOSINT 0x40000000 194 #define TX39_INTRSTATUS3_CHIDOUTPOSINT 0x20000000 195 #define TX39_INTRSTATUS3_CHIDINPOSINT 0x10000000 196 #define TX39_INTRSTATUS3_DREQPOSINT 0x08000000 197 #define TX39_INTRSTATUS3_DGRINTPOSINT 0x04000000 198 #define TX39_INTRSTATUS3_BC32KPOSINT 0x02000000 199 #define TX39_INTRSTATUS3_TXDPOSINT 0x01000000 200 #define TX39_INTRSTATUS3_RXDPOSINT 0x00800000 201 #define TX39_INTRSTATUS3_CS1POSINT 0x00400000 202 #define TX39_INTRSTATUS3_CS2POSINT 0x00200000 203 #define TX39_INTRSTATUS3_CS3POSINT 0x00100000 204 #define TX39_INTRSTATUS3_MCS0POSINT 0x00080000 205 #define TX39_INTRSTATUS3_MCS1POSINT 0x00040000 206 #define TX39_INTRSTATUS3_MCS2POSINT 0x00020000 207 #define TX39_INTRSTATUS3_MCS3POSINT 0x00010000 208 #define TX39_INTRSTATUS3_SPICLKPOSINT 0x00008000 209 #define TX39_INTRSTATUS3_SPIOUTPOSINT 0x00004000 210 #define TX39_INTRSTATUS3_SPINPOSINT 0x00002000 211 #define TX39_INTRSTATUS3_SIBMCLKPOSINT 0x00001000 212 #define TX39_INTRSTATUS3_CARDREGPOSINT 0x00000800 213 #define TX39_INTRSTATUS3_CARDIOWRPOSINT 0x00000400 214 #define TX39_INTRSTATUS3_CARDIORDPOSINT 0x00000200 215 #define TX39_INTRSTATUS3_CARD1CSLPOSINT 0x00000100 216 #define TX39_INTRSTATUS3_CARD1CSHPOSINT 0x00000080 217 #define TX39_INTRSTATUS3_CARD2CSLPOSINT 0x00000040 218 #define TX39_INTRSTATUS3_CARD2CSHPOSINT 0x00000020 219 #define TX39_INTRSTATUS3_CARD1WAITPOSINT 0x00000010 220 #define TX39_INTRSTATUS3_CARD2WAITPOSINT 0x00000008 221 #define TX39_INTRSTATUS3_CARDDIRPOSINT 0x00000004 222 223 /* 224 * Interrupt status/clear 4 register. (Multifunction I/O pin) 225 * -> Enable 4 register 226 */ 227 /* R/W */ 228 #define TX39_INTRSTATUS4_MFIONEGINT(r) ((r) << 1) 229 230 #define TX39_INTRSTATUS4_CHIFSNEGINT 0x80000000 231 #define TX39_INTRSTATUS4_CHICLKNEGINT 0x40000000 232 #define TX39_INTRSTATUS4_CHIDOUTNEGINT 0x20000000 233 #define TX39_INTRSTATUS4_CHIDINNEGINT 0x10000000 234 #define TX39_INTRSTATUS4_DREQNEGINT 0x08000000 235 #define TX39_INTRSTATUS4_DGRINTNEGINT 0x04000000 236 #define TX39_INTRSTATUS4_BC32KNEGINT 0x02000000 237 #define TX39_INTRSTATUS4_TXDNEGINT 0x01000000 238 #define TX39_INTRSTATUS4_RXDNEGINT 0x00800000 239 #define TX39_INTRSTATUS4_CS1NEGINT 0x00400000 240 #define TX39_INTRSTATUS4_CS2NEGINT 0x00200000 241 #define TX39_INTRSTATUS4_CS3NEGINT 0x00100000 242 #define TX39_INTRSTATUS4_MCS0NEGINT 0x00080000 243 #define TX39_INTRSTATUS4_MCS1NEGINT 0x00040000 244 #define TX39_INTRSTATUS4_MCS2NEGINT 0x00020000 245 #define TX39_INTRSTATUS4_MCS3NEGINT 0x00010000 246 #define TX39_INTRSTATUS4_SPICLKNEGINT 0x00008000 247 #define TX39_INTRSTATUS4_SPIOUTNEGINT 0x00004000 248 #define TX39_INTRSTATUS4_SPINNEGINT 0x00002000 249 #define TX39_INTRSTATUS4_SIBMCLKNEGINT 0x00001000 250 #define TX39_INTRSTATUS4_CARDREGNEGINT 0x00000800 251 #define TX39_INTRSTATUS4_CARDIOWRNEGINT 0x00000400 252 #define TX39_INTRSTATUS4_CARDIORDNEGINT 0x00000200 253 #define TX39_INTRSTATUS4_CARD1CSLNEGINT 0x00000100 254 #define TX39_INTRSTATUS4_CARD1CSHNEGINT 0x00000080 255 #define TX39_INTRSTATUS4_CARD2CSLNEGINT 0x00000040 256 #define TX39_INTRSTATUS4_CARD2CSHNEGINT 0x00000020 257 #define TX39_INTRSTATUS4_CARD1WAITNEGINT 0x00000010 258 #define TX39_INTRSTATUS4_CARD2WAITNEGINT 0x00000008 259 #define TX39_INTRSTATUS4_CARDDIRNEGINT 0x00000004 260 261 /* 262 * Interrupt status/clear 5 register. 263 * -> Enable 5 register 264 */ 265 /* R/W */ 266 #define TX39_INTRSTATUS5_RTCINT 0x80000000 267 #define TX39_INTRSTATUS5_ALARMINT 0x40000000 268 #define TX39_INTRSTATUS5_PERINT 0x20000000 269 #define TX39_INTRSTATUS5_STPTIMERINT 0x10000000 270 #define TX39_INTRSTATUS5_POSPWRINT 0x08000000 271 #define TX39_INTRSTATUS5_NEGPWRINT 0x04000000 272 #define TX39_INTRSTATUS5_POSPWROKINT 0x02000000 273 #define TX39_INTRSTATUS5_NEGPWROKINT 0x01000000 274 #define TX39_INTRSTATUS5_POSONBUTNINT 0x00800000 275 #define TX39_INTRSTATUS5_NEGONBUTNINT 0x00400000 276 #define TX39_INTRSTATUS5_SPIBUFAVAILINT 0x00200000 277 #define TX39_INTRSTATUS5_SPIERRINT 0x00100000 278 #define TX39_INTRSTATUS5_SPIRCVINT 0x00080000 279 #define TX39_INTRSTATUS5_SPIEMPTYINT 0x00040000 280 #define TX39_INTRSTATUS5_IRCONSMINT 0x00020000 281 #define TX39_INTRSTATUS5_CARSTINT 0x00010000 282 #define TX39_INTRSTATUS5_POSCARINT 0x00008000 283 #define TX39_INTRSTATUS5_NEGCARINT 0x00004000 284 #ifdef TX391X 285 #define TX39_INTRSTATUS5_IOPOSINT6 0x00002000 286 #define TX39_INTRSTATUS5_IOPOSINT5 0x00001000 287 #define TX39_INTRSTATUS5_IOPOSINT4 0x00000800 288 #define TX39_INTRSTATUS5_IOPOSINT3 0x00000400 289 #define TX39_INTRSTATUS5_IOPOSINT2 0x00000200 290 #define TX39_INTRSTATUS5_IOPOSINT1 0x00000100 291 #define TX39_INTRSTATUS5_IOPOSINT0 0x00000080 292 #define TX39_INTRSTATUS5_IONEGINT6 0x00000040 293 #define TX39_INTRSTATUS5_IONEGINT5 0x00000020 294 #define TX39_INTRSTATUS5_IONEGINT4 0x00000010 295 #define TX39_INTRSTATUS5_IONEGINT3 0x00000008 296 #define TX39_INTRSTATUS5_IONEGINT2 0x00000004 297 #define TX39_INTRSTATUS5_IONEGINT1 0x00000002 298 #define TX39_INTRSTATUS5_IONEGINT0 0x00000001 299 #endif /* TX391X */ 300 301 #define TX39_INTRSTATUS5_TIMER 0xe0000000 302 #define TX39_INTRSTATUS5_POWER 0x1fc00000 303 #define TX39_INTRSTATUS5_SPI 0x003c0000 304 #define TX39_INTRSTATUS5_IR 0x0003c000 305 #ifdef TX391X 306 #define TX39_INTRSTATUS5_IO 0x00003fff 307 308 #define TX39_INTRSTATUS5_IOPOSINT_SHIFT 7 309 #define TX39_INTRSTATUS5_IOPOSINT_MASK 0x7f 310 #define TX39_INTRSTATUS5_IOPOSINT(cr) \ 311 (((cr) >> TX39_INTRSTATUS5_IOPOSINT_SHIFT) & \ 312 TX39_INTRSTATUS5_IOPOSINT_MASK) 313 #define TX39_INTRSTATUS5_IOPOSINT_SET(cr, val) \ 314 ((cr) | (((val) << TX39_INTRSTATUS5_IOPOSINT_SHIFT) & \ 315 (TX39_INTRSTATUS5_IOPOSINT_MASK << TX39_INTRSTATUS5_IOPOSINT_SHIFT))) 316 317 #define TX39_INTRSTATUS5_IONEGINT_SHIFT 0 318 #define TX39_INTRSTATUS5_IONEGINT_MASK 0x7f 319 #define TX39_INTRSTATUS5_IONEGINT(cr) \ 320 (((cr) >> TX39_INTRSTATUS5_IONEGINT_SHIFT) & \ 321 TX39_INTRSTATUS5_IONEGINT_MASK) 322 #define TX39_INTRSTATUS5_IONEGINT_SET(cr, val) \ 323 ((cr) | (((val) << TX39_INTRSTATUS5_IONEGINT_SHIFT) & \ 324 (TX39_INTRSTATUS5_IONEGINT_MASK << TX39_INTRSTATUS5_IONEGINT_SHIFT))) 325 #endif /* TX391X */ 326 /* 327 * Interrupt status 6 register. 328 */ 329 /* R */ 330 #define TX39_INTRSTATUS6_IRQHIGH 0x80000000 331 #define TX39_INTRSTATUS6_IRQLOW 0x40000000 332 333 #define TX39_INTRSTATUS6_INTVECT_SHIFT 2 334 #define TX39_INTRSTATUS6_INTVECT_MASK 0xf 335 #define TX39_INTRSTATUS6_INTVECT(cr) \ 336 (((cr) >> TX39_INTRSTATUS6_INTVECT_SHIFT) & \ 337 TX39_INTRSTATUS6_INTVECT_MASK) 338 339 /* 340 * Interrupt enable 6 register. 341 */ 342 /* R/W */ 343 #define TX39_INTRENABLE6_GLOBALEN 0x00040000 344 345 #define TX39_INTRENABLE6_PRIORITYMASK_SHIFT 0 346 #define TX39_INTRENABLE6_PRIORITYMASK_MASK 0xffff 347 #define TX39_INTRENABLE6_PRIORITYMASK(cr) \ 348 (((cr) >> TX39_INTRENABLE6_PRIORITYMASK_SHIFT) & \ 349 TX39_INTRENABLE6_PRIORITYMASK_MASK) 350 #define TX39_INTRENABLE6_PRIORITYMASK_SET(cr, val) \ 351 ((cr) | (((val) << TX39_INTRENABLE6_PRIORITYMASK_SHIFT) & \ 352 (TX39_INTRENABLE6_PRIORITYMASK_MASK << TX39_INTRENABLE6_PRIORITYMASK_SHIFT))) 353 354 #ifdef TX392X 355 /* 356 * Interrupt Status 7 Register 357 */ 358 #define TX3922_INTRSTATUS7_IRTXCINT 0x00100000 359 #define TX3922_INTRSTATUS7_IRRXCINT 0x00080000 360 #define TX3922_INTRSTATUS7_IRTXEINT 0x00040000 361 #define TX3922_INTRSTATUS7_IRRXEINT 0x00020000 362 #define TX3922_INTRSTATUS7_IRSIRPXINT 0x00010000 363 364 /* 365 * Interrupt Status 8 Register 366 */ 367 #define TX39_INTRSTATUS8_IOPOSINT15 0x80000000 368 #define TX39_INTRSTATUS8_IOPOSINT14 0x40000000 369 #define TX39_INTRSTATUS8_IOPOSINT13 0x20000000 370 #define TX39_INTRSTATUS8_IOPOSINT12 0x10000000 371 #define TX39_INTRSTATUS8_IOPOSINT11 0x08000000 372 #define TX39_INTRSTATUS8_IOPOSINT10 0x04000000 373 #define TX39_INTRSTATUS8_IOPOSINT9 0x02000000 374 #define TX39_INTRSTATUS8_IOPOSINT8 0x01000000 375 #define TX39_INTRSTATUS8_IOPOSINT7 0x00800000 376 #define TX39_INTRSTATUS8_IOPOSINT6 0x00400000 377 #define TX39_INTRSTATUS8_IOPOSINT5 0x00200000 378 #define TX39_INTRSTATUS8_IOPOSINT4 0x00100000 379 #define TX39_INTRSTATUS8_IOPOSINT3 0x00080000 380 #define TX39_INTRSTATUS8_IOPOSINT2 0x00040000 381 #define TX39_INTRSTATUS8_IOPOSINT1 0x00020000 382 #define TX39_INTRSTATUS8_IOPOSINT0 0x00010000 383 #define TX39_INTRSTATUS8_IONEGINT15 0x00008000 384 #define TX39_INTRSTATUS8_IONEGINT14 0x00004000 385 #define TX39_INTRSTATUS8_IONEGINT13 0x00002000 386 #define TX39_INTRSTATUS8_IONEGINT12 0x00001000 387 #define TX39_INTRSTATUS8_IONEGINT11 0x00000800 388 #define TX39_INTRSTATUS8_IONEGINT10 0x00000400 389 #define TX39_INTRSTATUS8_IONEGINT9 0x00000200 390 #define TX39_INTRSTATUS8_IONEGINT8 0x00000100 391 #define TX39_INTRSTATUS8_IONEGINT7 0x00000080 392 #define TX39_INTRSTATUS8_IONEGINT6 0x00000040 393 #define TX39_INTRSTATUS8_IONEGINT5 0x00000020 394 #define TX39_INTRSTATUS8_IONEGINT4 0x00000010 395 #define TX39_INTRSTATUS8_IONEGINT3 0x00000008 396 #define TX39_INTRSTATUS8_IONEGINT2 0x00000004 397 #define TX39_INTRSTATUS8_IONEGINT1 0x00000002 398 #define TX39_INTRSTATUS8_IONEGINT0 0x00000001 399 400 #define TX3922_INTRSTATUS8_IOPOSINT_SHIFT 16 401 #define TX3922_INTRSTATUS8_IOPOSINT_MASK 0xffff 402 #define TX3922_INTRSTATUS8_IOPOSINT(cr) \ 403 (((cr) >> TX3922_INTRSTATUS8_IOPOSINT_SHIFT) & \ 404 TX3922_INTRSTATUS8_IOPOSINT_MASK) 405 #define TX3922_INTRSTATUS8_IOPOSINT_SET(cr, val) \ 406 ((cr) | (((val) << TX3922_INTRSTATUS8_IOPOSINT_SHIFT) & \ 407 (TX3922_INTRSTATUS8_IOPOSINT_MASK << TX3922_INTRSTATUS8_IOPOSINT_SHIFT))) 408 409 #define TX3922_INTRSTATUS8_IONEGINT_SHIFT 0 410 #define TX3922_INTRSTATUS8_IONEGINT_MASK 0xffff 411 #define TX3922_INTRSTATUS8_IONEGINT(cr) \ 412 (((cr) >> TX3922_INTRSTATUS8_IONEGINT_SHIFT) & \ 413 TX3922_INTRSTATUS8_IONEGINT_MASK) 414 #define TX3922_INTRSTATUS8_IONEGINT_SET(cr, val) \ 415 ((cr) | (((val) << TX3922_INTRSTATUS8_IONEGINT_SHIFT) & \ 416 (TX3922_INTRSTATUS8_IONEGINT_MASK << TX3922_INTRSTATUS8_IONEGINT_SHIFT))) 417 418 #endif /* TX392X */ 419 420 421 422 /* 423 * IRQHIGH (Priority level interrupt) 424 */ 425 #ifdef TX391X 426 #define TX39_INTRPRI15_PWROK_BIT 0x00008000 427 #define TX39_INTRPRI14_TIMER_ALARM_BIT 0x00004000 428 #define TX39_INTRPRI13_TIMER_PERIODIC_BIT 0x00002000 429 #define TX39_INTRPRI12_MBUS_BIT 0x00001000 430 #define TX39_INTRPRI11_UARTARX_BIT 0x00000800 431 #define TX39_INTRPRI10_UARTBRX_BIT 0x00000400 432 #define TX39_INTRPRI9_MFIO19_18_17_16POS_BIT 0x00000200 433 #define TX39_INTRPRI8_MFIO1_0_IO6_5POS_BIT 0x00000100 434 #define TX39_INTRPRI7_MFIO19_18_17_16NEG_BIT 0x00000080 435 #define TX39_INTRPRI6_MFIO1_0_IO6_5NEG_BIT 0x00000040 436 #define TX39_INTRPRI5_MBUSDMAFULL_BIT 0x00000020 437 #define TX39_INTRPRI4_SNDDMACNT_BIT 0x00000010 438 #define TX39_INTRPRI3_TELDMACNT_BIT 0x00000008 439 #define TX39_INTRPRI2_CHIDMACNT_BIT 0x00000004 440 #define TX39_INTRPRI1_IO0POSNEG_BIT 0x00000002 441 #define TX39_INTRPRI0_BIT 0x00000001 442 443 #define TX39_INTRPRI15_PWROK 15 444 #define TX39_INTRPRI14_TIMER_ALARM 14 445 #define TX39_INTRPRI13_TIMER_PERIODIC 13 446 #define TX39_INTRPRI12_MBUS 12 447 #define TX39_INTRPRI11_UARTARX 11 448 #define TX39_INTRPRI10_UARTBRX 10 449 #define TX39_INTRPRI9_MFIO19_18_17_16POS 9 450 #define TX39_INTRPRI8_MFIO1_0_IO6_5POS 8 451 #define TX39_INTRPRI7_MFIO19_18_17_16NEG 7 452 #define TX39_INTRPRI6_MFIO1_0_IO6_5NEG 6 453 #define TX39_INTRPRI5_MBUSDMAFULL 5 454 #define TX39_INTRPRI4_SNDDMACNT 4 455 #define TX39_INTRPRI3_TELDMACNT 3 456 #define TX39_INTRPRI2_CHIDMACNT 2 457 #define TX39_INTRPRI1_IO0POSNEG 1 458 #define TX39_INTRPRI0 0 459 #endif /* TX391X */ 460 461 #ifdef TX392X 462 #define TX39_INTRPRI15_PWROK_BIT 0x00008000 463 #define TX39_INTRPRI14_TIMER_ALARM_BIT 0x00004000 464 #define TX39_INTRPRI13_TIMER_PERIODIC_BIT 0x00002000 465 #define TX39_INTRPRI12_UARTABRX_BIT 0x00001000 466 #define TX39_INTRPRI11_MFIO19_18_17_16POS_BIT 0x00000800 467 #define TX39_INTRPRI10_MFIO1_0_IO6_5POS_BIT 0x00000400 468 #define TX39_INTRPRI9_MFIO19_18_17_16NEG_BIT 0x00000200 469 #define TX39_INTRPRI8_MFIO1_0_IO6_5NEG_BIT 0x00000100 470 #define TX39_INTRPRI5_MBUSDMAFULL_BIT 0x00000020 471 #define TX39_INTRPRI4_SNDDMACNT_BIT 0x00000010 472 #define TX39_INTRPRI3_TELDMACNT_BIT 0x00000008 473 #define TX39_INTRPRI2_CHIDMACNT_BIT 0x00000004 474 #define TX39_INTRPRI1_IO0POSNEG_BIT 0x00000002 475 #define TX39_INTRPRI0_BIT 0x00000001 476 477 #define TX39_INTRPRI15_PWROK 15 478 #define TX39_INTRPRI14_TIMER_ALARM 14 479 #define TX39_INTRPRI13_TIMER_PERIODIC 13 480 #define TX39_INTRPRI12_UARTABRX 12 481 #define TX39_INTRPRI11_MFIO19_18_17_16POS 11 482 #define TX39_INTRPRI10_MFIO1_0_IO6_5POS 10 483 #define TX39_INTRPRI9_MFIO19_18_17_16NEG 9 484 #define TX39_INTRPRI8_MFIO1_0_IO6_5NEG 8 485 #define TX39_INTRPRI5_IRRXCRXE 5 486 #define TX39_INTRPRI4_SNDDMACNT 4 487 #define TX39_INTRPRI3_TELDMACNT 3 488 #define TX39_INTRPRI2_CHIDMACNT 2 489 #define TX39_INTRPRI1_IO0POSNEG 1 490 #define TX39_INTRPRI0 0 491 #endif /* TX392X */ 492 493 /* 494 * CPU connection 495 */ 496 #define TX39_INTRIRQHIGH_MIPS_HARD_INT 4 497 #define TX39_INTRIRQLOW_MIPS_HARD_INT 2 498
Indexes created Thu Oct 30 22:09:55 GMT 2025