tx39icureg.h revision 1.3.4.1
1 /* $NetBSD: tx39icureg.h,v 1.3.4.1 2001/06/21 19:24:29 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * TOSHIBA TMPR3912/3922 interrupt module. 41 */ 42 #ifdef TX391X 43 #define TX39_INTRSET_MAX 5 44 #endif /* TX391X */ 45 #ifdef TX392X 46 #define TX39_INTRSET_MAX 8 47 #endif /* TX391X */ 48 49 #define TX39_IRQHIGH_MAX 16 50 /* R */ 51 #define TX39_INTRSTATUS1_REG 0x100 52 #define TX39_INTRSTATUS2_REG 0x104 53 #define TX39_INTRSTATUS3_REG 0x108 54 #define TX39_INTRSTATUS4_REG 0x10c 55 #define TX39_INTRSTATUS5_REG 0x110 56 #define TX39_INTRSTATUS6_REG 0x114 57 #ifdef TX392X 58 #define TX39_INTRSTATUS7_REG 0x130 59 #define TX39_INTRSTATUS8_REG 0x138 60 #endif /* TX392X */ 61 #ifdef TX391X 62 #define TX39_INTRSTATUS_REG(x) (((x) - 1) * 4 + TX39_INTRSTATUS1_REG) 63 #endif /* TX391X */ 64 #ifdef TX392X 65 #define TX39_INTRSTATUS_REG(x) (((x) <= 6) ? \ 66 (((x) - 1) * 4 + TX39_INTRSTATUS1_REG) : \ 67 (((x) - 7) * 8 + TX39_INTRSTATUS7_REG)) 68 #endif /* TX392X */ 69 70 /* W */ 71 #define TX39_INTRCLEAR1_REG 0x100 72 #define TX39_INTRCLEAR2_REG 0x104 73 #define TX39_INTRCLEAR3_REG 0x108 74 #define TX39_INTRCLEAR4_REG 0x10c 75 #define TX39_INTRCLEAR5_REG 0x110 76 #ifdef TX392X 77 #define TX39_INTRCLEAR7_REG 0x130 78 #define TX39_INTRCLEAR8_REG 0x138 79 #endif /* TX392X */ 80 #ifdef TX391X 81 #define TX39_INTRCLEAR_REG(x) (((x) - 1) * 4 + TX39_INTRCLEAR1_REG) 82 #endif /* TX391X */ 83 #ifdef TX392X 84 #define TX39_INTRCLEAR_REG(x) (((x) <= 6) ? \ 85 (((x) - 1) * 4 + TX39_INTRCLEAR1_REG) : \ 86 (((x) - 7) * 8 + TX39_INTRCLEAR7_REG)) 87 #endif /* TX392X */ 88 89 /* R/W */ 90 #define TX39_INTRENABLE1_REG 0x118 91 #define TX39_INTRENABLE2_REG 0x11c 92 #define TX39_INTRENABLE3_REG 0x120 93 #define TX39_INTRENABLE4_REG 0x124 94 #define TX39_INTRENABLE5_REG 0x128 95 #define TX39_INTRENABLE6_REG 0x12c 96 #ifdef TX392X 97 #define TX39_INTRENABLE7_REG 0x134 98 #define TX39_INTRENABLE8_REG 0x13c 99 #endif /* TX392X */ 100 #ifdef TX391X 101 #define TX39_INTRENABLE_REG(x) (((x) - 1) * 4 + TX39_INTRENABLE1_REG) 102 #endif /* TX391X */ 103 #ifdef TX392X 104 #define TX39_INTRENABLE_REG(x) (((x) <= 6) ? \ 105 (((x) - 1) * 4 + TX39_INTRENABLE1_REG) : \ 106 (((x) - 7) * 8 + TX39_INTRENABLE7_REG)) 107 #endif /* TX392X */ 108 /* 109 * IRQLOW 110 */ 111 /* 112 * Interrupt status/clear 1 register. 113 * -> Enable 1 register 114 */ 115 /* R/W */ 116 #ifdef TX391X 117 #define TX39_INTRSTATUS1_LCDINT 0x80000000 118 #define TX39_INTRSTATUS1_DFINT 0x40000000 119 #endif /* TX391X */ 120 #define TX39_INTRSTATUS1_CHI0_5INT 0x20000000 121 #define TX39_INTRSTATUS1_CHI1_0INT 0x10000000 122 #define TX39_INTRSTATUS1_CHIDMACNTINT 0x08000000 123 #define TX39_INTRSTATUS1_CHININTA 0x04000000 124 #define TX39_INTRSTATUS1_CHININTB 0x02000000 125 #define TX39_INTRSTATUS1_CHIACTINT 0x01000000 126 #define TX39_INTRSTATUS1_CHIERRINT 0x00800000 127 #define TX39_INTRSTATUS1_SND0_5INT 0x00400000 128 #define TX39_INTRSTATUS1_SND1_0INT 0x00200000 129 #define TX39_INTRSTATUS1_TEL0_5INT 0x00100000 130 #define TX39_INTRSTATUS1_TEL1_0INT 0x00080000 131 #define TX39_INTRSTATUS1_SNDDMACNTINT 0x00040000 132 #define TX39_INTRSTATUS1_TELDMACNTINT 0x00020000 133 #define TX39_INTRSTATUS1_LSNDCLIPINT 0x00010000 134 #define TX39_INTRSTATUS1_RSNDCLIPINT 0x00008000 135 #define TX39_INTRSTATUS1_VALSNDPOSINT 0x00004000 136 #define TX39_INTRSTATUS1_VALSNDNEGINT 0x00002000 137 #define TX39_INTRSTATUS1_VALTELPOSINT 0x00001000 138 #define TX39_INTRSTATUS1_VALTELNEGINT 0x00000800 139 #define TX39_INTRSTATUS1_SNDININT 0x00000400 140 #define TX39_INTRSTATUS1_TELININT 0x00000200 141 #define TX39_INTRSTATUS1_SIBSF0INT 0x00000100 142 #define TX39_INTRSTATUS1_SIBSF1INT 0x00000080 143 #define TX39_INTRSTATUS1_SIBIRQPOSINT 0x00000040 144 #define TX39_INTRSTATUS1_SIBIRQNEGINT 0x00000020 145 146 #ifdef TX391X 147 #define TX39_INTRSTATUS1_VIDEO 0xc0000000 148 #endif /* TX391X */ 149 #define TX39_INTRSTATUS1_CHI 0x3f800000 150 #define TX39_INTRSTATUS1_SND 0x007ffe00 151 #define TX39_INTRSTATUS1_SIB 0x000001e0 152 153 /* 154 * Interrupt status/clear 2 register. 155 * -> Enable 2 register 156 */ 157 /* R/W */ 158 #define TX39_INTRSTATUS2_UARTARXINT 0x80000000 159 #define TX39_INTRSTATUS2_UARTARXOVERRUNINT 0x40000000 160 #define TX39_INTRSTATUS2_UARTAFRAMEERRINT 0x20000000 161 #define TX39_INTRSTATUS2_UARTABREAKINT 0x10000000 162 #define TX39_INTRSTATUS2_UARTAPARITYERRINT 0x08000000 163 #define TX39_INTRSTATUS2_UARTATXINT 0x04000000 164 #define TX39_INTRSTATUS2_UARTATXOVERRUNINT 0x02000000 165 #define TX39_INTRSTATUS2_UARTAEMPTYINT 0x01000000 166 #define TX39_INTRSTATUS2_UARTADMAFULLINT 0x00800000 167 #define TX39_INTRSTATUS2_UARTADMAHALFINT 0x00400000 168 169 #define TX39_INTRSTATUS2_UARTBRXINT 0x00200000 170 #define TX39_INTRSTATUS2_UARTBRXOVERRUNINT 0x00100000 171 #define TX39_INTRSTATUS2_UARTBFRAMEERRINT 0x00080000 172 #define TX39_INTRSTATUS2_UARTBBREAKINT 0x00040000 173 #define TX39_INTRSTATUS2_UARTBPARITYERRINT 0x00020000 174 #define TX39_INTRSTATUS2_UARTBTXINT 0x00010000 175 #define TX39_INTRSTATUS2_UARTBTXOVERRUNINT 0x00008000 176 #define TX39_INTRSTATUS2_UARTBEMPTYINT 0x00004000 177 #define TX39_INTRSTATUS2_UARTBDMAFULLINT 0x00002000 178 #define TX39_INTRSTATUS2_UARTBDMAHALFINT 0x00001000 179 180 #define TX39_INTRSTATUS2_UARTRXINT(x) \ 181 ((x) ? TX39_INTRSTATUS2_UARTBRXINT : \ 182 TX39_INTRSTATUS2_UARTARXINT) 183 #define TX39_INTRSTATUS2_UARTRXOVERRUNINT(x) \ 184 ((x) ? TX39_INTRSTATUS2_UARTBRXOVERRUNINT : \ 185 TX39_INTRSTATUS2_UARTARXOVERRUNINT) 186 #define TX39_INTRSTATUS2_UARTFRAMEERRINT(x) \ 187 ((x) ? TX39_INTRSTATUS2_UARTBFRAMEERRINT : \ 188 TX39_INTRSTATUS2_UARTAFRAMEERRINT) 189 #define TX39_INTRSTATUS2_UARTBREAKINT(x) \ 190 ((x) ? TX39_INTRSTATUS2_UARTBBREAKINT : \ 191 TX39_INTRSTATUS2_UARTABREAKINT) 192 #define TX39_INTRSTATUS2_UARTPARITYERRINT(x) \ 193 ((x) ? TX39_INTRSTATUS2_UARTBPARITYERRINT : \ 194 TX39_INTRSTATUS2_UARTAPARITYERRINT) 195 #define TX39_INTRSTATUS2_UARTTXINT(x) \ 196 ((x) ? TX39_INTRSTATUS2_UARTBTXINT : \ 197 TX39_INTRSTATUS2_UARTATXINT) 198 #define TX39_INTRSTATUS2_UARTTXOVERRUNINT(x) \ 199 ((x) ? TX39_INTRSTATUS2_UARTBTXOVERRUNINT : \ 200 TX39_INTRSTATUS2_UARTATXOVERRUNINT) 201 #define TX39_INTRSTATUS2_UARTEMPTYINT(x) \ 202 ((x) ? TX39_INTRSTATUS2_UARTBEMPTYINT : \ 203 TX39_INTRSTATUS2_UARTEMPTYINT) 204 #define TX39_INTRSTATUS2_UARTDMAFULLINT(x) \ 205 ((x) ? TX39_INTRSTATUS2_UARTBDMAFULLINT : \ 206 TX39_INTRSTATUS2_UARTADMAFULLINT) 207 #define TX39_INTRSTATUS2_UARTDMAHALFINT(x) \ 208 ((x) ? TX39_INTRSTATUS2_UARTBDMAHALFINT : \ 209 TX39_INTRSTATUS2_UARTADMAHALFINT) 210 211 #ifdef TX391X 212 #define TX39_INTRSTATUS2_MBUSTXBUFAVAILINT 0x00000800 213 #define TX39_INTRSTATUS2_MBUSTXERRINT 0x00000400 214 #define TX39_INTRSTATUS2_MBUSEMPTYINT 0x00000200 215 #define TX39_INTRSTATUS2_MBUSRXBUFAVAILINT 0x00000100 216 #define TX39_INTRSTATUS2_MBUSRXERRINT 0x00000080 217 #define TX39_INTRSTATUS2_MBUSDETINT 0x00000040 218 #define TX39_INTRSTATUS2_MBUSDMAFULLINT 0x00000020 219 #define TX39_INTRSTATUS2_MBUSDMAHALFINT 0x00000010 220 #define TX39_INTRSTATUS2_MBUSPOSINT 0x00000008 221 #define TX39_INTRSTATUS2_MBUSNEGINT 0x00000004 222 #endif /* TX391X */ 223 224 #define TX39_INTRSTATUS2_UARTA 0xffc00000 225 #define TX39_INTRSTATUS2_UARTB 0x003ff000 226 #ifdef TX391X 227 #define TX39_INTRSTATUS2_MBUS 0x00000ffc 228 #endif /* TX391X */ 229 /* 230 * Interrupt status/clear 3 register. (Multifunction I/O pin) 231 * -> Enable 3 register 232 */ 233 /* R/W */ 234 #define TX39_INTRSTATUS3_MFIOPOSINT(r) ((r) << 1) 235 236 #define TX39_INTRSTATUS3_CHIFSPOSINT 0x80000000 237 #define TX39_INTRSTATUS3_CHICLKPOSINT 0x40000000 238 #define TX39_INTRSTATUS3_CHIDOUTPOSINT 0x20000000 239 #define TX39_INTRSTATUS3_CHIDINPOSINT 0x10000000 240 #define TX39_INTRSTATUS3_DREQPOSINT 0x08000000 241 #define TX39_INTRSTATUS3_DGRINTPOSINT 0x04000000 242 #define TX39_INTRSTATUS3_BC32KPOSINT 0x02000000 243 #define TX39_INTRSTATUS3_TXDPOSINT 0x01000000 244 #define TX39_INTRSTATUS3_RXDPOSINT 0x00800000 245 #define TX39_INTRSTATUS3_CS1POSINT 0x00400000 246 #define TX39_INTRSTATUS3_CS2POSINT 0x00200000 247 #define TX39_INTRSTATUS3_CS3POSINT 0x00100000 248 #define TX39_INTRSTATUS3_MCS0POSINT 0x00080000 249 #define TX39_INTRSTATUS3_MCS1POSINT 0x00040000 250 #define TX39_INTRSTATUS3_MCS2POSINT 0x00020000 251 #define TX39_INTRSTATUS3_MCS3POSINT 0x00010000 252 #define TX39_INTRSTATUS3_SPICLKPOSINT 0x00008000 253 #define TX39_INTRSTATUS3_SPIOUTPOSINT 0x00004000 254 #define TX39_INTRSTATUS3_SPINPOSINT 0x00002000 255 #define TX39_INTRSTATUS3_SIBMCLKPOSINT 0x00001000 256 #define TX39_INTRSTATUS3_CARDREGPOSINT 0x00000800 257 #define TX39_INTRSTATUS3_CARDIOWRPOSINT 0x00000400 258 #define TX39_INTRSTATUS3_CARDIORDPOSINT 0x00000200 259 #define TX39_INTRSTATUS3_CARD1CSLPOSINT 0x00000100 260 #define TX39_INTRSTATUS3_CARD1CSHPOSINT 0x00000080 261 #define TX39_INTRSTATUS3_CARD2CSLPOSINT 0x00000040 262 #define TX39_INTRSTATUS3_CARD2CSHPOSINT 0x00000020 263 #define TX39_INTRSTATUS3_CARD1WAITPOSINT 0x00000010 264 #define TX39_INTRSTATUS3_CARD2WAITPOSINT 0x00000008 265 #define TX39_INTRSTATUS3_CARDDIRPOSINT 0x00000004 266 267 /* 268 * Interrupt status/clear 4 register. (Multifunction I/O pin) 269 * -> Enable 4 register 270 */ 271 /* R/W */ 272 #define TX39_INTRSTATUS4_MFIONEGINT(r) ((r) << 1) 273 274 #define TX39_INTRSTATUS4_CHIFSNEGINT 0x80000000 275 #define TX39_INTRSTATUS4_CHICLKNEGINT 0x40000000 276 #define TX39_INTRSTATUS4_CHIDOUTNEGINT 0x20000000 277 #define TX39_INTRSTATUS4_CHIDINNEGINT 0x10000000 278 #define TX39_INTRSTATUS4_DREQNEGINT 0x08000000 279 #define TX39_INTRSTATUS4_DGRINTNEGINT 0x04000000 280 #define TX39_INTRSTATUS4_BC32KNEGINT 0x02000000 281 #define TX39_INTRSTATUS4_TXDNEGINT 0x01000000 282 #define TX39_INTRSTATUS4_RXDNEGINT 0x00800000 283 #define TX39_INTRSTATUS4_CS1NEGINT 0x00400000 284 #define TX39_INTRSTATUS4_CS2NEGINT 0x00200000 285 #define TX39_INTRSTATUS4_CS3NEGINT 0x00100000 286 #define TX39_INTRSTATUS4_MCS0NEGINT 0x00080000 287 #define TX39_INTRSTATUS4_MCS1NEGINT 0x00040000 288 #define TX39_INTRSTATUS4_MCS2NEGINT 0x00020000 289 #define TX39_INTRSTATUS4_MCS3NEGINT 0x00010000 290 #define TX39_INTRSTATUS4_SPICLKNEGINT 0x00008000 291 #define TX39_INTRSTATUS4_SPIOUTNEGINT 0x00004000 292 #define TX39_INTRSTATUS4_SPINNEGINT 0x00002000 293 #define TX39_INTRSTATUS4_SIBMCLKNEGINT 0x00001000 294 #define TX39_INTRSTATUS4_CARDREGNEGINT 0x00000800 295 #define TX39_INTRSTATUS4_CARDIOWRNEGINT 0x00000400 296 #define TX39_INTRSTATUS4_CARDIORDNEGINT 0x00000200 297 #define TX39_INTRSTATUS4_CARD1CSLNEGINT 0x00000100 298 #define TX39_INTRSTATUS4_CARD1CSHNEGINT 0x00000080 299 #define TX39_INTRSTATUS4_CARD2CSLNEGINT 0x00000040 300 #define TX39_INTRSTATUS4_CARD2CSHNEGINT 0x00000020 301 #define TX39_INTRSTATUS4_CARD1WAITNEGINT 0x00000010 302 #define TX39_INTRSTATUS4_CARD2WAITNEGINT 0x00000008 303 #define TX39_INTRSTATUS4_CARDDIRNEGINT 0x00000004 304 305 /* 306 * Interrupt status/clear 5 register. 307 * -> Enable 5 register 308 */ 309 /* R/W */ 310 #define TX39_INTRSTATUS5_RTCINT 0x80000000 311 #define TX39_INTRSTATUS5_ALARMINT 0x40000000 312 #define TX39_INTRSTATUS5_PERINT 0x20000000 313 #define TX39_INTRSTATUS5_STPTIMERINT 0x10000000 314 #define TX39_INTRSTATUS5_POSPWRINT 0x08000000 315 #define TX39_INTRSTATUS5_NEGPWRINT 0x04000000 316 #define TX39_INTRSTATUS5_POSPWROKINT 0x02000000 317 #define TX39_INTRSTATUS5_NEGPWROKINT 0x01000000 318 #define TX39_INTRSTATUS5_POSONBUTNINT 0x00800000 319 #define TX39_INTRSTATUS5_NEGONBUTNINT 0x00400000 320 #define TX39_INTRSTATUS5_SPIBUFAVAILINT 0x00200000 321 #define TX39_INTRSTATUS5_SPIERRINT 0x00100000 322 #define TX39_INTRSTATUS5_SPIRCVINT 0x00080000 323 #define TX39_INTRSTATUS5_SPIEMPTYINT 0x00040000 324 #define TX39_INTRSTATUS5_IRCONSMINT 0x00020000 325 #define TX39_INTRSTATUS5_CARSTINT 0x00010000 326 #define TX39_INTRSTATUS5_POSCARINT 0x00008000 327 #define TX39_INTRSTATUS5_NEGCARINT 0x00004000 328 #ifdef TX391X 329 #define TX39_INTRSTATUS5_IOPOSINT6 0x00002000 330 #define TX39_INTRSTATUS5_IOPOSINT5 0x00001000 331 #define TX39_INTRSTATUS5_IOPOSINT4 0x00000800 332 #define TX39_INTRSTATUS5_IOPOSINT3 0x00000400 333 #define TX39_INTRSTATUS5_IOPOSINT2 0x00000200 334 #define TX39_INTRSTATUS5_IOPOSINT1 0x00000100 335 #define TX39_INTRSTATUS5_IOPOSINT0 0x00000080 336 #define TX39_INTRSTATUS5_IONEGINT6 0x00000040 337 #define TX39_INTRSTATUS5_IONEGINT5 0x00000020 338 #define TX39_INTRSTATUS5_IONEGINT4 0x00000010 339 #define TX39_INTRSTATUS5_IONEGINT3 0x00000008 340 #define TX39_INTRSTATUS5_IONEGINT2 0x00000004 341 #define TX39_INTRSTATUS5_IONEGINT1 0x00000002 342 #define TX39_INTRSTATUS5_IONEGINT0 0x00000001 343 #endif /* TX391X */ 344 345 #define TX39_INTRSTATUS5_TIMER 0xe0000000 346 #define TX39_INTRSTATUS5_POWER 0x1fc00000 347 #define TX39_INTRSTATUS5_SPI 0x003c0000 348 #define TX39_INTRSTATUS5_IR 0x0003c000 349 #ifdef TX391X 350 #define TX39_INTRSTATUS5_IO 0x00003fff 351 352 #define TX39_INTRSTATUS5_IOPOSINT_SHIFT 7 353 #define TX39_INTRSTATUS5_IOPOSINT_MASK 0x7f 354 #define TX39_INTRSTATUS5_IOPOSINT(cr) \ 355 (((cr) >> TX39_INTRSTATUS5_IOPOSINT_SHIFT) & \ 356 TX39_INTRSTATUS5_IOPOSINT_MASK) 357 #define TX39_INTRSTATUS5_IOPOSINT_SET(cr, val) \ 358 ((cr) | (((val) << TX39_INTRSTATUS5_IOPOSINT_SHIFT) & \ 359 (TX39_INTRSTATUS5_IOPOSINT_MASK << TX39_INTRSTATUS5_IOPOSINT_SHIFT))) 360 361 #define TX39_INTRSTATUS5_IONEGINT_SHIFT 0 362 #define TX39_INTRSTATUS5_IONEGINT_MASK 0x7f 363 #define TX39_INTRSTATUS5_IONEGINT(cr) \ 364 (((cr) >> TX39_INTRSTATUS5_IONEGINT_SHIFT) & \ 365 TX39_INTRSTATUS5_IONEGINT_MASK) 366 #define TX39_INTRSTATUS5_IONEGINT_SET(cr, val) \ 367 ((cr) | (((val) << TX39_INTRSTATUS5_IONEGINT_SHIFT) & \ 368 (TX39_INTRSTATUS5_IONEGINT_MASK << TX39_INTRSTATUS5_IONEGINT_SHIFT))) 369 #endif /* TX391X */ 370 /* 371 * Interrupt status 6 register. 372 */ 373 /* R */ 374 #define TX39_INTRSTATUS6_IRQHIGH 0x80000000 375 #define TX39_INTRSTATUS6_IRQLOW 0x40000000 376 377 #define TX39_INTRSTATUS6_INTVECT_SHIFT 2 378 #define TX39_INTRSTATUS6_INTVECT_MASK 0xf 379 #define TX39_INTRSTATUS6_INTVECT(cr) \ 380 (((cr) >> TX39_INTRSTATUS6_INTVECT_SHIFT) & \ 381 TX39_INTRSTATUS6_INTVECT_MASK) 382 383 /* 384 * Interrupt enable 6 register. 385 */ 386 /* R/W */ 387 #define TX39_INTRENABLE6_GLOBALEN 0x00040000 388 389 #define TX39_INTRENABLE6_PRIORITYMASK_SHIFT 0 390 #define TX39_INTRENABLE6_PRIORITYMASK_MASK 0xffff 391 #define TX39_INTRENABLE6_PRIORITYMASK(cr) \ 392 (((cr) >> TX39_INTRENABLE6_PRIORITYMASK_SHIFT) & \ 393 TX39_INTRENABLE6_PRIORITYMASK_MASK) 394 #define TX39_INTRENABLE6_PRIORITYMASK_SET(cr, val) \ 395 ((cr) | (((val) << TX39_INTRENABLE6_PRIORITYMASK_SHIFT) & \ 396 (TX39_INTRENABLE6_PRIORITYMASK_MASK << \ 397 TX39_INTRENABLE6_PRIORITYMASK_SHIFT))) 398 399 #ifdef TX392X 400 /* 401 * Interrupt Status 7 Register 402 */ 403 #define TX3922_INTRSTATUS7_IRTXCINT 0x00100000 404 #define TX3922_INTRSTATUS7_IRRXCINT 0x00080000 405 #define TX3922_INTRSTATUS7_IRTXEINT 0x00040000 406 #define TX3922_INTRSTATUS7_IRRXEINT 0x00020000 407 #define TX3922_INTRSTATUS7_IRSIRPXINT 0x00010000 408 409 /* 410 * Interrupt Status 8 Register 411 */ 412 #define TX39_INTRSTATUS8_IOPOSINT15 0x80000000 413 #define TX39_INTRSTATUS8_IOPOSINT14 0x40000000 414 #define TX39_INTRSTATUS8_IOPOSINT13 0x20000000 415 #define TX39_INTRSTATUS8_IOPOSINT12 0x10000000 416 #define TX39_INTRSTATUS8_IOPOSINT11 0x08000000 417 #define TX39_INTRSTATUS8_IOPOSINT10 0x04000000 418 #define TX39_INTRSTATUS8_IOPOSINT9 0x02000000 419 #define TX39_INTRSTATUS8_IOPOSINT8 0x01000000 420 #define TX39_INTRSTATUS8_IOPOSINT7 0x00800000 421 #define TX39_INTRSTATUS8_IOPOSINT6 0x00400000 422 #define TX39_INTRSTATUS8_IOPOSINT5 0x00200000 423 #define TX39_INTRSTATUS8_IOPOSINT4 0x00100000 424 #define TX39_INTRSTATUS8_IOPOSINT3 0x00080000 425 #define TX39_INTRSTATUS8_IOPOSINT2 0x00040000 426 #define TX39_INTRSTATUS8_IOPOSINT1 0x00020000 427 #define TX39_INTRSTATUS8_IOPOSINT0 0x00010000 428 #define TX39_INTRSTATUS8_IONEGINT15 0x00008000 429 #define TX39_INTRSTATUS8_IONEGINT14 0x00004000 430 #define TX39_INTRSTATUS8_IONEGINT13 0x00002000 431 #define TX39_INTRSTATUS8_IONEGINT12 0x00001000 432 #define TX39_INTRSTATUS8_IONEGINT11 0x00000800 433 #define TX39_INTRSTATUS8_IONEGINT10 0x00000400 434 #define TX39_INTRSTATUS8_IONEGINT9 0x00000200 435 #define TX39_INTRSTATUS8_IONEGINT8 0x00000100 436 #define TX39_INTRSTATUS8_IONEGINT7 0x00000080 437 #define TX39_INTRSTATUS8_IONEGINT6 0x00000040 438 #define TX39_INTRSTATUS8_IONEGINT5 0x00000020 439 #define TX39_INTRSTATUS8_IONEGINT4 0x00000010 440 #define TX39_INTRSTATUS8_IONEGINT3 0x00000008 441 #define TX39_INTRSTATUS8_IONEGINT2 0x00000004 442 #define TX39_INTRSTATUS8_IONEGINT1 0x00000002 443 #define TX39_INTRSTATUS8_IONEGINT0 0x00000001 444 445 #define TX3922_INTRSTATUS8_IOPOSINT_SHIFT 16 446 #define TX3922_INTRSTATUS8_IOPOSINT_MASK 0xffff 447 #define TX3922_INTRSTATUS8_IOPOSINT(cr) \ 448 (((cr) >> TX3922_INTRSTATUS8_IOPOSINT_SHIFT) & \ 449 TX3922_INTRSTATUS8_IOPOSINT_MASK) 450 #define TX3922_INTRSTATUS8_IOPOSINT_SET(cr, val) \ 451 ((cr) | (((val) << TX3922_INTRSTATUS8_IOPOSINT_SHIFT) & \ 452 (TX3922_INTRSTATUS8_IOPOSINT_MASK << \ 453 TX3922_INTRSTATUS8_IOPOSINT_SHIFT))) 454 455 #define TX3922_INTRSTATUS8_IONEGINT_SHIFT 0 456 #define TX3922_INTRSTATUS8_IONEGINT_MASK 0xffff 457 #define TX3922_INTRSTATUS8_IONEGINT(cr) \ 458 (((cr) >> TX3922_INTRSTATUS8_IONEGINT_SHIFT) & \ 459 TX3922_INTRSTATUS8_IONEGINT_MASK) 460 #define TX3922_INTRSTATUS8_IONEGINT_SET(cr, val) \ 461 ((cr) | (((val) << TX3922_INTRSTATUS8_IONEGINT_SHIFT) & \ 462 (TX3922_INTRSTATUS8_IONEGINT_MASK << \ 463 TX3922_INTRSTATUS8_IONEGINT_SHIFT))) 464 465 #endif /* TX392X */ 466 467 /* 468 * IRQHIGH (Priority level interrupt) 469 */ 470 #ifdef TX391X 471 #define TX39_INTRPRI15_PWROK_BIT 0x00008000 472 #define TX39_INTRPRI14_TIMER_ALARM_BIT 0x00004000 473 #define TX39_INTRPRI13_TIMER_PERIODIC_BIT 0x00002000 474 #define TX39_INTRPRI12_MBUS_BIT 0x00001000 475 #define TX39_INTRPRI11_UARTARX_BIT 0x00000800 476 #define TX39_INTRPRI10_UARTBRX_BIT 0x00000400 477 #define TX39_INTRPRI9_MFIO19_18_17_16POS_BIT 0x00000200 478 #define TX39_INTRPRI8_MFIO1_0_IO6_5POS_BIT 0x00000100 479 #define TX39_INTRPRI7_MFIO19_18_17_16NEG_BIT 0x00000080 480 #define TX39_INTRPRI6_MFIO1_0_IO6_5NEG_BIT 0x00000040 481 #define TX39_INTRPRI5_MBUSDMAFULL_BIT 0x00000020 482 #define TX39_INTRPRI4_SNDDMACNT_BIT 0x00000010 483 #define TX39_INTRPRI3_TELDMACNT_BIT 0x00000008 484 #define TX39_INTRPRI2_CHIDMACNT_BIT 0x00000004 485 #define TX39_INTRPRI1_IO0POSNEG_BIT 0x00000002 486 #define TX39_INTRPRI0_BIT 0x00000001 487 488 #define TX39_INTRPRI15_PWROK 15 489 #define TX39_INTRPRI14_TIMER_ALARM 14 490 #define TX39_INTRPRI13_TIMER_PERIODIC 13 491 #define TX39_INTRPRI12_MBUS 12 492 #define TX39_INTRPRI11_UARTARX 11 493 #define TX39_INTRPRI10_UARTBRX 10 494 #define TX39_INTRPRI9_MFIO19_18_17_16POS 9 495 #define TX39_INTRPRI8_MFIO1_0_IO6_5POS 8 496 #define TX39_INTRPRI7_MFIO19_18_17_16NEG 7 497 #define TX39_INTRPRI6_MFIO1_0_IO6_5NEG 6 498 #define TX39_INTRPRI5_MBUSDMAFULL 5 499 #define TX39_INTRPRI4_SNDDMACNT 4 500 #define TX39_INTRPRI3_TELDMACNT 3 501 #define TX39_INTRPRI2_CHIDMACNT 2 502 #define TX39_INTRPRI1_IO0POSNEG 1 503 #define TX39_INTRPRI0 0 504 #endif /* TX391X */ 505 506 #ifdef TX392X 507 #define TX39_INTRPRI15_PWROK_BIT 0x00008000 508 #define TX39_INTRPRI14_TIMER_ALARM_BIT 0x00004000 509 #define TX39_INTRPRI13_TIMER_PERIODIC_BIT 0x00002000 510 #define TX39_INTRPRI12_UARTABRX_BIT 0x00001000 511 #define TX39_INTRPRI11_MFIO19_18_17_16POS_BIT 0x00000800 512 #define TX39_INTRPRI10_MFIO1_0_IO6_5POS_BIT 0x00000400 513 #define TX39_INTRPRI9_MFIO19_18_17_16NEG_BIT 0x00000200 514 #define TX39_INTRPRI8_MFIO1_0_IO6_5NEG_BIT 0x00000100 515 #define TX39_INTRPRI5_MBUSDMAFULL_BIT 0x00000020 516 #define TX39_INTRPRI4_SNDDMACNT_BIT 0x00000010 517 #define TX39_INTRPRI3_TELDMACNT_BIT 0x00000008 518 #define TX39_INTRPRI2_CHIDMACNT_BIT 0x00000004 519 #define TX39_INTRPRI1_IO0POSNEG_BIT 0x00000002 520 #define TX39_INTRPRI0_BIT 0x00000001 521 522 #define TX39_INTRPRI15_PWROK 15 523 #define TX39_INTRPRI14_TIMER_ALARM 14 524 #define TX39_INTRPRI13_TIMER_PERIODIC 13 525 #define TX39_INTRPRI12_UARTABRX 12 526 #define TX39_INTRPRI11_MFIO19_18_17_16POS 11 527 #define TX39_INTRPRI10_MFIO1_0_IO6_5POS 10 528 #define TX39_INTRPRI9_MFIO19_18_17_16NEG 9 529 #define TX39_INTRPRI8_MFIO1_0_IO6_5NEG 8 530 #define TX39_INTRPRI5_IRRXCRXE 5 531 #define TX39_INTRPRI4_SNDDMACNT 4 532 #define TX39_INTRPRI3_TELDMACNT 3 533 #define TX39_INTRPRI2_CHIDMACNT 2 534 #define TX39_INTRPRI1_IO0POSNEG 1 535 #define TX39_INTRPRI0 0 536 #endif /* TX392X */ 537 538 /* 539 * CPU connection 540 */ 541 #define TX39_INTRIRQHIGH_MIPS_HARD_INT 4 542 #define TX39_INTRIRQLOW_MIPS_HARD_INT 2 543
Indexes created Wed Nov 05 22:09:55 GMT 2025