1 1.24 andvar /* $NetBSD: tx39io.c,v 1.24 2023/09/10 14:11:33 andvar Exp $ */ 2 1.1 uch 3 1.6 uch /*- 4 1.11 uch * Copyright (c) 1999-2001 The NetBSD Foundation, Inc. 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.6 uch * This code is derived from software contributed to The NetBSD Foundation 8 1.6 uch * by UCHIYAMA Yasushi. 9 1.6 uch * 10 1.1 uch * Redistribution and use in source and binary forms, with or without 11 1.1 uch * modification, are permitted provided that the following conditions 12 1.1 uch * are met: 13 1.1 uch * 1. Redistributions of source code must retain the above copyright 14 1.1 uch * notice, this list of conditions and the following disclaimer. 15 1.6 uch * 2. Redistributions in binary form must reproduce the above copyright 16 1.6 uch * notice, this list of conditions and the following disclaimer in the 17 1.6 uch * documentation and/or other materials provided with the distribution. 18 1.1 uch * 19 1.6 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.6 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.6 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.6 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.6 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.6 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.6 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.6 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.6 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.6 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.6 uch * POSSIBILITY OF SUCH DAMAGE. 30 1.1 uch */ 31 1.16 lukem 32 1.16 lukem #include <sys/cdefs.h> 33 1.24 andvar __KERNEL_RCSID(0, "$NetBSD: tx39io.c,v 1.24 2023/09/10 14:11:33 andvar Exp $"); 34 1.1 uch 35 1.1 uch #include <sys/param.h> 36 1.1 uch #include <sys/systm.h> 37 1.1 uch #include <sys/device.h> 38 1.1 uch 39 1.1 uch #include <machine/bus.h> 40 1.1 uch 41 1.1 uch #include <hpcmips/tx/tx39var.h> 42 1.7 uch #include <hpcmips/tx/tx39icureg.h> 43 1.17 uch #define __TX39IO_PRIVATE 44 1.5 uch #include <hpcmips/tx/tx39iovar.h> 45 1.1 uch #include <hpcmips/tx/tx39ioreg.h> 46 1.1 uch 47 1.11 uch #ifdef TX39IO_DEBUG 48 1.17 uch #define DPRINTF_ENABLE 49 1.17 uch #define DPRINTF_DEBUG tx39io_debug 50 1.7 uch #endif 51 1.11 uch #include <machine/debug.h> 52 1.5 uch 53 1.20 christos #define ISBITSET(x, s) ((x) & (1 << (s))) 54 1.1 uch 55 1.23 chs int tx39io_match(device_t, cfdata_t, void *); 56 1.23 chs void tx39io_attach(device_t, device_t, void *); 57 1.1 uch 58 1.23 chs CFATTACH_DECL_NEW(tx39io, sizeof(struct tx39io_softc), 59 1.15 thorpej tx39io_match, tx39io_attach, NULL, NULL); 60 1.1 uch 61 1.7 uch /* IO/MFIO common */ 62 1.8 uch static void port_intr_disestablish(hpcio_chip_t, hpcio_intr_handle_t); 63 1.8 uch static void port_intr_clear(hpcio_chip_t, hpcio_intr_handle_t); 64 1.7 uch /* MFIO */ 65 1.8 uch static void *mfio_intr_establish(hpcio_chip_t, int, int, int (*)(void *), 66 1.8 uch void *); 67 1.8 uch static int mfio_in(hpcio_chip_t, int); 68 1.8 uch static void mfio_out(hpcio_chip_t, int, int); 69 1.8 uch static int mfio_intr_map(int *, int, int); 70 1.8 uch static void mfio_dump(hpcio_chip_t); 71 1.8 uch static void mfio_update(hpcio_chip_t); 72 1.7 uch /* IO */ 73 1.8 uch static void *io_intr_establish(hpcio_chip_t, int, int, int (*)(void *), 74 1.8 uch void *); 75 1.1 uch #ifdef TX391X 76 1.8 uch static int tx391x_io_in(hpcio_chip_t, int); 77 1.8 uch static void tx391x_io_out(hpcio_chip_t, int, int); 78 1.8 uch static void tx391x_io_update(hpcio_chip_t); 79 1.8 uch static int tx391x_io_intr_map(int *, int, int); 80 1.7 uch #endif 81 1.1 uch #ifdef TX392X 82 1.8 uch static int tx392x_io_in(hpcio_chip_t, int); 83 1.8 uch static void tx392x_io_out(hpcio_chip_t, int, int); 84 1.8 uch static void tx392x_io_update(hpcio_chip_t); 85 1.8 uch static int tx392x_io_intr_map(int *, int, int); 86 1.8 uch #endif 87 1.8 uch #if defined TX391X && defined TX392X 88 1.17 uch #define tx39_io_intr_map(t, s, p, m) \ 89 1.22 dholland (IS_TX391X(t) \ 90 1.8 uch ? tx391x_io_intr_map(s, p, m) : tx392x_io_intr_map(s, p, m)) 91 1.8 uch #elif defined TX391X 92 1.17 uch #define tx39io_intr_map(t, s, p, m) tx391x_io_intr_map(s, p, m) 93 1.8 uch #elif defined TX392X 94 1.17 uch #define tx39io_intr_map(t, s, p, m) tx392x_io_intr_map(s, p, m) 95 1.7 uch #endif 96 1.8 uch static void io_dump(hpcio_chip_t); 97 1.7 uch 98 1.7 uch static void __print_port_status(struct tx39io_port_status *, int); 99 1.1 uch 100 1.1 uch int 101 1.23 chs tx39io_match(device_t parent, cfdata_t cf, void *aux) 102 1.1 uch { 103 1.9 uch return (ATTACH_FIRST); /* 1st attach group of txsim */ 104 1.5 uch } 105 1.5 uch 106 1.5 uch void 107 1.23 chs tx39io_attach(device_t parent, device_t self, void *aux) 108 1.5 uch { 109 1.5 uch struct txsim_attach_args *ta = aux; 110 1.23 chs struct tx39io_softc *sc = device_private(self); 111 1.7 uch tx_chipset_tag_t tc; 112 1.8 uch struct hpcio_chip *io_hc = &sc->sc_io_ops; 113 1.8 uch struct hpcio_chip *mfio_hc = &sc->sc_mfio_ops; 114 1.17 uch 115 1.23 chs sc->sc_dev = self; 116 1.7 uch tc = sc->sc_tc = ta->ta_tc; 117 1.1 uch 118 1.5 uch printf("\n"); 119 1.7 uch sc->sc_stat_io_mask = ~(1 << 5); /* exclude Plum2 INT */ 120 1.7 uch sc->sc_stat_mfio_mask = ~(0x3|(0x3 << 23)); 121 1.7 uch 122 1.7 uch /* IO */ 123 1.8 uch io_hc->hc_chipid = IO; 124 1.8 uch io_hc->hc_name = "IO"; 125 1.8 uch io_hc->hc_sc = sc; 126 1.8 uch io_hc->hc_intr_establish = io_intr_establish; 127 1.8 uch io_hc->hc_intr_disestablish = port_intr_disestablish; 128 1.8 uch io_hc->hc_intr_clear = port_intr_clear; 129 1.8 uch io_hc->hc_dump = io_dump; 130 1.7 uch if (IS_TX391X(tc)) { 131 1.7 uch #ifdef TX391X 132 1.8 uch io_hc->hc_portread = tx391x_io_in; 133 1.8 uch io_hc->hc_portwrite = tx391x_io_out; 134 1.8 uch io_hc->hc_update = tx391x_io_update; 135 1.7 uch #endif 136 1.7 uch } else if (IS_TX392X(tc)) { 137 1.7 uch #ifdef TX392X 138 1.8 uch io_hc->hc_portread = tx392x_io_in; 139 1.8 uch io_hc->hc_portwrite = tx392x_io_out; 140 1.8 uch io_hc->hc_update = tx392x_io_update; 141 1.7 uch #endif 142 1.7 uch } 143 1.8 uch tx_conf_register_ioman(tc, io_hc); 144 1.7 uch 145 1.7 uch /* MFIO */ 146 1.8 uch mfio_hc->hc_chipid = MFIO; 147 1.8 uch mfio_hc->hc_name = "MFIO"; 148 1.8 uch mfio_hc->hc_sc = sc; 149 1.8 uch mfio_hc->hc_portread = mfio_in; 150 1.8 uch mfio_hc->hc_portwrite = mfio_out; 151 1.8 uch mfio_hc->hc_intr_establish = mfio_intr_establish; 152 1.8 uch mfio_hc->hc_intr_disestablish = port_intr_disestablish; 153 1.8 uch mfio_hc->hc_update = mfio_update; 154 1.8 uch mfio_hc->hc_dump = mfio_dump; 155 1.7 uch 156 1.8 uch tx_conf_register_ioman(tc, mfio_hc); 157 1.7 uch 158 1.8 uch hpcio_update(io_hc); 159 1.8 uch hpcio_update(mfio_hc); 160 1.7 uch 161 1.11 uch #ifdef TX39IO_DEBUG 162 1.8 uch hpcio_dump(io_hc); 163 1.8 uch hpcio_dump(mfio_hc); 164 1.7 uch printf("IO i0x%08x o0x%08x MFIO i0x%08x o0x%08x\n", 165 1.7 uch sc->sc_stat_io.in, sc->sc_stat_io.out, 166 1.7 uch sc->sc_stat_mfio.in, sc->sc_stat_mfio.out); 167 1.11 uch #endif /* TX39IO_DEBUG */ 168 1.1 uch } 169 1.1 uch 170 1.17 uch /* 171 1.17 uch * TX391X, TX392X common 172 1.7 uch */ 173 1.7 uch static void * 174 1.8 uch io_intr_establish(hpcio_chip_t arg, int port, int mode, int (*func)(void *), 175 1.8 uch void *func_arg) 176 1.5 uch { 177 1.8 uch struct tx39io_softc *sc = arg->hc_sc; 178 1.8 uch int src; 179 1.8 uch 180 1.8 uch if (tx39io_intr_map(sc->sc_tc, &src, port, mode) != 0) 181 1.8 uch return (0); 182 1.8 uch 183 1.8 uch return (tx_intr_establish(sc->sc_tc, src, IST_EDGE, IPL_CLOCK, func, 184 1.8 uch func_arg)); 185 1.8 uch } 186 1.8 uch 187 1.8 uch static void * 188 1.8 uch mfio_intr_establish(hpcio_chip_t arg, int port, int mode, int (*func)(void *), 189 1.8 uch void *func_arg) 190 1.8 uch { 191 1.8 uch struct tx39io_softc *sc = arg->hc_sc; 192 1.8 uch int src; 193 1.8 uch 194 1.8 uch if (mfio_intr_map(&src, port, mode) != 0) 195 1.8 uch return (0); 196 1.17 uch 197 1.8 uch return (tx_intr_establish(sc->sc_tc, src, IST_EDGE, IPL_CLOCK, func, 198 1.8 uch func_arg)); 199 1.5 uch } 200 1.5 uch 201 1.7 uch static void 202 1.8 uch port_intr_disestablish(hpcio_chip_t arg, void *ih) 203 1.5 uch { 204 1.8 uch struct tx39io_softc *sc = arg->hc_sc; 205 1.7 uch tx_intr_disestablish(sc->sc_tc, ih); 206 1.7 uch } 207 1.5 uch 208 1.7 uch static void 209 1.8 uch port_intr_clear(hpcio_chip_t arg, void *ih) 210 1.7 uch { 211 1.8 uch } 212 1.8 uch 213 1.8 uch static void 214 1.8 uch mfio_out(hpcio_chip_t arg, int port, int onoff) 215 1.8 uch { 216 1.8 uch struct tx39io_softc *sc = arg->hc_sc; 217 1.7 uch tx_chipset_tag_t tc; 218 1.7 uch txreg_t reg, pos; 219 1.5 uch 220 1.11 uch DPRINTF("port #%d\n", port); 221 1.7 uch tc = sc->sc_tc; 222 1.7 uch /* MFIO */ 223 1.7 uch pos = 1 << port; 224 1.7 uch #ifdef DIAGNOSTIC 225 1.7 uch if (!(sc->sc_stat_mfio.dir & pos)) { 226 1.13 provos panic("%s: MFIO%d is not output port.", 227 1.23 chs device_xname(sc->sc_dev), port); 228 1.5 uch } 229 1.7 uch #endif 230 1.7 uch reg = tx_conf_read(tc, TX39_IOMFIODATAOUT_REG); 231 1.7 uch if (onoff) 232 1.7 uch reg |= pos; 233 1.7 uch else 234 1.7 uch reg &= ~pos; 235 1.7 uch tx_conf_write(tc, TX39_IOMFIODATAOUT_REG, reg); 236 1.7 uch } 237 1.7 uch 238 1.7 uch static int 239 1.8 uch mfio_in(hpcio_chip_t arg, int port) 240 1.7 uch { 241 1.24 andvar struct tx39io_softc *sc __attribute__((__unused__)) = arg->hc_sc; 242 1.8 uch 243 1.11 uch DPRINTF("port #%d\n", port); 244 1.9 uch return (tx_conf_read(sc->sc_tc, TX39_IOMFIODATAIN_REG) & (1 << port)); 245 1.5 uch } 246 1.5 uch 247 1.8 uch static int 248 1.8 uch mfio_intr_map(int *src, int port, int mode) 249 1.1 uch { 250 1.8 uch 251 1.8 uch if (mode & HPCIO_INTR_POSEDGE) { 252 1.8 uch *src = MAKEINTR(3, (1 << port)); 253 1.8 uch return (0); 254 1.8 uch } else if (mode & HPCIO_INTR_NEGEDGE) { 255 1.8 uch *src = MAKEINTR(4, (1 << port)); 256 1.8 uch return (0); 257 1.8 uch } 258 1.17 uch 259 1.11 uch DPRINTF("invalid interrupt mode.\n"); 260 1.8 uch 261 1.8 uch return (1); 262 1.7 uch } 263 1.5 uch 264 1.7 uch static void 265 1.8 uch mfio_update(hpcio_chip_t arg) 266 1.7 uch { 267 1.8 uch struct tx39io_softc *sc = arg->hc_sc; 268 1.7 uch tx_chipset_tag_t tc = sc->sc_tc; 269 1.7 uch struct tx39io_port_status *stat_mfio = &sc->sc_stat_mfio; 270 1.7 uch 271 1.7 uch sc->sc_ostat_mfio = *stat_mfio; /* save old status */ 272 1.7 uch stat_mfio->dir = tx_conf_read(tc, TX39_IOMFIODATADIR_REG); 273 1.7 uch stat_mfio->in = tx_conf_read(tc, TX39_IOMFIODATAIN_REG); 274 1.7 uch stat_mfio->out = tx_conf_read(tc, TX39_IOMFIODATAOUT_REG); 275 1.7 uch stat_mfio->power = tx_conf_read(tc, TX39_IOMFIOPOWERDWN_REG); 276 1.7 uch stat_mfio->u.select = tx_conf_read(tc, TX39_IOMFIODATASEL_REG); 277 1.1 uch } 278 1.1 uch 279 1.7 uch #ifdef TX391X 280 1.17 uch /* 281 1.17 uch * TMPR3912 specific 282 1.7 uch */ 283 1.1 uch int 284 1.8 uch tx391x_io_in(hpcio_chip_t arg, int port) 285 1.1 uch { 286 1.8 uch struct tx39io_softc *sc __attribute__((__unused__)) = arg->hc_sc; 287 1.7 uch txreg_t reg = tx_conf_read(sc->sc_tc, TX39_IOCTRL_REG); 288 1.5 uch 289 1.11 uch DPRINTF("port #%d\n", port); 290 1.9 uch return (TX391X_IOCTRL_IODIN(reg) & (1 << port)); 291 1.1 uch } 292 1.1 uch 293 1.1 uch void 294 1.8 uch tx391x_io_out(hpcio_chip_t arg, int port, int onoff) 295 1.1 uch { 296 1.8 uch struct tx39io_softc *sc = arg->hc_sc; 297 1.7 uch tx_chipset_tag_t tc; 298 1.7 uch txreg_t reg, pos, iostat; 299 1.7 uch 300 1.7 uch KASSERT(sc); 301 1.11 uch DPRINTF("port #%d\n", port); 302 1.7 uch 303 1.7 uch tc = sc->sc_tc; 304 1.7 uch 305 1.17 uch /* IO [0:6] */ 306 1.7 uch pos = 1 << port; 307 1.7 uch #ifdef DIAGNOSTIC 308 1.7 uch if (!(sc->sc_stat_io.dir & pos)) 309 1.23 chs panic("%s: IO%d is not output port.", device_xname(sc->sc_dev), 310 1.10 uch port); 311 1.1 uch #endif 312 1.7 uch reg = tx_conf_read(tc, TX39_IOCTRL_REG); 313 1.7 uch iostat = TX391X_IOCTRL_IODOUT(reg); 314 1.7 uch if (onoff) 315 1.7 uch iostat |= pos; 316 1.7 uch else 317 1.7 uch iostat &= ~pos; 318 1.7 uch TX391X_IOCTRL_IODOUT_CLR(reg); 319 1.7 uch reg = TX391X_IOCTRL_IODOUT_SET(reg, iostat); 320 1.7 uch tx_conf_write(tc, TX39_IOCTRL_REG, reg); 321 1.7 uch } 322 1.1 uch 323 1.7 uch void 324 1.8 uch tx391x_io_update(hpcio_chip_t arg) 325 1.7 uch { 326 1.8 uch struct tx39io_softc *sc = arg->hc_sc; 327 1.7 uch struct tx39io_port_status *stat_io = &sc->sc_stat_io; 328 1.7 uch tx_chipset_tag_t tc = sc->sc_tc; 329 1.7 uch txreg_t reg; 330 1.7 uch 331 1.7 uch /* IO [0:6] */ 332 1.7 uch sc->sc_ostat_io = *stat_io; /* save old status */ 333 1.1 uch reg = tx_conf_read(tc, TX39_IOCTRL_REG); 334 1.7 uch stat_io->dir = TX391X_IOCTRL_IODIREC(reg); 335 1.7 uch stat_io->in = TX391X_IOCTRL_IODIN(reg); 336 1.17 uch stat_io->out = TX391X_IOCTRL_IODOUT(reg); 337 1.7 uch stat_io->u.debounce = TX391X_IOCTRL_IODEBSEL(reg); 338 1.7 uch reg = tx_conf_read(tc, TX39_IOIOPOWERDWN_REG); 339 1.7 uch stat_io->power = TX391X_IOIOPOWERDWN_IOPD(reg); 340 1.7 uch } 341 1.8 uch 342 1.8 uch int 343 1.8 uch tx391x_io_intr_map(int *src, int port, int mode) 344 1.8 uch { 345 1.8 uch 346 1.8 uch if (mode & HPCIO_INTR_POSEDGE) { 347 1.8 uch *src = MAKEINTR(5, (1 << (port + 7))); 348 1.8 uch return (0); 349 1.8 uch } else if (mode & HPCIO_INTR_NEGEDGE) { 350 1.8 uch *src = MAKEINTR(5, (1 << port)); 351 1.8 uch return (0); 352 1.8 uch } 353 1.17 uch 354 1.11 uch DPRINTF("invalid interrupt mode.\n"); 355 1.8 uch 356 1.8 uch return (1); 357 1.8 uch } 358 1.1 uch #endif /* TX391X */ 359 1.7 uch 360 1.1 uch #ifdef TX392X 361 1.17 uch /* 362 1.7 uch * TMPR3922 specific 363 1.7 uch */ 364 1.7 uch int 365 1.8 uch tx392x_io_in(hpcio_chip_t arg, int port) 366 1.7 uch { 367 1.8 uch struct tx39io_softc *sc __attribute__((__unused__)) = arg->hc_sc; 368 1.7 uch txreg_t reg = tx_conf_read(sc->sc_tc, TX392X_IODATAINOUT_REG); 369 1.8 uch 370 1.11 uch DPRINTF("port #%d\n", port); 371 1.17 uch 372 1.9 uch return (TX392X_IODATAINOUT_DIN(reg) & (1 << port)); 373 1.7 uch } 374 1.7 uch 375 1.7 uch void 376 1.8 uch tx392x_io_out(hpcio_chip_t arg, int port, int onoff) 377 1.7 uch { 378 1.8 uch struct tx39io_softc *sc = arg->hc_sc; 379 1.7 uch #ifdef DIAGNOSTIC 380 1.23 chs const char *devname = device_xname(sc->sc_dev); 381 1.7 uch #endif 382 1.7 uch tx_chipset_tag_t tc = sc->sc_tc; 383 1.7 uch txreg_t reg, pos, iostat; 384 1.7 uch 385 1.11 uch DPRINTF("port #%d\n", port); 386 1.7 uch /* IO [0:15] */ 387 1.7 uch pos = 1 << port; 388 1.7 uch #ifdef DIAGNOSTIC 389 1.12 uch if (!(sc->sc_stat_io.dir & pos)) 390 1.13 provos panic("%s: IO%d is not output port.", devname, port); 391 1.7 uch #endif 392 1.7 uch reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG); 393 1.7 uch iostat = TX392X_IODATAINOUT_DOUT(reg); 394 1.7 uch if (onoff) 395 1.7 uch iostat |= pos; 396 1.7 uch else 397 1.7 uch iostat &= ~pos; 398 1.7 uch TX392X_IODATAINOUT_DOUT_CLR(reg); 399 1.7 uch reg = TX392X_IODATAINOUT_DOUT_SET(reg, iostat); 400 1.7 uch tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg); 401 1.7 uch } 402 1.7 uch 403 1.8 uch int 404 1.8 uch tx392x_io_intr_map(int *src, int port, int mode) 405 1.7 uch { 406 1.8 uch 407 1.8 uch if (mode & HPCIO_INTR_POSEDGE) { 408 1.8 uch *src = MAKEINTR(8, (1 << (port + 16))); 409 1.8 uch return (0); 410 1.8 uch } else if (mode & HPCIO_INTR_NEGEDGE) { 411 1.8 uch *src = MAKEINTR(8, (1 << port)); 412 1.8 uch return (0); 413 1.8 uch } 414 1.17 uch 415 1.11 uch DPRINTF("invalid interrupt mode.\n"); 416 1.8 uch 417 1.8 uch return (1); 418 1.7 uch } 419 1.7 uch 420 1.7 uch void 421 1.8 uch tx392x_io_update(hpcio_chip_t arg) 422 1.7 uch { 423 1.8 uch struct tx39io_softc *sc = arg->hc_sc; 424 1.7 uch struct tx39io_port_status *stat_io = &sc->sc_stat_io; 425 1.7 uch tx_chipset_tag_t tc = sc->sc_tc; 426 1.7 uch txreg_t reg; 427 1.7 uch 428 1.7 uch sc->sc_ostat_io = *stat_io; /* save old status */ 429 1.7 uch /* IO [0:15] */ 430 1.7 uch reg = tx_conf_read(tc, TX39_IOCTRL_REG); 431 1.7 uch stat_io->dir = TX392X_IOCTRL_IODIREC(reg); 432 1.7 uch stat_io->u.debounce = TX392X_IOCTRL_IODEBSEL(reg); 433 1.7 uch reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG); 434 1.7 uch stat_io->in = TX392X_IODATAINOUT_DIN(reg); 435 1.17 uch stat_io->out = TX392X_IODATAINOUT_DOUT(reg); 436 1.7 uch reg = tx_conf_read(tc, TX39_IOIOPOWERDWN_REG); 437 1.7 uch stat_io->power = TX392X_IOIOPOWERDWN_IOPD(reg); 438 1.7 uch } 439 1.7 uch 440 1.1 uch #endif /* TX392X */ 441 1.7 uch 442 1.7 uch static const char *line = "--------------------------------------------------" 443 1.7 uch "------------\n"; 444 1.7 uch static void 445 1.8 uch mfio_dump(hpcio_chip_t arg) 446 1.7 uch { 447 1.8 uch struct tx39io_softc *sc = arg->hc_sc; 448 1.7 uch const struct tx39io_mfio_map *map = tx39io_get_mfio_map(tc); 449 1.7 uch struct tx39io_port_status *stat; 450 1.7 uch int i; 451 1.17 uch 452 1.7 uch printf("%s", line); 453 1.7 uch stat = &sc->sc_stat_mfio; 454 1.1 uch for (i = TX39_IO_MFIO_MAX - 1; i >= 0 ; i--) { 455 1.7 uch /* MFIO port has power down state */ 456 1.1 uch printf("MFIO %2d: - ", i); 457 1.7 uch __print_port_status(stat, i); 458 1.20 christos printf(ISBITSET(stat->u.select, i) ? " MFIO(%s)\n" : " %s\n", 459 1.7 uch map[i].std_pin_name); 460 1.1 uch } 461 1.7 uch printf("%s", line); 462 1.1 uch } 463 1.1 uch 464 1.7 uch static void 465 1.8 uch io_dump(hpcio_chip_t arg) 466 1.1 uch { 467 1.8 uch struct tx39io_softc *sc = arg->hc_sc; 468 1.7 uch struct tx39io_port_status *stat; 469 1.17 uch int i; 470 1.7 uch 471 1.7 uch printf("%s Debounce Direction DataOut DataIn PowerDown Select" 472 1.7 uch "\n%s", line, line); 473 1.7 uch stat = &sc->sc_stat_io; 474 1.7 uch for (i = tx39io_get_io_max(tc) - 1; i >= 0 ; i--) { 475 1.7 uch /* IO port has debouncer */ 476 1.7 uch printf("IO %2d: %s ", i, 477 1.20 christos ISBITSET(stat->u.debounce, i) ? "On " : "Off"); 478 1.7 uch __print_port_status(stat, i); 479 1.7 uch printf(" -\n"); 480 1.1 uch } 481 1.7 uch } 482 1.6 uch 483 1.7 uch static void 484 1.7 uch __print_port_status(struct tx39io_port_status *stat, int i) 485 1.7 uch { 486 1.7 uch printf("%s %d %d %s", 487 1.20 christos ISBITSET(stat->dir, i) ? "Out" : "In ", 488 1.20 christos ISBITSET(stat->out, i) ? 1 : 0, 489 1.20 christos ISBITSET(stat->in, i) ? 1 : 0, 490 1.20 christos ISBITSET(stat->power, i) ? "Down ": "Active"); 491 1.7 uch } 492