1 1.11 andvar /* $NetBSD: tx39ir.c,v 1.11 2023/09/10 20:28:25 andvar Exp $ */ 2 1.1 uch 3 1.2 uch /*- 4 1.2 uch * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.2 uch * This code is derived from software contributed to The NetBSD Foundation 8 1.2 uch * by UCHIYAMA Yasushi. 9 1.2 uch * 10 1.1 uch * Redistribution and use in source and binary forms, with or without 11 1.1 uch * modification, are permitted provided that the following conditions 12 1.1 uch * are met: 13 1.1 uch * 1. Redistributions of source code must retain the above copyright 14 1.1 uch * notice, this list of conditions and the following disclaimer. 15 1.2 uch * 2. Redistributions in binary form must reproduce the above copyright 16 1.2 uch * notice, this list of conditions and the following disclaimer in the 17 1.2 uch * documentation and/or other materials provided with the distribution. 18 1.1 uch * 19 1.2 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2 uch * POSSIBILITY OF SUCH DAMAGE. 30 1.1 uch */ 31 1.1 uch 32 1.1 uch /* 33 1.1 uch * TX39 IR module (connected to UARTB) 34 1.1 uch */ 35 1.7 lukem 36 1.7 lukem #include <sys/cdefs.h> 37 1.11 andvar __KERNEL_RCSID(0, "$NetBSD: tx39ir.c,v 1.11 2023/09/10 20:28:25 andvar Exp $"); 38 1.1 uch 39 1.1 uch #include <sys/param.h> 40 1.1 uch #include <sys/systm.h> 41 1.1 uch #include <sys/device.h> 42 1.1 uch 43 1.1 uch #include <machine/bus.h> 44 1.1 uch #include <machine/intr.h> 45 1.1 uch 46 1.1 uch #include <hpcmips/tx/tx39var.h> 47 1.1 uch #include <hpcmips/tx/tx39icureg.h> 48 1.1 uch #include <hpcmips/tx/tx39irvar.h> 49 1.1 uch #include <hpcmips/tx/tx39irreg.h> 50 1.1 uch 51 1.1 uch #include <hpcmips/tx/tx39clockreg.h> /* XXX */ 52 1.1 uch 53 1.1 uch #ifdef TX39IRDEBUG 54 1.11 andvar #define DPRINTF_ENABLE 55 1.11 andvar #define DPRINTF_DEBUG tx39ir_debug 56 1.1 uch #endif 57 1.11 andvar #include <machine/debug.h> 58 1.1 uch 59 1.10 chs int tx39ir_match(device_t, cfdata_t, void *); 60 1.10 chs void tx39ir_attach(device_t, device_t, void *); 61 1.1 uch 62 1.1 uch struct tx39ir_softc { 63 1.10 chs device_t sc_parent; 64 1.1 uch tx_chipset_tag_t sc_tc; 65 1.1 uch }; 66 1.1 uch 67 1.3 shin #ifdef TX39IRDEBUG 68 1.2 uch static void tx39ir_dump(struct tx39ir_softc *); 69 1.3 shin #endif 70 1.3 shin #if not_required_yet 71 1.2 uch static int tx39ir_intr(void *); 72 1.3 shin #endif 73 1.1 uch 74 1.10 chs CFATTACH_DECL_NEW(tx39ir, sizeof(struct tx39ir_softc), 75 1.6 thorpej tx39ir_match, tx39ir_attach, NULL, NULL); 76 1.1 uch 77 1.1 uch int 78 1.10 chs tx39ir_match(device_t parent, cfdata_t cf, void *aux) 79 1.1 uch { 80 1.2 uch return (ATTACH_NORMAL); 81 1.1 uch } 82 1.1 uch 83 1.1 uch void 84 1.10 chs tx39ir_attach(device_t parent, device_t self, void *aux) 85 1.1 uch { 86 1.1 uch struct txcom_attach_args *tca = aux; 87 1.10 chs struct tx39ir_softc *sc = device_private(self); 88 1.1 uch tx_chipset_tag_t tc; 89 1.1 uch txreg_t reg; 90 1.1 uch 91 1.1 uch sc->sc_tc = tc = tca->tca_tc; 92 1.1 uch sc->sc_parent = tca->tca_parent; 93 1.1 uch 94 1.1 uch printf("\n"); 95 1.1 uch 96 1.1 uch /* setup IR module */ 97 1.1 uch reg = tx_conf_read(tc, TX39_IRCTRL1_REG); 98 1.1 uch reg |= TX39_IRCTRL1_RXPWR; 99 1.1 uch tx_conf_write(tc, TX39_IRCTRL1_REG, reg); 100 1.1 uch 101 1.1 uch /* power up IR module */ 102 1.1 uch reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG); 103 1.1 uch reg |= TX39_CLOCK_ENIRCLK | TX39_CLOCK_ENUARTBCLK; 104 1.1 uch tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg); 105 1.1 uch 106 1.1 uch /* turn to pulse mode UARTB */ 107 1.1 uch txcom_pulse_mode(sc->sc_parent); 108 1.1 uch 109 1.1 uch #if not_required_yet 110 1.1 uch tx_intr_establish(tc, MAKEINTR(5, TX39_INTRSTATUS5_CARSTINT), 111 1.2 uch IST_EDGE, IPL_TTY, tx39ir_intr, sc); 112 1.1 uch tx_intr_establish(tc, MAKEINTR(5, TX39_INTRSTATUS5_POSCARINT), 113 1.2 uch IST_EDGE, IPL_TTY, tx39ir_intr, sc); 114 1.1 uch tx_intr_establish(tc, MAKEINTR(5, TX39_INTRSTATUS5_NEGCARINT), 115 1.2 uch IST_EDGE, IPL_TTY, tx39ir_intr, sc); 116 1.1 uch #endif 117 1.1 uch 118 1.1 uch #ifdef TX39IRDEBUG 119 1.1 uch tx39ir_dump(sc); 120 1.1 uch #endif 121 1.1 uch } 122 1.1 uch 123 1.3 shin #ifdef TX39IRDEBUG 124 1.1 uch void 125 1.2 uch tx39ir_dump(struct tx39ir_softc *sc) 126 1.1 uch { 127 1.1 uch tx_chipset_tag_t tc = sc->sc_tc; 128 1.1 uch txreg_t reg; 129 1.1 uch 130 1.1 uch reg = tx_conf_read(tc, TX39_IRCTRL1_REG); 131 1.4 uch #define ISSETPRINT(r, m) dbg_bitmask_print((u_int32_t)(r), \ 132 1.2 uch TX39_IRCTRL1_##m, #m) 133 1.1 uch ISSETPRINT(reg, CARDET); 134 1.1 uch ISSETPRINT(reg, TESTIR); 135 1.1 uch ISSETPRINT(reg, DTINVERT); 136 1.1 uch ISSETPRINT(reg, RXPWR); 137 1.1 uch ISSETPRINT(reg, ENSTATE); 138 1.1 uch ISSETPRINT(reg, ENCOMSM); 139 1.2 uch #undef ISSETPRINT 140 1.1 uch printf("baudval %d\n", TX39_IRCTRL1_BAUDVAL(reg)); 141 1.1 uch } 142 1.3 shin #endif 143 1.1 uch 144 1.3 shin #if not_required_yet 145 1.1 uch int 146 1.2 uch tx39ir_intr(void *arg) 147 1.1 uch { 148 1.2 uch return (0); 149 1.1 uch } 150 1.3 shin #endif 151