1 1.3 martin /* $NetBSD: tx39irreg.h,v 1.3 2008/04/28 20:23:21 martin Exp $ */ 2 1.1 uch 3 1.2 uch /*- 4 1.2 uch * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.2 uch * This code is derived from software contributed to The NetBSD Foundation 8 1.2 uch * by UCHIYAMA Yasushi. 9 1.2 uch * 10 1.1 uch * Redistribution and use in source and binary forms, with or without 11 1.1 uch * modification, are permitted provided that the following conditions 12 1.1 uch * are met: 13 1.1 uch * 1. Redistributions of source code must retain the above copyright 14 1.1 uch * notice, this list of conditions and the following disclaimer. 15 1.2 uch * 2. Redistributions in binary form must reproduce the above copyright 16 1.2 uch * notice, this list of conditions and the following disclaimer in the 17 1.2 uch * documentation and/or other materials provided with the distribution. 18 1.1 uch * 19 1.2 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2 uch * POSSIBILITY OF SUCH DAMAGE. 30 1.1 uch */ 31 1.1 uch /* 32 1.1 uch * Toshiba TX3912 IR module 33 1.1 uch */ 34 1.1 uch 35 1.1 uch #define TX39_IRCTRL1_REG 0x0a0 /* R/W */ 36 1.1 uch #define TX39_IRCTRL2_REG 0x0a4 /* W */ 37 1.1 uch #define TX39_IRTXHOLD_REG 0x0a8 /* W */ 38 1.1 uch 39 1.1 uch /* 40 1.1 uch * IR control 1 register 41 1.1 uch */ 42 1.1 uch #define TX39_IRCTRL1_CARDET 0x01000000 43 1.1 uch 44 1.1 uch #define TX39_IRCTRL1_BAUDVAL_SHIFT 16 45 1.1 uch #define TX39_IRCTRL1_BAUDVAL_MASK 0xff 46 1.2 uch #define TX39_IRCTRL1_BAUDVAL(cr) \ 47 1.2 uch (((cr) >> TX39_IRCTRL1_BAUDVAL_SHIFT) & \ 48 1.1 uch TX39_IRCTRL1_BAUDVAL_MASK) 49 1.2 uch #define TX39_IRCTRL1_BAUDVAL_SET(cr, val) \ 50 1.2 uch ((cr) | (((val) << TX39_IRCTRL1_BAUDVAL_SHIFT) & \ 51 1.1 uch (TX39_IRCTRL1_BAUDVAL_MASK << TX39_IRCTRL1_BAUDVAL_SHIFT))) 52 1.2 uch #define TX39_IRCTRL1_BAUDVAL_CLR(cr) \ 53 1.1 uch ((cr) &= ~(TX39_IRCTRL1_BAUDVAL_MASK << TX39_IRCTRL1_BAUDVAL_SHIFT)) 54 1.1 uch 55 1.1 uch #define TX39_IRCTRL1_TESTIR 0x00000010 /* don't set */ 56 1.1 uch #define TX39_IRCTRL1_DTINVERT 0x00000008 57 1.1 uch #define TX39_IRCTRL1_RXPWR 0x00000004 58 1.1 uch #define TX39_IRCTRL1_ENSTATE 0x00000002 59 1.1 uch #define TX39_IRCTRL1_ENCOMSM 0x00000001 60 1.1 uch 61 1.1 uch /* 62 1.1 uch * IR control 2 register 63 1.1 uch */ 64 1.1 uch /* 65 1.1 uch * period = (PER + 1) * (BAUDVAL + 1) * (1/3.6864MHz) 66 1.1 uch */ 67 1.1 uch #define TX39_IRCTRL2_PER_SHIFT 24 68 1.1 uch #define TX39_IRCTRL2_PER_MASK 0xff 69 1.2 uch #define TX39_IRCTRL2_PER_SET(cr, val) \ 70 1.2 uch ((cr) | (((val) << TX39_IRCTRL2_PER_SHIFT) & \ 71 1.1 uch (TX39_IRCTRL2_PER_MASK << TX39_IRCTRL2_PER_SHIFT))) 72 1.2 uch #define TX39_IRCTRL2_PER_CLR(cr) \ 73 1.1 uch ((cr) &= ~(TX39_IRCTRL2_PER_MASK << TX39_IRCTRL2_PER_SHIFT)) 74 1.1 uch 75 1.1 uch /* 76 1.1 uch * on time = ONTIME * (BAUDVAL + 1) * (1/3.6864MHz) 77 1.1 uch */ 78 1.1 uch #define TX39_IRCTRL2_ONTIME_SHIFT 16 79 1.1 uch #define TX39_IRCTRL2_ONTIME_MASK 0xff 80 1.2 uch #define TX39_IRCTRL2_ONTIME_SET(cr, val) \ 81 1.2 uch ((cr) | (((val) << TX39_IRCTRL2_ONTIME_SHIFT) & \ 82 1.1 uch (TX39_IRCTRL2_ONTIME_MASK << TX39_IRCTRL2_ONTIME_SHIFT))) 83 1.2 uch #define TX39_IRCTRL2_ONTIME_CLR(cr) \ 84 1.1 uch ((cr) &= ~(TX39_IRCTRL2_ONTIME_MASK << TX39_IRCTRL2_ONTIME_SHIFT)) 85 1.1 uch 86 1.1 uch /* 87 1.1 uch * delay time = (DELAYVAL + 1) * 7.8ms 88 1.1 uch */ 89 1.1 uch #define TX39_IRCTRL2_DELAYVAL_SHIFT 8 90 1.1 uch #define TX39_IRCTRL2_DELAYVAL_MASK 0xff 91 1.2 uch #define TX39_IRCTRL2_DELAYVAL_SET(cr, val) \ 92 1.2 uch ((cr) | (((val) << TX39_IRCTRL2_DELAYVAL_SHIFT) & \ 93 1.1 uch (TX39_IRCTRL2_DELAYVAL_MASK << TX39_IRCTRL2_DELAYVAL_SHIFT))) 94 1.2 uch #define TX39_IRCTRL2_DELAYVAL_CLR(cr) \ 95 1.1 uch ((cr) &= ~(TX39_IRCTRL2_DELAYVAL_MASK << TX39_IRCTRL2_DELAYVAL_SHIFT)) 96 1.1 uch 97 1.1 uch /* 98 1.1 uch * wait time = (DELAYVAL + 1) * (WAITVAL + 1) * 7.8ms 99 1.1 uch */ 100 1.1 uch #define TX39_IRCTRL2_WAITVAL_SHIFT 0 101 1.1 uch #define TX39_IRCTRL2_WAITVAL_MASK 0xff 102 1.2 uch #define TX39_IRCTRL2_WAITVAL_SET(cr, val) \ 103 1.2 uch ((cr) | (((val) << TX39_IRCTRL2_WAITVAL_SHIFT) & \ 104 1.1 uch (TX39_IRCTRL2_WAITVAL_MASK << TX39_IRCTRL2_WAITVAL_SHIFT))) 105 1.2 uch #define TX39_IRCTRL2_WAITVAL_CLR(cr) \ 106 1.1 uch ((cr) &= ~(TX39_IRCTRL2_WAITVAL_MASK << TX39_IRCTRL2_WAITVAL_SHIFT)) 107
Indexes created Thu Oct 30 03:10:01 GMT 2025