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tx39irreg.h revision 1.1.6.2 
      1 /*	$NetBSD: tx39irreg.h,v 1.1.6.2 2000/11/20 20:47:25 bouyer Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2000, by UCHIYAMA Yasushi
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. The name of the developer may NOT be used to endorse or promote products
     13  *    derived from this software without specific prior written permission.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     25  * SUCH DAMAGE.
     26  *
     27  */
     28 /*
     29  * Toshiba TX3912 IR module
     30  */
     31 
     32 #define TX39_IRCTRL1_REG	0x0a0 /* R/W */
     33 #define TX39_IRCTRL2_REG	0x0a4 /* W */
     34 #define TX39_IRTXHOLD_REG	0x0a8 /* W */
     35 
     36 /*
     37  * IR control 1 register
     38  */
     39 #define TX39_IRCTRL1_CARDET	0x01000000
     40 
     41 #define TX39_IRCTRL1_BAUDVAL_SHIFT	16
     42 #define TX39_IRCTRL1_BAUDVAL_MASK	0xff
     43 #define TX39_IRCTRL1_BAUDVAL(cr) \
     44 	(((cr) >> TX39_IRCTRL1_BAUDVAL_SHIFT) & \
     45 	TX39_IRCTRL1_BAUDVAL_MASK)
     46 #define TX39_IRCTRL1_BAUDVAL_SET(cr, val) \
     47 	((cr) | (((val) << TX39_IRCTRL1_BAUDVAL_SHIFT) & \
     48 	(TX39_IRCTRL1_BAUDVAL_MASK << TX39_IRCTRL1_BAUDVAL_SHIFT)))
     49 #define TX39_IRCTRL1_BAUDVAL_CLR(cr) \
     50 	((cr) &= ~(TX39_IRCTRL1_BAUDVAL_MASK << TX39_IRCTRL1_BAUDVAL_SHIFT))
     51 
     52 #define TX39_IRCTRL1_TESTIR	0x00000010 /* don't set */
     53 #define TX39_IRCTRL1_DTINVERT	0x00000008
     54 #define TX39_IRCTRL1_RXPWR	0x00000004
     55 #define TX39_IRCTRL1_ENSTATE	0x00000002
     56 #define TX39_IRCTRL1_ENCOMSM	0x00000001
     57 
     58 /*
     59  * IR control 2 register
     60  */
     61 /*
     62  * period = (PER + 1) * (BAUDVAL + 1) * (1/3.6864MHz)
     63  */
     64 #define TX39_IRCTRL2_PER_SHIFT		24
     65 #define TX39_IRCTRL2_PER_MASK		0xff
     66 #define TX39_IRCTRL2_PER_SET(cr, val) \
     67 	((cr) | (((val) << TX39_IRCTRL2_PER_SHIFT) & \
     68 	(TX39_IRCTRL2_PER_MASK << TX39_IRCTRL2_PER_SHIFT)))
     69 #define TX39_IRCTRL2_PER_CLR(cr) \
     70 	((cr) &= ~(TX39_IRCTRL2_PER_MASK << TX39_IRCTRL2_PER_SHIFT))
     71 
     72 /*
     73  * on time = ONTIME * (BAUDVAL + 1) * (1/3.6864MHz)
     74  */
     75 #define TX39_IRCTRL2_ONTIME_SHIFT	16
     76 #define TX39_IRCTRL2_ONTIME_MASK	0xff
     77 #define TX39_IRCTRL2_ONTIME_SET(cr, val) \
     78 	((cr) | (((val) << TX39_IRCTRL2_ONTIME_SHIFT) & \
     79 	(TX39_IRCTRL2_ONTIME_MASK << TX39_IRCTRL2_ONTIME_SHIFT)))
     80 #define TX39_IRCTRL2_ONTIME_CLR(cr) \
     81 	((cr) &= ~(TX39_IRCTRL2_ONTIME_MASK << TX39_IRCTRL2_ONTIME_SHIFT))
     82 
     83 /*
     84  * delay time = (DELAYVAL + 1) * 7.8ms
     85  */
     86 #define TX39_IRCTRL2_DELAYVAL_SHIFT	8
     87 #define TX39_IRCTRL2_DELAYVAL_MASK	0xff
     88 #define TX39_IRCTRL2_DELAYVAL_SET(cr, val) \
     89 	((cr) | (((val) << TX39_IRCTRL2_DELAYVAL_SHIFT) & \
     90 	(TX39_IRCTRL2_DELAYVAL_MASK << TX39_IRCTRL2_DELAYVAL_SHIFT)))
     91 #define TX39_IRCTRL2_DELAYVAL_CLR(cr) \
     92 	((cr) &= ~(TX39_IRCTRL2_DELAYVAL_MASK << TX39_IRCTRL2_DELAYVAL_SHIFT))
     93 
     94 /*
     95  * wait time = (DELAYVAL + 1) * (WAITVAL + 1) * 7.8ms
     96  */
     97 #define TX39_IRCTRL2_WAITVAL_SHIFT	0
     98 #define TX39_IRCTRL2_WAITVAL_MASK	0xff
     99 #define TX39_IRCTRL2_WAITVAL_SET(cr, val) \
    100 	((cr) | (((val) << TX39_IRCTRL2_WAITVAL_SHIFT) & \
    101 	(TX39_IRCTRL2_WAITVAL_MASK << TX39_IRCTRL2_WAITVAL_SHIFT)))
    102 #define TX39_IRCTRL2_WAITVAL_CLR(cr) \
    103 	((cr) &= ~(TX39_IRCTRL2_WAITVAL_MASK << TX39_IRCTRL2_WAITVAL_SHIFT))
    104